Hi
arch/powerpc/sysdev/fsl_lbc.c driver claims that it is compatible with
fsl,pq2-localbus and fsl,pq2pro-localbus
arch/powerpc/sysdev/fsl_lbc.c driver requires irq configured in device
tree since very old times (commit 3ab8f2a2 from 2.6.37 times)
None of in-tree dts files that have either fsl,p
In hotplug case, function pcibios_add_pci_devices() is called to
rescan the specified PCI bus, which might not have any child devices.
Access to the PCI bus's child device node will cause kernel crash
without exception. The patch adds condition of skipping scanning
PCI bus without child devices, in
We might not get some PCI slot information (e.g. power status)
immediately by OPAL API. Instead, opal_pci_poll() need to be called
for the required information.
The patch introduces pnv_pci_poll(), which bases on original
pnv_eeh_poll(), to cover the above case
Signed-off-by: Gavin Shan
---
arc
The patch intends to add standalone driver to support PCI hotplug
for PowerPC PowerNV platform, which runs on top of skiboot firmware.
The firmware identified hotpluggable slots and marked their device
tree node with proper "ibm,slot-pluggable" and "ibm,reset-by-firmware".
The driver simply scans d
The patch moves pcibios_find_pci_bus() to PPC kerenl directory so
that it can be reused by hotplug code for pSeries and PowerNV
platform at the same time.
Signed-off-by: Gavin Shan
Acked-by: Benjamin Herrenschmidt
---
arch/powerpc/kernel/pci-hotplug.c | 36 +
For PowerNV platform, running on top of skiboot, all PE level reset
should be routed to firmware if the bridge of the PE primary bus has
device-node property "ibm,reset-by-firmware". Otherwise, the kernel
has to issue hot reset on PE's primary bus despite the requested
reset types, which is the beh
The patch exports two functions, which base on corresponding OPAL
APIs to retrieve PCI slot status. Those functions are going to be
used by PCI hotplug module in subsequent patches:
pnv_pci_get_power_status() opal_pci_get_power_status()
pnv_pci_get_presence_status() opal_pci_get_presenc
Function pnv_pci_reset_secondary_bus() is used to reset specified
PCI bus, which is leaded by root complex or PCI bridge. That means
the function shouldn't be called on PCI root bus and the patch
removes the logic for that case.
Also, some adapters may require fundamental reset to reload their
fir
The patchset was built based on patchset "powerpc/powernv: Simplify EEH
implementation", which can be found from:
https://patchwork.ozlabs.org/patch/439956/
The patchset corresponds to skiboot changes, which manages PCI slots
in a unified way: OPAL APIs used to do slot reset, power management,
pr
Signed-off-by: Denis Kirjanov
---
arch/powerpc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 22b0940..5084bdc 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -126,7 +126,7 @@ config PPC
select
Signed-off-by: Denis Kirjanov
---
arch/powerpc/net/Makefile| 2 +-
arch/powerpc/net/{bpf_jit_64.S => bpf_jit_asm.S} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename arch/powerpc/net/{bpf_jit_64.S => bpf_jit_asm.S} (100%)
diff --git a/arch/powerpc/net/Makefile b
Signed-off-by: Denis Kirjanov
---
arch/powerpc/net/bpf_jit.h | 17 +
arch/powerpc/net/bpf_jit_comp.c | 14 +-
2 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index 2d5e715..889fd19 100644
---
Use helpers from the asm-compat.h to wrap up assembly mnemonics
Signed-off-by: Denis Kirjanov
---
arch/powerpc/net/bpf_jit.h | 47 ++-
arch/powerpc/net/bpf_jit_64.S | 70 -
arch/powerpc/net/bpf_jit_comp.c | 32 ++-
Signed-off-by: Denis Kirjanov
---
arch/powerpc/include/asm/ppc-opcode.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 03cd858..2eadde0 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc
This patch series enables BPF JIT on ppc32. There are relatevily
few chnages in the code to make it work.
All test_bpf tests passed both on 7447a and P2041-based machines.
Changelog:
v1 - > v2: Reordered Kconfig patch in the series
Denis Kirjanov (6):
ppc: bpf: add required compatibility m
Signed-off-by: Denis Kirjanov
---
arch/powerpc/include/asm/asm-compat.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/include/asm/asm-compat.h
b/arch/powerpc/include/asm/asm-compat.h
index 21be8ae..dc85dcb 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/power
On Tue, 2015-02-17 at 09:38 +0530, Preeti U Murthy wrote:
> On 02/17/2015 07:28 AM, Michael Ellerman wrote:
> > On Sat, 2015-01-31 at 09:44 +0530, Preeti U Murthy wrote:
> >> These duties include do_timer to update jiffies and broadcast wakeups on
> >> those
> >> platforms which do not have an ext
On 02/17/2015 07:28 AM, Michael Ellerman wrote:
> On Sat, 2015-01-31 at 09:44 +0530, Preeti U Murthy wrote:
>> These duties include do_timer to update jiffies and broadcast wakeups on
>> those
>> platforms which do not have an external device to handle wakeup of cpus from
>> deep
>> idle states.
On Thu, Dec 04, 2014 at 04:54:43PM +1100, Gavin Shan wrote:
Please ignore this one. I'll rebase the repost new revision later.
Thanks,
Gavin
>The series of patches depends on the OPAL firmware changes. If the firmware
>doesn't have the changes, PCI hotplug slots won't be populated properly.
>Oth
On Thu, Dec 04, 2014 at 04:50:50PM +1100, Gavin Shan wrote:
Please ignore this one. I'll rebase and send out a new revision
shortly.
Thanks,
Gavin
>The patchset corresponds to skiboot changes, which manages PCI slots
>in a unified way: OPAL APIs used to do slot reset, power management,
>presence
On Sat, 2015-01-31 at 09:44 +0530, Preeti U Murthy wrote:
> These duties include do_timer to update jiffies and broadcast wakeups on those
> platforms which do not have an external device to handle wakeup of cpus from
> deep
> idle states. The handover of these duties is not robust against a cpu o
On Mon, 2015-02-16 at 09:46 -0600, Emil Medve wrote:
> From: Geoff Thorpe
>
> Change-Id: I075944acf740dbaae861104c17a9ff7247dec1be
> Signed-off-by: Geoff Thorpe
Remove Change-Id.
Provide a description of what BMan is.
> diff --git a/drivers/soc/freescale/Kconfig b/drivers/soc/freescale/Kconfig
On Mon, Feb 16, 2015 at 11:14:27AM -0200, casca...@linux.vnet.ibm.com wrote:
>On Fri, Feb 13, 2015 at 03:54:55PM +1100, Gavin Shan wrote:
>> VFIO PCI infrastructure depends on pci_reset_function() to do reset on
>> PCI devices so that they would be in clean state when host or guest grabs
>> them. U
On Mon, Feb 09, 2015 at 09:40:19PM +0100, Andi Kleen wrote:
> > I'll NAK any external 'download area' (and I told that Andi
> > before): tools/perf/event-tables/ or so is a good enough
> > 'download area' with fast enough update cycles.
>
> The proposal was to put it on kernel.org, similar to ho
> Von: linux-crypto-ow...@vger.kernel.org
> [linux-crypto-ow...@vger.kernel.org]" im Auftrag von "Segher
> Boessenkool [seg...@kernel.crashing.org]
> Gesendet: Montag, 16. Februar 2015 15:37
> An: David Laight
> Cc: Markus Stockhausen; linux-cry...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.or
On 02/11/2015 05:55 AM, Jeremy Kerr wrote:
> For epapr-style boot, we may be little-endian. This change implements
> the proper conversion for fdt*_to_cpu and cpu_to_fdt*. We also need the
> full cpu_to_* and *_to_cpu macros for this.
>
> Signed-off-by: Jeremy Kerr
> Acked-by: Benjamin Herrenschm
On 02/16/2015 08:13 AM, Denis Kirjanov wrote:
...
Well, I don't see significant challenges to enable eBPF on ppc64 in the future.
I'll start working on it after I get this merged
Cool, awesome!
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.o
From: Geoff Thorpe
Change-Id: I59de17c040cdd304f86306336fcf89f130f7db2d
Signed-off-by: Geoff Thorpe
---
arch/powerpc/platforms/85xx/corenet_generic.c | 8 +++-
arch/powerpc/platforms/85xx/p1023_rdb.c | 8 +++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/po
From: Geoff Thorpe
Change-Id: I7eea7aea8a58ad0c28451b70801c0d101e88d263
Signed-off-by: Geoff Thorpe
---
drivers/soc/freescale/Kconfig| 7 +++
drivers/soc/freescale/Makefile | 1 +
drivers/soc/freescale/bman_api.c | 19 ++
drivers/soc/freescale/bman_debugfs.c | 119 +++
From: Geoff Thorpe
Change-Id: I59a75a91b289193b5ab1d30a08f60119dc4d7568
Signed-off-by: Geoff Thorpe
---
drivers/soc/freescale/Kconfig|7 +
drivers/soc/freescale/Makefile |1 +
drivers/soc/freescale/qman_api.c | 58 ++
drivers/soc/freescale/qman_debugfs.c | 1326 +
From: Geoff Thorpe
Change-Id: If1b44bb013addc1e855c73a4e6ff74bc8b6e4829
Signed-off-by: Geoff Thorpe
---
drivers/soc/freescale/Kconfig| 26
drivers/soc/freescale/Makefile | 8 +-
drivers/soc/freescale/bman.c | 16 +--
drivers/soc/freescale/bman_api.c
From: Geoff Thorpe
Change-Id: I314d36d94717cfc34053b6212899f71cb729d16c
Signed-off-by: Geoff Thorpe
---
drivers/soc/freescale/Kconfig | 26 +-
drivers/soc/freescale/Makefile | 4 +
drivers/soc/freescale/bman_test.c | 2 +-
drivers/s
v2: Moved out of staging into soc/freescale
Hello,
This is the se attempt to publish the . They are
not to be applied yet.
These are the Freescale DPAA B/QMan drivers. At this stage, this is more or less
the drivers from the Freescale PowerPC SDK roughly squashed and split in a
sequence o
From: Geoff Thorpe
Change-Id: I59de17c040cdd304f86306336fcf89f130f7db2d
Signed-off-by: Geoff Thorpe
---
arch/powerpc/Kconfig | 5 +
arch/powerpc/configs/mpc85xx_defconfig| 1 +
arch/powerpc/configs/mpc85xx_smp_defconfig| 1 +
arch/powerpc/platforms/85
From: Hai-Ying Wang
Change-Id: I863d5c15c7f35f9de4ea3d985e4ff467167924b7
Signed-off-by: Hai-Ying Wang
---
drivers/soc/freescale/bman_portal.c | 45 -
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/freescale/bman_portal.c
b/drivers/
From: Hai-Ying Wang
Change-Id: Ica4d1b2b0fd3c3ae5e043663febd9f4cb7c762cf
Signed-off-by: Hai-Ying Wang
---
drivers/soc/freescale/qman_portal.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/drivers/soc/freescale/qman_portal.c
b/drivers/soc/freescale/q
On Mon, Feb 16, 2015 at 2:13 AM, Denis Kirjanov wrote:
> On 2/15/15, Daniel Borkmann wrote:
>> On 02/15/2015 07:06 PM, Denis Kirjanov wrote:
>>> This patch series enables BPF JIT on ppc32. There are relatevily
>>> few chnages in the code to make it work.
>>>
>>> All test_bpf tests passed both on
On Mon, Feb 16, 2015 at 02:19:50PM +, David Laight wrote:
> From: Markus Stockhausen
> > 4K AES tables for big endian
>
> I can't help feeling that you could give more information about how the
> values are generated.
... and an explanation of why this does not open you up to a timing attack
From: Markus Stockhausen
> 4K AES tables for big endian
I can't help feeling that you could give more information about how the
values are generated.
...
> + * These big endian AES encryption/decryption tables are designed to be
> simply
> + * accessed by a combination of rlwimi/lwz instruction
On Fri, Feb 13, 2015 at 03:54:55PM +1100, Gavin Shan wrote:
> VFIO PCI infrastructure depends on pci_reset_function() to do reset on
> PCI devices so that they would be in clean state when host or guest grabs
> them. Unfortunately, the function doesn't work (or not well) on some PCI
> devices that
[PATCH v1 7/7] AES for PPC/SPE - kernel config
Integrate the module into the kernel configuration
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile
index a07e763..1698fb9 100644
--- a/arch/powerpc/crypto/Makefile
+++ b/arch/powerpc/crypto
[PATCH v1 6/7] AES for PPC/SPE - glue code
Integrate the assembler modules into the kernel crypto
framework. Take care to avoid long intervals of disabled
preemption.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes_spe_glue.c
b/arch/powerpc/crypto/aes_spe_glue.c
new file
[PATCH v1 2/7] AES for PPC/SPE - aes tables
4K AES tables for big endian
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-tab-4k.S b/arch/powerpc/crypto/aes-tab-4k.S
new file mode 100644
index 000..6bc1755
--- /dev/null
+++ b/arch/powerpc/crypto/aes-tab-4k.S
@@ -0,0 +1
[PATCH v1 4/7] AES for PPC/SPE - key handling
Key generation for big endian core routines.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-spe-keys.S
b/arch/powerpc/crypto/aes-spe-keys.S
new file mode 100644
index 000..55b258c
--- /dev/null
+++ b/arch/powerpc/crypto/
[PATCH v1 5/7] AES for PPC/SPE - ECB/CBC/CTR/XTS modes
The assembler block cipher module that controls the core
AES functions.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-spe-modes.S
b/arch/powerpc/crypto/aes-spe-modes.S
new file mode 100644
index 000..1141841
--
[PATCH v1 3/7] AES for PPC/SPE - assembler core
The assembler AES encryption and decryption core routines.
Implemented & optimized for big endian. Nevertheless they
work on little endian too.
For most efficient reuse in (higher level) block cipher
routines they are implemented as "fast" call mod
[PATCH v1 1/7] AES for PPC/SPE - register defines
Define some register aliases for better readability.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-spe-regs.h
b/arch/powerpc/crypto/aes-spe-regs.h
new file mode 100644
index 000..30d217b
--- /dev/null
+++ b/arch/pow
[PATCH v1 0/7] AES for PPC/SPE
The following patches add support for 64bit accelerated AES
calculation on PPC processors with SPE instruction set. Besides
the AES core module it implements ECB/CBC/CTR/XTS as block
ciphers. The implementation takes care of the following
constraints:
- save SPE re
Drop unused fsl_mpic_primary_get_version(), mpic_set_clk_ratio(),
mpic_set_serial_int().
Signed-off-by: Arseny Solokha
---
arch/powerpc/include/asm/mpic.h | 16
arch/powerpc/sysdev/mpic.c | 35 ---
2 files changed, 51 deletions(-)
diff --git
Drop ucc_slow_poll_transmitter_now() which has no users.
Signed-off-by: Arseny Solokha
---
arch/powerpc/include/asm/ucc_slow.h | 13 -
arch/powerpc/sysdev/qe_lib/ucc_slow.c | 5 -
2 files changed, 18 deletions(-)
diff --git a/arch/powerpc/include/asm/ucc_slow.h
b/arch/powerp
Drop planetcore_set_serial_speed() which had no users since its inception.
Signed-off-by: Arseny Solokha
---
arch/powerpc/boot/planetcore.c | 33 -
arch/powerpc/boot/planetcore.h | 3 ---
2 files changed, 36 deletions(-)
diff --git a/arch/powerpc/boot/planetcore
Drop unused static procedure which doesn't have callers within its
translation unit.
Signed-off-by: Arseny Solokha
Cc: Alexander Graf
Cc: Gleb Natapov
Cc: Paolo Bonzini
---
arch/powerpc/kvm/mpic.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/powerpc/kvm/mpic.c b/arch/powerpc/k
This series removes unused functions from powerpc tree that I've been
able to discover.
Arseny Solokha (4):
powerpc/boot: drop planetcore_set_serial_speed
kvm/ppc/mpic: drop unused IRQ_testbit
powrepc/qe: drop unused ucc_slow_poll_transmitter_now
powerpc/mpic: remove unused functions
arc
This moves iommu_table creation to the beginning. This is a mechanical
patch.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 31 +--
drivers/vfio/vfio_iommu_spapr_tce.c | 4 +++-
2 files changed, 20 insertions(+), 15 deletio
The iommu_free_table helper release memory it is using (the TCE table and
@it_map) and release the iommu_table struct as well. We might not want
the very last step as we store iommu_table in parent structures.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h | 1 +
arch/
This adds multi-level TCE tables support to pnv_pci_ioda2_create_table()
and pnv_pci_ioda2_free_table() callbacks.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h | 4 +
arch/powerpc/platforms/powernv/pci-ioda.c | 125 +++---
arch/power
The existing implementation accounts the whole DMA window in
the locked_vm counter which is going to be even worse with multiple
containers and huge DMA windows.
This introduces 2 ioctls to register/unregister DMA memory which
receive user space address and size of the memory region which
needs to
The previous patch introduced iommu_table_ops::exchange() callback
which effectively disabled VFIO on pseries. This implements exchange()
for pseries/lpar so VFIO can work in nested guests.
Since exchange() callback returns an old TCE, it has to call H_GET_TCE
for every TCE being put to the table
Signed-off-by: Alexey Kardashevskiy
---
drivers/vfio/vfio_iommu_spapr_tce.c | 62 +++--
1 file changed, 38 insertions(+), 24 deletions(-)
diff --git a/drivers/vfio/vfio_iommu_spapr_tce.c
b/drivers/vfio/vfio_iommu_spapr_tce.c
index fdcc04c..4ff8289 100644
--- a/dr
At the moment the iommu_table struct has a set_bypass() which enables/
disables DMA bypass on IODA2 PHB. This is exposed to POWERPC IOMMU code
which calls this callback when external IOMMU users such as VFIO are
about to get over a PHB.
The set_bypass() callback is not really an iommu_table functi
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a powerpc_iommu container
for TCE tables. Right now just one table is supported.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h| 18 +++--
arch/pow
This extends powerpc_iommu_ops by a set of callbacks to support dynamic
DMA windows management.
query() returns IOMMU capabilities such as default DMA window address and
supported number of DMA windows and TCE table levels.
create_table() creates a TCE table with specific parameters. For now
it r
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.
Another problem this patch is addressing is the use of pool locks for
external IOMMU users such a
This uses new helpers to remove the default TCE table if the ownership is
being taken and create it otherwise. So once an external user (such as
VFIO) obtained the ownership over a group, it does not have any DMA
windows, neither default 32bit not bypass window. The external user is
expected to unp
The pnv_pci_ioda_tce_invalidate() helper invalidates TCE cache. It is
supposed to be called on IODA1/2 and not called on p5ioc2. It receives
start and end host addresses of TCE table. This approach makes it possible
to get pnv_pci_ioda_tce_invalidate() unintentionally called on p5ioc2.
Another issu
This replaces multiple calls of kzalloc_node() with a new
iommu_table_alloc() helper. Right now it calls kzalloc_node() but
later it will be modified to allocate a powerpc_iommu struct with
a single iommu_table in it.
Later the helper will allocate a powerpc_iommu struct which embeds
the iommu tab
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where they really belong to.
This adds the requirement for @it_ops to be initialized before calling
iommu_init_table() to m
This adds missing locks in iommu_take_ownership()/
iommu_release_ownership().
This marks all pages busy in iommu_table::it_map in order to catch
errors if there is an attempt to use this table while ownership over it
is taken.
This only clears TCE content if there is no page marked busy in it_map
There moves locked pages accounting to helpers.
Later they will be reused for Dynamic DMA windows (DDW).
This reworks debug messages to show the current value and the limit.
This stores the locked pages number in the container so when unlocking
the iommu table pointer won't be needed. This does n
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential not to put bits which are not
implied in the direction flag.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David
This is a pretty mechanical patch to make next patches simpler.
New tce_iommu_unuse_page() helper does put_page() now but it might skip
that after the memory registering patch applied.
As we are here, this removes unnecessary checks for a value returned
by pfn_to_page() as it cannot possibly retu
This adds create/remove window ioctls to create and remove DMA windows.
sPAPR defines a Dynamic DMA windows capability which allows
para-virtualized guests to create additional DMA windows on a PCI bus.
The existing linux kernels use this new window to map the entire guest
memory and switch to the
The existing implementation accounts the whole DMA window in
the locked_vm counter which is going to be even worse with multiple
containers and huge DMA windows.
This introduces 2 ioctls to register/unregister DMA memory which
receive user space address and size of a memory region which
needs to b
At the moment DMA map/unmap requests are handled irrespective to
the container's state. This allows the user space to pin memory which
it might not be allowed to pin.
This adds checks to MAP/UNMAP that the container is enabled, otherwise
-EPERM is returned.
Signed-off-by: Alexey Kardashevskiy
--
This is a part of moving DMA window programming to an iommu_ops
callback.
This is a mechanical patch.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 84 ---
1 file changed, 56 insertions(+), 28 deletions(-)
diff --git a/arch/powe
This changes few functions to receive a powerpc_iommu pointer
rather than PE as they are going to be a part of upcoming
powerpc_iommu_ops callback set.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 13 -
1 file changed, 8 insertions(+), 5 deletio
This is a part of moving TCE table allocation into an iommu_ops
callback to support multiple IOMMU groups per one VFIO container.
This is a mechanical patch.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 88 +++
1 file changed, 6
This clears the TCE table when a container is being closed as this is
a good thing to leave the table clean before passing the ownership
back to the host kernel.
Signed-off-by: Alexey Kardashevskiy
---
drivers/vfio/vfio_iommu_spapr_tce.c | 14 +++---
1 file changed, 11 insertions(+), 3 d
This enables PAPR defined feature called Dynamic DMA windows (DDW).
Each Partitionable Endpoint (IOMMU group) has a separate DMA window on
a PCI bus where devices are allows to perform DMA. By default there is
1 or 2GB window allocated at the host boot time and these windows are
used when an IOMM
This makes use of the it_page_size from the iommu_table struct
as page size can differ.
This replaces missing IOMMU_PAGE_SHIFT macro in commented debug code
as recently introduced IOMMU_PAGE_XXX macros do not include
IOMMU_PAGE_SHIFT.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted access to physical memory between
the end of the actual page and the end of the aligned up TCE page.
Since compoun
This moves page pinning (get_user_pages_fast()/put_page()) code out of
the platform IOMMU code and puts it to VFIO IOMMU driver where it belongs
to as the platform code does not deal with page pinning.
This makes iommu_take_ownership()/iommu_release_ownership() deal with
the IOMMU table bitmap onl
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