From: Igal Liberman
Describe the PHY topology for all configurations supported by each board
Based on prior work by Andy Fleming
Signed-off-by: Igal Liberman
Signed-off-by: Shruti Kanetkar
Signed-off-by: Emil Medve
---
v2: Remove 'Change-Id'
arch/powerpc/boot/dts/b4860qds.dts| 6
In order to enable SRIOV on PowerNV platform, the PF's IOV BAR needs to be
adjusted:
1. size expanded
2. aligned to M64BT size
This patch documents this change on the reason and how.
[bhelgaas: reformat, clarify, expand]
Signed-off-by: Wei Yang
---
.../powerpc/pci_iov_resource_on_power
In struct pci_dn, the pcidev field is assigned but not used, so remove it.
Signed-off-by: Wei Yang
Acked-by: Gavin Shan
---
arch/powerpc/include/asm/pci-bridge.h |1 -
arch/powerpc/platforms/powernv/pci-ioda.c |1 -
2 files changed, 2 deletions(-)
diff --git a/arch/powerpc/include/
When IOV BAR is big, each is covered by 4 M64 windows. This leads to
several VF PE sits in one PE in terms of M64.
Group VF PEs according to the M64 allocation.
[bhelgaas: use dev_printk() when possible]
Signed-off-by: Wei Yang
---
arch/powerpc/include/asm/pci-bridge.h |2 +-
arch/powe
M64 aperture size is limited on PHB3. When the IOV BAR is too big, this
will exceed the limitation and failed to be assigned.
Introduce a different mechanism based on the IOV BAR size:
- if IOV BAR size is smaller than 64MB, expand to total_pe
- if IOV BAR size is bigger than 64MB, roundup p
On PowerNV platform, resource position in M64 BAR implies the PE# the
resource belongs to. In some cases, adjustment of a resource is necessary
to locate it to a correct position in M64 BAR .
This patch adds pnv_pci_vf_resource_shift() to shift the 'real' PF IOV BAR
address according to an offset.
Implement pcibios_iov_resource_alignment() on powernv platform.
On PowerNV platform, there are 3 cases for the IOV BAR:
1. initial state, the IOV BAR size is multiple times of VF BAR size
2. after expanded, the IOV BAR size is expanded to meet the M64 segment size
3. sizing stage, the IOV BAR is t
On PHB3, PF IOV BAR will be covered by M64 BAR to have better PE isolation.
M64 BAR is a type of hardware resource in PHB3, which could map a range of
MMIO to PE numbers on powernv platform. And this range is divided equally
by the number of total_pe with each divided range mapping to a PE number.
Previously the iommu_table had the same lifetime as a struct pnv_ioda_pe
and was embedded in it. The pnv_ioda_pe was assigned to a PE on the bootup
stage. Since PEs are based on the hardware layout which is static in the
system, they will never get released. This means the iommu_table in the
pnv_io
Flag PCI_REASSIGN_ALL_RSRC is used to ignore resources information setup by
firmware, so that kernel would re-assign all resources of pci devices.
On powerpc arch, this happens in a header fixup function
pcibios_fixup_resources(), which will clean up the resources if this flag
is set. This works f
When sizing and assigning resources, we divide the resources into two
lists: the requested list and the additional list. We don't consider the
alignment of additional VF(n) BAR space.
This is because the alignment required for the VF(n) BAR space is the size
of an individual VF BAR, not the size
Per the SR-IOV spec r1.1, sec 3.3.14, the required alignment of a PF's IOV
BAR is the size of an individual VF BAR, and the size consumed is the
individual VF BAR size times NumVFs.
The PowerNV platform has additional alignment requirements to help support
its Partitionable Endpoint device isolati
VFs are dynamically created when a driver enables them. On some platforms,
like PowerNV, special resources are necessary to enable VFs.
Add platform hooks for enabling and disabling VFs.
Signed-off-by: Wei Yang
Acked-by: Bjorn Helgaas
---
drivers/pci/iov.c | 19 +++
1 file c
On PowerNV, some resource reservation is needed for SR-IOV VFs that don't
exist at the bootup stage. To do the match between resources and VFs, the
code need to get the VF's BDF in advance.
Rename virtfn_bus() and virtfn_devfn() to pci_iov_virtfn_bus() and
pci_iov_virtfn_devfn() and export them.
An SR-IOV device can change its First VF Offset and VF Stride based on the
values of ARI Capable Hierarchy and NumVFs. The number of buses required
for all VFs is determined by NumVFs, First VF Offset, and VF Stride (see
SR-IOV spec r1.1, sec 2.1.2).
Previously pci_iov_bus_range() computed how ma
The First VF Offset and VF Stride fields depend on the NumVFs setting, so
refresh the cached fields in struct pci_sriov when updating NumVFs. See
the SR-IOV spec r1.1, sec 3.3.9 and 3.3.10.
[bhelgaas: changelog, remove kernel-doc comment marker]
Signed-off-by: Wei Yang
Acked-by: Bjorn Helgaas
-
From: Bjorn Helgaas
Most of PCI uses "res = &dev->resource[i]", not "res = dev->resource + i".
Use that style in iov.c also.
No functional change.
Signed-off-by: Bjorn Helgaas
Acked-by: Wei Yang
---
drivers/pci/iov.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --gi
Currently we don't store the individual VF BAR size. We calculate it when
needed by dividing the PF's IOV resource size (which contains space for
*all* the VFs) by total_VFs or by reading the BAR in the SR-IOV capability
again.
Keep the individual VF BAR size in struct pci_sriov.barsz[], add
pci_
When we size VF BAR0, VF BAR1, etc., from the SR-IOV Capability of a PF, we
learn the alignment requirement and amount of space consumed by a single
VF. But when VFs are enabled, *each* of the NumVFs consumes that amount of
space, so the total size of the PF resource is "VF BAR size * NumVFs".
Ad
From: Bjorn Helgaas
If we don't have space for all the bus numbers required to enable VFs,
print the largest bus number required and the range available.
No functional change; improved error message only.
Signed-off-by: Bjorn Helgaas
Acked-by: Wei Yang
---
drivers/pci/iov.c |7 +--
1
Michael Ellerman writes:
> The powernv code has some conditional support for running on bare metal
> machines that have no OPAL firmware, but provide RTAS.
>
> No released machines ever supported that, and even in the lab it was
> just a transitional hack in the days when OPAL was still being
> d
The PCI config accessors previously relied on device_node. Unfortunately,
VFs don't have a corresponding device_node, so change the accessors to use
pci_dn instead.
[bhelgaas: changelog]
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/eeh-powernv.c | 14 +-
arch/powerpc/platf
From: Gavin Shan
pci_dn is the extension of PCI device node and is created from device node.
Unfortunately, VFs are enabled dynamically by PF's driver and they don't
have corresponding device nodes, and pci_dn. Refactor pci_dn to support
VFs:
* pci_dn is organized as a hierarchy tree. VF's
This patchset enables the SRIOV on POWER8.
The general idea is put each VF into one individual PE and allocate required
resources like MMIO/DMA/MSI. The major difficulty comes from the MMIO
allocation and adjustment for PF's IOV BAR.
On P8, we use M64BT to cover a PF's IOV BAR, which could make a
Now that we have ported the calls to iommu_init_early_dart to always
supply a pci_controller_ops struct, we can safely drop the check.
Signed-off-by: Daniel Axtens
---
arch/powerpc/sysdev/dart_iommu.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/machdep.h| 2 --
arch/powerpc/include/asm/pci-bridge.h | 14 --
arch/powerpc/kernel/pci-common.c | 5 -
arch/powerpc/sysdev/dart_iommu.c | 3 ---
4 files changed, 4 insertions(+), 20 deletions(-)
diff --gi
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/machdep.h| 1 -
arch/powerpc/include/asm/pci-bridge.h | 9 -
arch/powerpc/kernel/pci-common.c | 5 -
arch/powerpc/sysdev/dart_iommu.c | 2 --
4 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/arch/po
This also moves back the defines, as explained in the commit that
created the shim.
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/machdep.h| 1 -
arch/powerpc/include/asm/pci-bridge.h | 16
arch/powerpc/include/asm/pci.h| 5 +
arch/powerpc/kernel/pc
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/machdep.h| 4
arch/powerpc/include/asm/pci-bridge.h | 11 ---
arch/powerpc/kernel/pci-common.c | 7 +--
3 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/include/asm/machdep.h
b/arch/
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/machdep.h| 3 ---
arch/powerpc/include/asm/pci-bridge.h | 16
arch/powerpc/kernel/pci-common.c | 9 -
3 files changed, 8 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/include/asm/machdep.h
b
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/machdep.h| 3 ---
arch/powerpc/include/asm/pci-bridge.h | 18 --
arch/powerpc/kernel/pci-common.c | 12 +++-
3 files changed, 11 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/include/asm/machde
This moves the Cell platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
This depends on the patch to drop celleb support:
http://patchwork.ozlabs.org/patch/451730/
Signed-off-by: Daniel Axtens
---
arch/powerpc/platforms/cell/cell.h | 24 ++
This moves the setup out of swiotlb's subsys init call, and into an
fsl_pci.c is the only thing that checks the ppc_swiotlb_enable global,
so we can be confident that patching it will cover all the PCI
implementations affected by the changes to dma-swiotlb.c.
Signed-off-by: Daniel Axtens
---
ar
This moves the Maple platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens
---
arch/powerpc/platforms/maple/maple.h | 2 ++
arch/powerpc/platforms/maple/pci.c | 4
arch/powerpc/platforms/maple/setup.c | 2 +-
3 file
This moves the PaSemi platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens
---
arch/powerpc/platforms/pasemi/iommu.c | 6 --
arch/powerpc/platforms/pasemi/pasemi.h | 1 +
arch/powerpc/platforms/pasemi/pci.c| 5 ++
This moves the PowerNV platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens
---
arch/powerpc/platforms/powernv/pci-ioda.c | 7 ---
arch/powerpc/platforms/powernv/pci-p5ioc2.c | 1 +
arch/powerpc/platforms/powernv/pc
This moves the pSeries platform to use the pci_controller_ops structure,
rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens
---
arch/powerpc/platforms/pseries/iommu.c | 9 +
arch/powerpc/platforms/pseries/pseries.h | 2 ++
arch/powerpc/platforms/pseries/setu
This moves the Power Mac platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens
---
arch/powerpc/platforms/powermac/pci.c | 17 +++--
arch/powerpc/platforms/powermac/pmac.h | 5 +
arch/powerpc/platforms/
If a pci_controller_ops struct is provided to iommu_init_early_dart,
populate that with the DMA setup ops, rather than ppc_md. If NULL is
provided, populate ppc_md as before.
This also patches the call sites for Maple and Power Mac to pass
NULL, so existing behaviour is preserved.
The benefit of
On Thu, 2015-02-26 at 10:48 +0100, Thomas Haschka wrote:
> Hello,
>
> I hope I get it correct this time, thanks again.
Thanks. Sorry for the delay, I've been a bit swamped. I looked at your
code a bit more in depth and I would appreciate a couple more changes
if you don't mind:
.../...
> +st
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/pci-bridge.h | 17 +
arch/powerpc/kernel/pci-common.c | 7 +--
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index d
Name the shim pci_window_alignment (rather than window_alignment)
to avoid clashing with window_alignment in drivers/pci/setup-bus.c
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/pci-bridge.h | 21 +
arch/powerpc/kernel/pci-common.c | 10 +-
2 files c
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/pci-bridge.h | 15 +++
arch/powerpc/kernel/pci-common.c | 5 ++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 5d699
We need to move the probe mode defines to pci-bridge.h from pci.h.
They are required by the shim in order to return a sensible default.
Previously, the were defined in pci.h, but pci.h includes pci-bridge.h
before the relevant #defines. This means the definitions are absent
if pci.h is included bef
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/pci-bridge.h | 11 +++
arch/powerpc/kernel/pci-common.c | 3 +--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 2474f29..68
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/pci-bridge.h | 14 ++
arch/powerpc/kernel/pci-common.c | 3 +--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 3ab8a2d.
Signed-off-by: Daniel Axtens
---
arch/powerpc/include/asm/pci-bridge.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 546d036..3ab8a2d 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/pow
pcibios_enable_device_hook returned an int. Every implementation
returned either -EINVAL or 0. The return value wasn't propagated by
the caller: any non-zero return value caused pcibios_enable_device
to return -EINVAL itself. Therefore, make the hook return a bool.
Signed-off-by: Daniel Axtens
--
The only function that checks ppc_swiotlb_enable is swiotlb_subsys_init.
The code in fsl_pci.c is called well after that, so don't bother
changing it.
(ppc_swiotlb is usually set in swiotlb_detect_4g, which is called by
a number of arch initcalls.)
Signed-off-by: Daniel Axtens
---
arch/powerpc/
swiotlb_late_init sets up platform specific hooks. It's not actually
a late initcall, but a subsys initcall, called much earlier.
Ideally we'd call it swiotlb_init, but that's taken.
Call it swiotlb_subsys_init for now.
(It will be refactored and renamed later.)
Signed-off-by: Daniel Axtens
---
Signed-off-by: Daniel Axtens
---
arch/powerpc/platforms/powermac/pci.c | 17 +
arch/powerpc/platforms/powermac/pmac.h | 4
arch/powerpc/platforms/powermac/setup.c | 18 --
3 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/platfo
Previously, find_and_init_phbs() was used in both PowerNV and pSeries
setup. However, since RTAS support has been dropped from PowerNV, we
can move it into a platform-specific file.
This patch depends on the patch to drop RTAS support from PowerNV:
http://patchwork.ozlabs.org/patch/449316/
Signed
This patch set moves some PCI controller operations out of ppc_md and
into a new pci_controller_ops struct.
This is desirable for systems with more than one type of PCI
controller. In particular, it's intended that this new interface will
be used by the CXL (aka CAPI) driver.
The design tries to
On Wed, 2015-03-18 at 16:04 +1100, Michael Ellerman wrote:
> On Tue, 2015-03-17 at 11:35 +0530, Anshuman Khandual wrote:
> > On 03/17/2015 04:34 AM, Michael Ellerman wrote:
> > > What are you seeing exactly?
> >
> > I am running on a BE PKVM guest but compiling the test case on
> > a different BE
On Thu, 2015-03-19 at 15:15 +1100, Michael Ellerman wrote:
> The celleb code has seen no actual development for ~7 years.
>
> We (maintainers) have no access to test hardware, and it is highly
> likely the code has bit-rotted.
>
> As far as we're aware the hardware was never widely available, and
On Thu, 2015-03-12 at 17:27 +1100, Michael Ellerman wrote:
> The powernv code has some conditional support for running on bare metal
> machines that have no OPAL firmware, but provide RTAS.
>
> No released machines ever supported that, and even in the lab it was
> just a transitional hack in the d
On Tue, 2015-24-03 at 12:33:22 UTC, Jan Stancek wrote:
> One path in power_pmu_event_init() calls get_cpu_var(), but is
> missing matching call to put_cpu_var(), which causes preemption
> imbalance and crash in user-space:
>
> Page fault in user mode with in_atomic() = 1 mm = c01fefa5a280
>
On Fri, 2015-03-20 at 16:34 +0530, Vasant Hegde wrote:
> From: Anshuman Khandual
>
> This patch implements LED driver for PowerNV platform using the existing
> generic LED class framework. It registers classdev structures for all
> individual LEDs detected on the system through LED specific devic
On Tue, 2015-02-03 at 12:39 +0100, Christophe Leroy wrote:
> csum_tcpudp_magic() is only a few instructions, and does not modifies any
> other
> register than the returned result. So it is not worth having it as a separate
> function and suffer function branching and saving of volatile registers.
On Fri, 2015-27-02 at 22:22:54 UTC, Yannick Guerrini wrote:
> Change 'Kenrel' to 'Kernel'
>
> Signed-off-by: Yannick Guerrini
> ---
> arch/powerpc/include/asm/smu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
If you're going to send spelling fix patches, please at least fix all the
On Tue, 2015-03-24 at 11:52 +1100, Cyril Bur wrote:
> On Wed, 2015-03-04 at 12:22 -0800, Tyrel Datwyler wrote:
> > During suspend/migration operation we must wait for the VASI state reported
> > by the hypervisor to become Suspending prior to making the ibm,suspend-me
> > RTAS call. Calling routine
On Tue, 2015-03-24 at 21:49 +0200, Alex Dowad wrote:
> On 20/03/15 01:54, Michael Ellerman wrote:
> > On Thu, 2015-03-19 at 09:22 +0200, Alex Dowad wrote:
> >> On 19/03/15 08:45, Michael Ellerman wrote:
> >>> On Fri, 2015-13-03 at 18:14:46 UTC, Alex Dowad wrote:
> The 'arg' argument to copy_th
On Tue, 2015-03-24 at 19:45 -0500, Scott Wood wrote:
> On Fri, 2015-03-13 at 10:34 +1100, Michael Ellerman wrote:
> > On Thu, 2015-03-12 at 16:24 +0100, Christophe Leroy wrote:
> > > Two config options exist to define powerpc MPC8xx:
> > > * CONFIG_PPC_8xx
> > > * CONFIG_8xx
> > > In addition, CONF
On Tue, Feb 03, 2015 at 12:39:27PM +0100, LEROY Christophe wrote:
> The C version of csum_add() as defined in include/net/checksum.h gives the
> following assembly:
>0: 7c 04 1a 14 add r0,r4,r3
>4: 7c 64 00 10 subfc r3,r4,r0
>8: 7c 63 19 10
On Tue, Feb 03, 2015 at 12:39:27PM +0100, LEROY Christophe wrote:
> On PPC_8xx, lwz has a 2 cycles latency, and branching also takes 2 cycles.
> As the size of the header is minimum 5 words, we can unroll the loop for the
> first words to reduce number of branching, and we can re-order the
> instr
On Fri, 2015-03-13 at 10:34 +1100, Michael Ellerman wrote:
> On Thu, 2015-03-12 at 16:24 +0100, Christophe Leroy wrote:
> > Two config options exist to define powerpc MPC8xx:
> > * CONFIG_PPC_8xx
> > * CONFIG_8xx
> > In addition, CONFIG_PPC_8xx also defines CONFIG_CPM1 as
> > communication co-proce
On Tue, 2015-03-24 at 11:34 +0800, Yijing Wang wrote:
> Now we could use pci_scan_host_bridge() to scan
> pci buses, provide powerpc specific pci_host_bridge_ops.
>
> Signed-off-by: Yijing Wang
> CC: Benjamin Herrenschmidt
> CC: linuxppc-dev@lists.ozlabs.org
> ---
> arch/powerpc/kernel/pci-comm
POWER7 has a dedicated stream prefetcher that is pre-programmed via
dcbt rX,rY,0b010?0 instructions in the beginning of vmx_copy.
e6500 has no such prefetcher, so we revert to using regular dcbt
instructions in-loop:
1. at __copy_tofrom_user_power7 entry, we prefetch the first
src and dest lines
The innermost copyloops were optimized for POWER7's 128-byte cacheline.
This patch adds optimization for the e6500, which has a 64-byte
cacheline.
We basically do this by stripping loop bodies using L1_CACHE_BYTES
ifdeferry, replace 128 with L1_CACHE_BYTES, and 7's with L1_CACHE_SHIFTs.
We also a
This enables the VMX/ALTIVEC optimised copy-to/from-user code in
arch/powerpc/lib/copyuser_power7.S. The e6500 does, and the e5500
does not, have ALTIVEC.
Signed-off-by: Kim Phillips
---
arch/powerpc/include/asm/cputable.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch
From: Sowmini Varadhan
Date: Tue, 24 Mar 2015 13:10:27 -0400
> Deltas from patchv5:
> - removed iommu_tbl_ops, and instead pass the ->flush_all as
> an indirection to iommu_tbl_pool_init()
> - only invoke ->flush_all when there is no large_pool, based on
> the assumption that large-pool usage
One path in power_pmu_event_init() calls get_cpu_var(), but is
missing matching call to put_cpu_var(), which causes preemption
imbalance and crash in user-space:
Page fault in user mode with in_atomic() = 1 mm = c01fefa5a280
NIP = 3fff9bf2cae0 MSR = 90014280f032
Oops: Weird page fau
On Tue, Mar 24, 2015 at 8:33 AM, Mel Gorman wrote:
> On Tue, Mar 24, 2015 at 10:51:41PM +1100, Dave Chinner wrote:
>>
>> So it looks like the patch set fixes the remaining regression and in
>> 2 of the four cases actually improves performance
>
> \o/
W00t.
> Linus, these three patches plus t
On 20/03/15 01:54, Michael Ellerman wrote:
On Thu, 2015-03-19 at 09:22 +0200, Alex Dowad wrote:
On 19/03/15 08:45, Michael Ellerman wrote:
On Fri, 2015-13-03 at 18:14:46 UTC, Alex Dowad wrote:
The 'arg' argument to copy_thread() is only ever used when forking a new
kernel thread. Hence, rename
Deltas from patchv5:
- removed iommu_tbl_ops, and instead pass the ->flush_all as
an indirection to iommu_tbl_pool_init()
- only invoke ->flush_all when there is no large_pool, based on
the assumption that large-pool usage is infrequently encountered.
Sowmini (2):
Break up monolithic iommu t
On Tue, Mar 03, 2015 at 10:41:22PM +0200, Andy Shevchenko wrote:
> This patch re-uses hsdev->dev which is allocated on heap. Therefore, the
> private structure, which is global variable, is reduced by one field.
>
> In one case ap->dev is used and there it seems to be right decision.
>
> Signed-o
Investigation of multithreaded iperf experiments on an ethernet
interface show the iommu->lock as the hottest lock identified by
lockstat, with something of the order of 21M contentions out of
27M acquisitions, and an average wait time of 26 us for the lock.
This is not efficient. A more scalable
Note that this conversion is only being done to consolidate the
code and ensure that the common code provides the sufficient
abstraction. It is not expected to result in any noticeable
performance improvement, as there is typically one ldc_iommu
per vnet_port, and each one has 8k entries, with a ty
In iperf experiments running linux as the Tx side (TCP client) with
10 threads results in a severe performance drop when TSO is disabled,
indicating a weakness in the software that can be avoided by using
the scalable IOMMU arena DMA allocation.
Baseline numbers before this patch:
with default
From: Kumar Gala
Signed-off-by: Kumar Gala
Signed-off-by: Geoff Thorpe
Signed-off-by: Hai-Ying Wang
Signed-off-by: Chunhe Lan
Signed-off-by: Poonam Aggrwal
[Emil Medve: Sync with the upstream binding]
Signed-off-by: Emil Medve
---
v8: Fix indentation/whitespaces
v7: Remove 'Change
On Tue, Mar 24, 2015 at 10:51:41PM +1100, Dave Chinner wrote:
> On Mon, Mar 23, 2015 at 12:24:00PM +, Mel Gorman wrote:
> > These are three follow-on patches based on the xfsrepair workload Dave
> > Chinner reported was problematic in 4.0-rc1 due to changes in page table
> > management -- https
On Tue, 2015-03-24 at 12:18 +0530, Hemant Kumar wrote:
> Hi Michael,
>
> These patches were posted a month back. We don't have any review
> comments to handle at this time. Can you pull these patches to your tree?
> Please, do let me know if you want me to rebase these patches to a
> different t
On Tue, 2015-03-24 at 09:56 +0530, Anshuman Khandual wrote:
> On 03/24/2015 07:34 AM, Michael Ellerman wrote:
> > On Fri, 2015-03-20 at 14:34 +0530, Anshuman Khandual wrote:
> >> On 03/19/2015 10:13 AM, Sam Bobroff wrote:
> >>> This patch changes the syscall handler to doom (tabort) active
> >>> tr
On Mon, Mar 23, 2015 at 12:24:00PM +, Mel Gorman wrote:
> These are three follow-on patches based on the xfsrepair workload Dave
> Chinner reported was problematic in 4.0-rc1 due to changes in page table
> management -- https://lkml.org/lkml/2015/3/1/226.
>
> Much of the problem was reduced by
After previous discussions regarding the subject [1][2], there's no clear
explanation or reason why the call was needed in the first place. The sensible
argument is some sort of synchronization between the CPU and the MPIC, which
hasn't been pointed out precisely and is no longer required (at least
On Tue, 2015-03-24 at 11:23 +0530, Aneesh Kumar K.V wrote:
> >>/* assume we don't have huge pages in vmalloc space... */
> >>addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
> >> + local_irq_restore(flags);
> >>return __va(addr);
> >> }
> >
> > This is called in real mode, I
Hello Scott,
On 03/23/2015 06:30 PM, Scott Wood wrote:
> On Thu, 2015-02-26 at 09:26 -0600, Emil Medve wrote:
>> From: Igal Liberman
>>
>> Signed-off-by: Igal Liberman
>> ---
>> arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 11 +++
>> arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 8 ++
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