On 04/20/2015 12:44 PM, David Gibson wrote:
On Fri, Apr 17, 2015 at 08:09:29PM +1000, Alexey Kardashevskiy wrote:
On 04/16/2015 04:07 PM, David Gibson wrote:
On Fri, Apr 10, 2015 at 04:30:56PM +1000, Alexey Kardashevskiy wrote:
At the moment the iommu_table struct has a set_bypass() which enab
All of the k_clock users have been converted to the new methods. This patch
removes the older methods with timepsec/itimerspec type. As a result, the
k_clock
structure is ready for the year 2038.
Signed-off-by: Baolin Wang
---
include/linux/posix-timers.h |9 --
kernel/time/posix-timer
This patch changes to the new methods of k_clock structure with timespec64
type, converts the timespec/itimerspec type to timespec64/itimerspec64 type
for the callback function in posix-cpu-timers.c file.
Signed-off-by: Baolin Wang
---
kernel/time/posix-cpu-timers.c | 83 +-
This patch introduces some functions for converting cputime to timespec64 and
back,
that repalce the timespec type with timespec64 type, as well as for arch/s390
and
arch/powerpc architecture.
And these new methods will replace the old
cputime_to_timespec/timespec_to_cputime
function to ready f
This patch converts the posix clock operations over to the new methods with
timespec64/itimerspec64 type to making them ready for 2038, and it is based on
the ptp patch series.
And also changes to the 64bit methods for k_clock structure, that
converts the timespec/itimerspec type to timespec64/iti
This patch changes to the new methods with timespec64/itimerspec64
type of k_clock structure, and converts the timespec/itimerspec type to
timespec64/itimerspec64 typein alarmtimer.c file.
Signed-off-by: Baolin Wang
---
kernel/time/alarmtimer.c | 43 ++-
This patch converts to the 64bit methods for k_clock callback
function, that converts the timespec type to timespec64 type and
converts the itimerspec type to itimerspec64 type.
Signed-off-by: Baolin Wang
---
drivers/char/mmtimer.c | 36 +---
1 file changed, 17
This patch converts the timepsec type to timespec64 type, and converts the
itimerspec type to itimerspec64 type for the k_clock callback functions.
This patch also converts the timespec type to timespec64 type for
timekeeping_clocktai()
function which is used only in the posix-timers.c file.
Sig
This patch introduces the new methods with timespec64 type for k_clcok
structure,
converts the timepsec type to timespec64 type in k_clock structure and converts
the itimerspec type to itimerspec64 type to ready for 2038 issue.
And also introduces the 64bit methods with timespec64 type for the fr
This patch introduces hrtimer_get_res64() function to get the timer resolution
with timespec64 type, and moves the hrtimer_get_res() function into
include/linux/hrtimer.h as a 'static inline' helper that just calls
hrtimer_get_res64.
It is ready for 2038 year when getting the timer resolution by
This patch adds current_kernel_time64() function with timespec64 type,
and makes current_kernel_time() 'static inline' and moves it to timekeeping.h
file.
It is convenient for user to get the current kernel time with timespec64 type,
and delete the current_kernel_time() function easily in timekeep
This patch introduces the 'struct itimerspec64' for 64bit to replace itimerspec,
and also introduces the conversion methods: itimerspec64_to_itimerspec() and
itimerspec_to_itimerspec64(), that makes itimerspec to ready for 2038 year.
Signed-off-by: Baolin Wang
---
include/linux/time64.h | 13 +
This patch series changes the 32-bit time type (timespec/itimerspec) to the
64-bit one
(timespec64/itimerspec64), since 32-bit time types will break in the year 2038.
This patch series introduces new methods with timespec64/itimerspec64 type,
and removes the old ones with timespec/itimerspec type
On 04/13/2015 02:18 PM, Anshuman Khandual wrote:
> On 04/10/2015 04:03 PM, Ulrich Weigand wrote:
>> Anshuman Khandual wrote on 10.04.2015
>> 11:10:35:
>
> I believed it stores the check pointed MSR value which was in the register
> before the transaction started. But then how it is different from
On 04/20/2015 12:46 PM, David Gibson wrote:
On Fri, Apr 17, 2015 at 08:16:13PM +1000, Alexey Kardashevskiy wrote:
On 04/16/2015 04:10 PM, David Gibson wrote:
On Fri, Apr 10, 2015 at 04:30:57PM +1000, Alexey Kardashevskiy wrote:
This adds missing locks in iommu_take_ownership()/
iommu_release_o
On Fri, Apr 17, 2015 at 08:37:54PM +1000, Alexey Kardashevskiy wrote:
> On 04/16/2015 04:26 PM, David Gibson wrote:
> >On Fri, Apr 10, 2015 at 04:30:59PM +1000, Alexey Kardashevskiy wrote:
> >>At the moment writing new TCE value to the IOMMU table fails with EBUSY
> >>if there is a valid entry alre
On Fri, Apr 17, 2015 at 08:09:29PM +1000, Alexey Kardashevskiy wrote:
> On 04/16/2015 04:07 PM, David Gibson wrote:
> >On Fri, Apr 10, 2015 at 04:30:56PM +1000, Alexey Kardashevskiy wrote:
> >>At the moment the iommu_table struct has a set_bypass() which enables/
> >>disables DMA bypass on IODA2 PH
On Fri, Apr 17, 2015 at 08:16:13PM +1000, Alexey Kardashevskiy wrote:
> On 04/16/2015 04:10 PM, David Gibson wrote:
> >On Fri, Apr 10, 2015 at 04:30:57PM +1000, Alexey Kardashevskiy wrote:
> >>This adds missing locks in iommu_take_ownership()/
> >>iommu_release_ownership().
> >>
> >>This marks all
On Fri, Apr 17, 2015 at 07:46:23PM +1000, Alexey Kardashevskiy wrote:
> On 04/16/2015 03:55 PM, David Gibson wrote:
> >On Fri, Apr 10, 2015 at 04:30:54PM +1000, Alexey Kardashevskiy wrote:
> >>Modern IBM POWERPC systems support multiple (currently two) TCE tables
> >>per IOMMU group (a.k.a. PE). Th
On Fri, Apr 17, 2015 at 01:48:13AM +1000, Alexey Kardashevskiy wrote:
> On 04/16/2015 03:55 PM, David Gibson wrote:
> >On Fri, Apr 10, 2015 at 04:30:54PM +1000, Alexey Kardashevskiy wrote:
> >>Modern IBM POWERPC systems support multiple (currently two) TCE tables
> >>per IOMMU group (a.k.a. PE). Th
On Fri, Apr 17, 2015 at 02:29:23AM +1000, Alexey Kardashevskiy wrote:
> On 04/16/2015 04:46 PM, David Gibson wrote:
> >On Fri, Apr 10, 2015 at 04:31:03PM +1000, Alexey Kardashevskiy wrote:
> >>The iommu_free_table helper release memory it is using (the TCE table and
> >>@it_map) and release the iom
Le 20/04/2015 07:26, Christophe Leroy a écrit :
This patchset provides a further optimisation of TLB handling in the 8xx.
Main changes are based on:
- Using processor handling of PGD/PTE Validity bits instead of testing ourselves
the entries validity
- Aligning PGD address to allow direct bit man
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most
likely sufficient for most cases. However, kernel configuration allows
to set TASK_SIZE to another value, so the 8xx shall handle it.
This patch also takes into account the case of PAGE_OFFSET lower than
0x8000, allthought m
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/
CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we
don't need to do anything at all with CR.
- We use r10, then we reload SRR0/MD_EPN into r10 when CR is
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/head_
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 9b53fe1..1279018 100644
--- a
This patchset provides a further optimisation of TLB handling in the 8xx.
Changes are:
- Not saving registers like CR when not needed
- Adding support to any TASK_SIZE
Only the last patch of the set is changed compared to v4
Resending with proper From: this time.
Christophe Leroy (5):
powerpc/
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29 +++
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch
CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we
don't need to do anything at all with CR.
- If CONFIG_8xx_CPU6 is defined, we have r3 available for sa
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/head
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b227902e..b3f3cb5 100644
---
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index aa45225..b227902e 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc
All accessed to PGD entries are done via 0(r11).
By using lower part of swapper_pg_dir as load index to r11, we can remove the
ori instruction.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff
L1 base address is now aligned so we can insert L1 index into r11 directly and
then preserve r10
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 34 +++---
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/kernel/head_8
When pages are not 4K, PGDIR table is allocated with kmalloc(). In order to
optimise TLB handlers, aligned memory is needed. kmalloc() doesn't provide
aligned memory blocks, so lets use a kmem_cache pool instead.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable-ppc32.h | 4
Kernel MMU handling code handles validity of entries via _PMD_PRESENT which
corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx
triggers TLBError exception. So we don't have to check that and branch ourself
to TLBError. We can set TLB entries with non present entries, remov
Since commit 33fb845a6f01 ("powerpc/8xx: Don't use MD_TWC for walk"), MD_EPN and
MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/powerpc/ke
This patchset provides a further optimisation of TLB handling in the 8xx.
Main changes are based on:
- Using processor handling of PGD/PTE Validity bits instead of testing ourselves
the entries validity
- Aligning PGD address to allow direct bit manipulation
- Not saving registers like CR when not
Hi Michael,
On 04/19/2015 08:01 PM, Michael Ellerman wrote:
On Sun, 2015-04-19 at 14:36 -0400, Sowmini Varadhan wrote:
On (04/19/15 14:09), David Miller wrote:
On (04/18/15 21:23), Guenter Roeck wrote:
lib/built-in.o:(.discard+0x1): multiple definition of
`__pcpu_unique_iommu_pool_hash'
arch
Fastsleep is one of the idle state which cpuidle subsystem currently
uses on power8 machines. In this state L2 cache is brought down to a
threshold voltage. Therefore when the core is in fastsleep, the
communication between L2 and L3 needs to be fenced. But there is a bug
in the current power8 chip
This is a cleanup patch; doesn't change any functionality. Moves
all cpuidle related code from setup.c to a new file.
Signed-off-by: Shreyas B. Prabhu
Reviewed-by: Preeti U Murthy
---
arch/powerpc/platforms/powernv/Makefile | 2 +-
arch/powerpc/platforms/powernv/idle.c | 191 +++
Currently, cpu_online_cores_map returns a mask, which for every core with
at least one online thread, has the bit for thread 0 of the core set to 1,
and the bits for all other threads of the core set to 0. But thread 0 of
the core itself may not be online always. In such cases, if the returned
mask
Fastsleep is one of the idle state which cpuidle subsystem currently
uses on power8 machines. In this state L2 cache is brought down to a
threshold voltage. Therefore when the core is in fastsleep, the
communication between L2 and L3 needs to be fenced. But there is a bug
in the current power8 ch
On Sun, 2015-04-19 at 14:36 -0400, Sowmini Varadhan wrote:
> > On (04/19/15 14:09), David Miller wrote:
> >
> > > On (04/18/15 21:23), Guenter Roeck wrote:
> > >> lib/built-in.o:(.discard+0x1): multiple definition of
> > >> `__pcpu_unique_iommu_pool_hash'
> > >> arch/powerpc/kernel/built-in.o:(.dis
> On (04/19/15 14:09), David Miller wrote:
>
> > On (04/18/15 21:23), Guenter Roeck wrote:
> >> lib/built-in.o:(.discard+0x1): multiple definition of
> >> `__pcpu_unique_iommu_pool_hash'
> >> arch/powerpc/kernel/built-in.o:(.discard+0x18): first defined here
> >> .. I get a similar failure in the
Dear Kiran,
arghhh... Please do not post the same question in several messages to
many addrresses; if you really feel you need to send it to all, then
please put all on Cc: so all can receive the replies, too.
I answered before:
In message
you wrote:
>
> In uboot, i run some IPMI commands and
Dear Ajit Phadnis,
In message
you wrote:
>
> Would like to how to store the response command of a run command
You should ask U-Boot related questions on the U-Boot mailing list [1]
instead; chances for a helpful reply are much better there than on
lists that do not actually deal with U-Boot.
Hello team,
I have a problem.
In uboot, i run some IPMI commands and I have to store that value in uboot
and also extract the interim byte of the output value.
I dont see the support for the same in Uboot or I'm missing something.
eg:
uboot> run
The output of this has to be stored in some var
Hi Folks,
Would like to how to store the response command of a run command
=>setenv addr 'ping 192.172.24.24'
=>setenv ping_resp 'run addr'
Would to store the outcome of "run addr" in into a variable and grep for
the characters or string in Uboot.
// Expecting the output as ping response s
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