We print the respective warning after parsing EPOW interrupts,
prompting user to take action depending upon the severity of the
event.
Some times same EPOW event warning, such as below could flood kernel
log, within very short duration. So Limit the message by using
ratelimit variant of pr_err.
M
On Wed, May 20, 2015 at 09:17:11PM -0500, Scott Wood wrote:
> From: Jaiprakash Singh
>
> IFC IO accressor are set at run time based
> on IFC IP registers endianness.IFC node in
> DTS file contains information about
> endianness.
>
> Signed-off-by: Jaiprakash Singh
> Signed-off-by: Scott Wood
>
On Wednesday, May 27, 2015 02:31:49 PM Bjorn Helgaas wrote:
> [updated Rafael's email addr; not sure if sisk.pl still works or not]
>
> On Wed, May 27, 2015 at 11:31:21AM -0700, Yinghai Lu wrote:
> > On Fri, Jul 26, 2013 at 5:43 AM, Yinghai Lu wrote:
> > > On Thu, Jul 25, 2013 at 10:57 AM, Bjorn
On Wed, 2015-05-27 at 17:11 +0800, Zhao Qiang wrote:
> +int qe_muram_init(void)
> +{
> + struct device_node *np;
> + struct resource r;
> + u32 zero[OF_MAX_ADDR_CELLS] = {};
> + resource_size_t max = 0;
> + int i = 0;
> + int ret = 0;
> +
> + if (muram_pbase)
> +
From: Andi Kleen
Add a --no-desc flag to perf list to not print the event descriptions
that were earlier added for JSON events. This may be useful to
get a less crowded listing.
It's still default to print descriptions as that is the more useful
default for most users.
v2: Rename --quiet to --n
From: Andi Kleen
Automatically adapt the now wider and word wrapped perf list
output to wider terminals. This requires querying the terminal
before the auto pager takes over, and exporting this
information from the pager subsystem.
Acked-by: Namhyung Kim
Signed-off-by: Andi Kleen
---
tools/pe
From: Andi Kleen
Implement the code to match CPU types to mapfile types for x86
based on CPUID. This extends an existing similar function,
but changes it to use the x86 mapfile cpu description.
This allows to resolve event lists generated by jevents.
v2: Update to new get_cpuid_str() interface
S
From: Andi Kleen
Add support to print alias descriptions in perf list, which
are taken from the generated event files.
The sorting code is changed to put the events with descriptions
at the end. The descriptions are printed as possibly multiple word
wrapped lines.
Example output:
% perf list
.
From: Andi Kleen
The Intel events use a dot to separate event name and unit mask.
Allow dot in names in the scanner, and remove special handling
of dot as EOF. Also remove the hack in jevents to replace dot
with underscore. This way dotted events can be specified
directly by the user.
I'm not fu
From: Andi Kleen
Support a header line in the mapfile.csv, to match the existing
mapfiles
Signed-off-by: Andi Kleen
---
tools/perf/pmu-events/jevents.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 03f7b65..4365
From: Andi Kleen
This is a modified version of an earlier patch by Andi Kleen.
We expect architectures to describe the performance monitoring events
for each CPU in a corresponding JSON file, which look like:
[
{
"EventCode": "0x00",
"UMask": "0x01",
"Eve
At run time, (i.e when perf is starting up), locate the specific events
table for the current CPU and create event aliases for each of the events.
Use these aliases to parse user's specified perf event.
Signed-off-by: Sukadev Bhattiprolu
Changelog[v2]
[Andi Kleen] Replace the pmu_events
From: Andi Kleen
I need a JSON parser. This adds the simplest JSON
parser I could find -- Serge Zaitsev's jsmn `jasmine' --
to the perf library. I merely converted it to (mostly)
Linux style and added support for non 0 terminated input.
The parser is quite straight forward and does not
copy any
CPUs support a large number of performance monitoring events (PMU events)
and often these events are very specific to an architecture/model of the
CPU. To use most of these PMU events with perf we currently have to identify
the events by their raw codes:
perf stat -e r100f2 sleep 1
This p
Hi Cyril,
On Thu, May 21, 2015 at 04:12:52PM +1000, Cyril Bur wrote:
> One question though,
>
> On Wed, 2015-05-20 at 14:17 -0700, Brian Norris wrote:
> > On Mon, May 04, 2015 at 04:42:19PM +1000, Cyril Bur wrote:
> > > Powerpc powernv platforms allow access to certain system flash devices
> > >
Andi Kleen [a...@linux.intel.com] wrote:
| > I know. What I said is make it optional so that we can drop if it's
identical.
|
| Should be easy enough. It's already optional in the jevents parser.
I have removed the duplicated entries in power8.json.
[updated Rafael's email addr; not sure if sisk.pl still works or not]
On Wed, May 27, 2015 at 11:31:21AM -0700, Yinghai Lu wrote:
> On Fri, Jul 26, 2013 at 5:43 AM, Yinghai Lu wrote:
> > On Thu, Jul 25, 2013 at 10:57 AM, Bjorn Helgaas wrote:
> >> Convert pciehp to be builtin only, with no module
On Fri, Jul 26, 2013 at 5:43 AM, Yinghai Lu wrote:
> On Thu, Jul 25, 2013 at 10:57 AM, Bjorn Helgaas wrote:
>> Convert pciehp to be builtin only, with no module option.
>>
>> Signed-off-by: Bjorn Helgaas
>> Acked-by: Rafael J. Wysocki
>> ---
>> drivers/pci/pcie/Kconfig |5 +
>> 1 file
On Wed, 2015-05-27 at 17:12 +0800, Zhao Qiang wrote:
> qe need to use the rheap, so move it to public directory.
You've been previously asked to use lib/genalloc.c rather than
introduce duplicate functionality into /lib. NACK.
Also, please don't use coreid-based e-mail addresses with no real
n
On Thu, May 28, 2015 at 12:01:31AM +0900, Namhyung Kim wrote:
> On Wed, May 27, 2015 at 11:41 PM, Andi Kleen wrote:
> >> > + {
> >> > +"EventCode": "0x2505e",
> >> > +"EventName": "PM_BACK_BR_CMPL",
> >> > +"BriefDescription": "Branch instruction completed with a target
> >> > addres
On Wed, May 27, 2015 at 11:41 PM, Andi Kleen wrote:
>> > + {
>> > +"EventCode": "0x2505e",
>> > +"EventName": "PM_BACK_BR_CMPL",
>> > +"BriefDescription": "Branch instruction completed with a target
>> > address less than current instruction address,",
>> > +"PublicDescription":
Hi Andi,
On Wed, May 27, 2015 at 11:40 PM, Andi Kleen wrote:
>> So we build tables of all models in the architecture, and choose
>> matching one when compiling perf, right? Can't we do that when
>> building the tables? IOW, why don't we check the VFM and discard
>> non-matching tables? Those n
> > + {
> > +"EventCode": "0x2505e",
> > +"EventName": "PM_BACK_BR_CMPL",
> > +"BriefDescription": "Branch instruction completed with a target
> > address less than current instruction address,",
> > +"PublicDescription": "Branch instruction completed with a target
> > address le
> So we build tables of all models in the architecture, and choose
> matching one when compiling perf, right? Can't we do that when
> building the tables? IOW, why don't we check the VFM and discard
> non-matching tables? Those non-matching tables are also needed?
We build it for all cpus in an
On Tue, May 26, 2015 at 6:06 PM, Ulf Hansson wrote:
> On 21 May 2015 at 10:43, Suman Tripathi wrote:
> > The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
> > This patch adds the support to disable SDR104/SDR50/DDR50 based on
> > reading the capability register 0.
> >
> > Sign
On Tue, May 19, 2015 at 05:02:10PM -0700, Sukadev Bhattiprolu wrote:
> The power8.json and 004d0100.json files describe the PMU events in the
> Power8 processor.
>
> The jevents program from the prior patches will use these JSON files
> to create tables which will then be used in perf to build ali
Hi Sukadev,
On Tue, May 19, 2015 at 05:02:08PM -0700, Sukadev Bhattiprolu wrote:
> From: Andi Kleen
>
> This is a modified version of an earlier patch by Andi Kleen.
>
> We expect architectures to describe the performance monitoring events
> for each CPU in a corresponding JSON file, which look
On Mon, May 25, 2015 at 02:45:16PM +1000, Cyril Bur wrote:
> Selecting CRYPTO_DEV_NX causes a conditional include of nx/Kconfig but
> options within nx/Kconfig do not depend on it. The included options should
> depend on CRYPTO_DEV_NX since currently CRYPTO_DEV_NX cannot be built for
> little endia
qe need to call some common functions,
add a new file drivers/soc/fsl/qe/qe_common.c
for them.
Signed-off-by: Zhao Qiang
---
drivers/soc/fsl/qe/Makefile| 3 +-
drivers/soc/fsl/qe/qe_common.c | 185 +
include/soc/fsl/qe.h | 75 +
qe need to use the rheap, so move it to public directory.
Signed-off-by: Zhao Qiang
---
arch/powerpc/Kconfig| 3 ---
arch/powerpc/include/asm/fsl_85xx_cache_sram.h | 2 +-
arch/powerpc/lib/Makefile | 2 --
arch/powerpc/pl
On Wed, 27 May 2015 07:59:34 +0200
Thomas Huth wrote:
> On Wed, 27 May 2015 02:11:13 +0200
> Greg Kurz wrote:
>
> > SLOF currently calls hv-logical-load and hv-logical-store for every pixel
> > when enabling or disabling the cursor. This is suboptimal when writing one
> > char at a time to the
Greg Kurz writes:
> On Wed, 27 May 2015 10:41:06 +0530
> Nikunj A Dadhania wrote:
>
>> Greg Kurz writes:
>>
>> > SLOF currently calls hv-logical-load and hv-logical-store for every pixel
>> > when enabling or disabling the cursor. This is suboptimal when writing one
>> > char at a time to the
On Wed, 27 May 2015 10:41:06 +0530
Nikunj A Dadhania wrote:
> Greg Kurz writes:
>
> > SLOF currently calls hv-logical-load and hv-logical-store for every pixel
> > when enabling or disabling the cursor. This is suboptimal when writing one
> > char at a time to the console since terminal-write a
From: Scott Wood
> Sent: 26 May 2015 20:43
...
> > I was thinking of all 64bit targets, not 32bit ones.
>
> Oh, you mean move it out of arch/powerpc? Sounds reasonable, but
> someone should probably check what the resulting code looks like on
> other common arches. OTOH, if we're going to modify
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