* Preeti U Murthy [2015-05-29 19:17:17]:
[snip]
> > + if (max_idle_state > 1) {
> > + snooze_timeout_en = true;
> > + snooze_timeout = cpuidle_state_table[1].target_residency *
> > +tb_ticks_per_usec;
> > + }
>
> Any idea why we don't have sno
On Fri, May 29, 2015 at 11:13:15AM +0200, Jiri Olsa wrote:
> On Thu, May 28, 2015 at 10:45:06PM -0700, Sukadev Bhattiprolu wrote:
> > Jiri Olsa [jo...@redhat.com] wrote:
> > | > if (line[0] == '#' || line[0] == '\n')
> > | > continue;
> > | > +
On Wed, May 06, 2015 at 02:29:08PM +0800, Yangbo Lu wrote:
> Signed-off-by: Yangbo Lu
> ---
> arch/powerpc/configs/corenet32_smp_defconfig | 2 ++
> arch/powerpc/configs/corenet64_smp_defconfig | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/arch/powerpc/configs/corenet32_smp_defconf
On 05/28/2015 05:46 PM, Scott Wood wrote:
> On Thu, May 07, 2015 at 05:41:37PM +0800, songwenbin wrote:
>> From: York Sun
>>
>> Remove mpc83xx and mpc85xx as dependency.
>>
>> Signed-off-by: York Sun
>> Signed-off-by: songwenbin
>> ---
>> drivers/edac/Kconfig | 4 ++--
>> 1 file changed, 2 in
At Fri, 29 May 2015 17:49:06 +0200,
Quentin Lambert wrote:
>
>
>
> On 28/05/2015 17:01, Takashi Iwai wrote:
> >>> Also, it'd be better to move ATTRIBUTE_GROUPS(soundbus_dev) into
> >>> soundbus/sysfs.c, and make it this global instead of
> >>> soundbus_dev_attrs[].
> >> Ok, I need to find a nice
On 28/05/2015 17:01, Takashi Iwai wrote:
Also, it'd be better to move ATTRIBUTE_GROUPS(soundbus_dev) into
soundbus/sysfs.c, and make it this global instead of
soundbus_dev_attrs[].
Ok, I need to find a nice way to do that because ATTRIBUTE_GROUPS
declares the
structure as static.
If it resul
Building on the previous patch, extend mlockall() to give a process a
way to specify that pages should be locked when they are faulted in, but
that pre-faulting is not needed.
Signed-off-by: Eric B Munson
Cc: linux-al...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-m...@linux-mips.o
The cost of faulting in all memory to be locked can be very high when
working with large mappings. If only portions of the mapping will be
used this can incur a high penalty for locking. This patch introduces
the ability to request that pages are not pre-faulted, but are placed on
the unevictable
mlock() allows a user to control page out of program memory, but this
comes at the cost of faulting in the entire mapping when it is
allocated. For large mappings where the entire area is not necessary
this is not ideal.
This series introduces new flags for mmap() and mlockall() that allow a
user
Hi Shilpa,
The subject does not convey the purpose of this patch clearly IMO.
I would definitely suggest changing the subject to something like
"Auto promotion of snooze to deeper idle state" or similar.
On 05/29/2015 06:02 PM, Shilpasri G Bhat wrote:
> The idle cpus which stay in snooze for a lo
From: Dinar Valeev
Original issue is home and end keys are not functional in grub2.
Later I've found other inconsistencies in f1-f12 keys.
"Correct sequence" was crabbed by pressing key on cat running in
xterm.
Tested with Home, End, F2, Del and F10 keys in grub2
Signed-off-by: Dinar Valeev
-
The idle cpus which stay in snooze for a long period can degrade the
perfomance of the sibling cpus. If the cpu stays in snooze for more
than target residency of the next available idle state, then exit from
snooze. This gives a chance to the cpuidle governor to re-evaluate the
last idle state of t
At Fri, 29 May 2015 20:06:09 +0900,
Wolfram Sang wrote:
>
> > Do you think from which stable kernel version can this be applied?
>
> The offending commit is 3a3dd0186f619b74e61e6f29dddcaf59af7d3cac
> ("i2c/powermac: Improve detection of devices from device-tree") which
> came in with v3.6 if I re
> Do you think from which stable kernel version can this be applied?
The offending commit is 3a3dd0186f619b74e61e6f29dddcaf59af7d3cac
("i2c/powermac: Improve detection of devices from device-tree") which
came in with v3.6 if I read correctly.
signature.asc
Description: Digital signature
___
At Fri, 29 May 2015 19:50:22 +0900,
Wolfram Sang wrote:
>
> On Thu, May 28, 2015 at 09:33:27AM +0200, Takashi Iwai wrote:
> > At Tue, 26 May 2015 02:19:34 -0700,
> > Dan DeVoto wrote:
> > >
> > > Hi,
> > >
> > > I applied this patch ("check if DEQ was already instantiated") on top of
> > > "sou
On Thu, May 28, 2015 at 09:33:27AM +0200, Takashi Iwai wrote:
> At Tue, 26 May 2015 02:19:34 -0700,
> Dan DeVoto wrote:
> >
> > Hi,
> >
> > I applied this patch ("check if DEQ was already instantiated") on top of
> > "sound: ppc: keywest: drop using attach adapter" and sound works great.
> > Eve
From: Dinar Valeev
Caps behaves like shift only for latin characters.
In case we're typing - for example with caps enabled, SLOF picks _ char
from shifted table.
Threat caps as shift only for letters.
Signed-off-by: Dinar Valeev
---
lib/libusb/usb-hid.c | 19 ---
1 file change
[...]
+/**
+ * @mtd: the device
+ * @erase: the erase info
+ * Returns 0 if erase successful or -ERRNO if an error occurred
+ */
+static int powernv_flash_erase(struct mtd_info *mtd, struct erase_info *erase)
+{
+ int rc;
+
+ erase->state = MTD_ERASING;
+
+ /* todo: register ou
On 05/29/2015 12:57 PM, Cedric Le Goater wrote:
Hello,
On 05/28/2015 07:25 PM, Neelesh Gupta wrote:
On 05/28/2015 06:36 PM, Cyril Bur wrote:
+
+ rc = opal_async_wait_response(token, &msg);
+ opal_async_release_token(token);
+ if (rc) {
+ dev_err(dev, "opal asy
On Thu, May 28, 2015 at 10:45:06PM -0700, Sukadev Bhattiprolu wrote:
> Jiri Olsa [jo...@redhat.com] wrote:
> | > if (line[0] == '#' || line[0] == '\n')
> | > continue;
> | > + if (!strncmp(line, "Family", 6))
> | > + continue;
> |
> | I think we
This is a part of moving TCE table allocation into an iommu_ops
callback to support multiple IOMMU groups per one VFIO container.
This moves the code which allocates the actual TCE tables to helpers:
pnv_pci_ioda2_table_alloc_pages() and pnv_pci_ioda2_table_free_pages().
These do not allocate/free
The iommu_table struct keeps a list of IOMMU groups it is used for.
At the moment there is just a single group attached but further
patches will add TCE table sharing. When sharing is enabled, TCE cache
in each PE needs to be invalidated so does the patch.
This does not change pnv_pci_ioda1_tce_in
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.
Another problem this patch is addressing is the use of pool locks for
external IOMMU users such a
This moves iommu_table creation to the beginning to make following changes
easier to review. This starts using table parameters from the iommu_table
struct.
This should cause no behavioural change.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
Reviewed-by: Gavin Shan
---
Change
The existing code programmed TVT#0 with some address and then
immediately released that memory.
This makes use of pnv_pci_ioda2_unset_window() and
pnv_pci_ioda2_set_bypass() which do correct resource release and
TVT update.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/
This adds a way for the IOMMU user to know how much a new table will
use so it can be accounted in the locked_vm limit before allocation
happens.
This stores the allocated table size in pnv_pci_ioda2_get_table_size()
so the locked_vm counter can be updated correctly when a table is
being disposed.
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential not to put bits which are not
implied in the direction flag as the old TCE value (more precisely -
the permission bit
This is to make extended ownership and multiple groups support patches
simpler for review.
This should cause no behavioural change.
Signed-off-by: Alexey Kardashevskiy
[aw: for the vfio related changes]
Acked-by: Alex Williamson
Reviewed-by: David Gibson
Reviewed-by: Gavin Shan
---
drivers/v
The set_iommu_table_base_and_group() name suggests that the function
sets table base and add a device to an IOMMU group.
The actual purpose for table base setting is to put some reference
into a device so later iommu_add_device() can get the IOMMU group
reference and the device to the group.
At t
This adds create/remove window ioctls to create and remove DMA windows.
sPAPR defines a Dynamic DMA windows capability which allows
para-virtualized guests to create additional DMA windows on a PCI bus.
The existing linux kernels use this new window to map the entire guest
memory and switch to the
This replaces direct accesses to TCE table with a helper which
returns an TCE entry address. This does not make difference now but will
when multi-level TCE tables get introduces.
No change in behavior is expected.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
Reviewed-by: Gavin
This is a part of moving DMA window programming to an iommu_ops
callback. pnv_pci_ioda2_set_window() takes an iommu_table_group as
a first parameter (not pnv_ioda_pe) as it is going to be used as
a callback for VFIO DDW code.
This adds pnv_pci_ioda2_tvt_invalidate() to invalidate TVT as it is
a go
At the moment DMA map/unmap requests are handled irrespective to
the container's state. This allows the user space to pin memory which
it might not be allowed to pin.
This adds checks to MAP/UNMAP that the container is enabled, otherwise
-EPERM is returned.
Signed-off-by: Alexey Kardashevskiy
[a
This extends iommu_table_group_ops by a set of callbacks to support
dynamic DMA windows management.
create_table() creates a TCE table with specific parameters.
it receives iommu_table_group to know nodeid in order to allocate
TCE table memory closer to the PHB. The exact format of allocated
multi
TCE tables might get too big in case of 4K IOMMU pages and DDW enabled
on huge guests (hundreds of GB of RAM) so the kernel might be unable to
allocate contiguous chunk of physical memory to store the TCE table.
To address this, POWER8 CPU (actually, IODA2) supports multi-level
TCE tables, up to 5
There moves locked pages accounting to helpers.
Later they will be reused for Dynamic DMA windows (DDW).
This reworks debug messages to show the current value and the limit.
This stores the locked pages number in the container so when unlocking
the iommu table pointer won't be needed. This does n
This adds tce_iommu_take_ownership() and tce_iommu_release_ownership
which call in a loop iommu_take_ownership()/iommu_release_ownership()
for every table on the group. As there is just one now, no change in
behaviour is expected.
At the moment the iommu_table struct has a set_bypass() which enabl
We are adding support for DMA memory pre-registration to be used in
conjunction with VFIO. The idea is that the userspace which is going to
run a guest may want to pre-register a user space memory region so
it all gets pinned once and never goes away. Having this done,
a hypervisor will not have to
This makes use of the it_page_size from the iommu_table struct
as page size can differ.
This replaces missing IOMMU_PAGE_SHIFT macro in commented debug code
as recently introduced IOMMU_PAGE_XXX macros do not include
IOMMU_PAGE_SHIFT.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
The pnv_pci_ioda_tce_invalidate() helper invalidates TCE cache. It is
supposed to be called on IODA1/2 and not called on p5ioc2. It receives
start and end host addresses of TCE table.
IODA2 actually needs PCI addresses to invalidate the cache. Those
can be calculated from host addresses but since
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where they really belong to.
This adds the requirement for @it_ops to be initialized before calling
iommu_init_table() to m
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
for TCE tables. Right now just one table is supported.
For IODA, instead of embedding iommu_table, the new iommu_table_group
keeps pointers to those. The iomm
At the moment the DMA setup code looks for the "ibm,opal-tce-kill"
property which contains the TCE kill register address. Writing to
this register invalidates TCE cache on IODA/IODA2 hub.
This moves the register address from iommu_table to pnv_pnb as this
register belongs to PHB and invalidates TC
The existing implementation accounts the whole DMA window in
the locked_vm counter. This is going to be worse with multiple
containers and huge DMA windows. Also, real-time accounting would requite
additional tracking of accounted pages due to the page size difference -
IOMMU uses 4K pages and syst
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
for TCE tables. Right now just one table is supported.
This defines iommu_table_group struct which stores pointers to
iommu_group and iommu_table(s). This rep
Before the IOMMU user (VFIO) would take control over the IOMMU table
belonging to a specific IOMMU group. This approach did not allow sharing
tables between IOMMU groups attached to the same container.
This introduces a new IOMMU ownership flavour when the user can not
just control the existing IO
This is a pretty mechanical patch to make next patches simpler.
New tce_iommu_unuse_page() helper does put_page() now but it might skip
that after the memory registering patch applied.
As we are here, this removes unnecessary checks for a value returned
by pfn_to_page() as it cannot possibly retu
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted access to physical memory between
the end of the actual page and the end of the aligned up TCE page.
Since compoun
At the moment iommu_free_table() only releases memory if
the table was initialized for the platform code use, i.e. it had
it_map initialized (which purpose is to track DMA memory space use).
With dynamic DMA windows, we will need to be able to release
iommu_table even if it was used for VFIO in wh
This adds missing locks in iommu_take_ownership()/
iommu_release_ownership().
This marks all pages busy in iommu_table::it_map in order to catch
errors if there is an attempt to use this table while ownership over it
is taken.
This only clears TCE content if there is no page marked busy in it_map
This moves page pinning (get_user_pages_fast()/put_page()) code out of
the platform IOMMU code and puts it to VFIO IOMMU driver where it belongs
to as the platform code does not deal with page pinning.
This makes iommu_take_ownership()/iommu_release_ownership() deal with
the IOMMU table bitmap onl
This enables sPAPR defined feature called Dynamic DMA windows (DDW).
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA window, 1 or 2GB big, mapped at zero
on a PC
So far an iommu_table lifetime was the same as PE. Dynamic DMA windows
will change this and iommu_free_table() will not always require
the group to be released.
This moves iommu_group_put() out of iommu_free_table().
This adds a iommu_pseries_free_table() helper which does
iommu_group_put() and i
The existing code has 3 calls to iommu_register_group() and
all 3 branches actually cover all possible cases.
This replaces 3 calls with one and moves the registration earlier;
the latter will make more sense when we add TCE table sharing.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Gavin S
This relies on the fact that a PCI device always has an IOMMU table
which may not be the case when we get dynamic DMA windows so
let's use more reliable check for IOMMU group here.
As we do not rely on the table presence here, remove the workaround
from pnv_pci_ioda2_set_bypass(); also remove the
We need to limit the max memory based on Linux page table format.
Add checks to limit memory based on pte size. Also limit the memory
based on MAX_PHSYSMEM_BITS.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V1:
* Update commit message. 4K can handle 64TB
* Also limit based on MAX_PHSYSMEM_BIT
Tested this patch on 16TB system and fixed the BUG_ON issue mentioned
here - https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-May/128767.html
I was able to reproduce this issue in all previous releases (tested
from 3.14). So this patch should be also in stable tree.
Acked-by: Haren Myneni
O
Powerpc powernv platforms allow access to certain system flash devices
through a firmwarwe interface. This change adds an mtd driver for these
flash devices.
Minor updates from Jeremy Kerr and Joel Stanley.
Signed-off-by: Cyril Bur
Signed-off-by: Joel Stanley
Signed-off-by: Jeremy Kerr
---
V2:
Hello,
On 05/28/2015 07:25 PM, Neelesh Gupta wrote:
>
>
> On 05/28/2015 06:36 PM, Cyril Bur wrote:
>> Powerpc powernv platforms allow access to certain system flash devices
>> through a firmwarwe interface. This change adds an mtd driver for these
>> flash devices.
>>
>> Minor updates from Jere
* Andi Kleen wrote:
> > So instead of this flat structure, there should at minimum be broad
> > categorization
> > of the various parts of the hardware they relate to: whether they relate to
> > the
> > branch predictor, memory caches, TLB caches, memory ops, offcore, decoders,
> > executio
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