[PATCH v3 5/5] cpufreq: qoriq: Don't look at clock implementation details

Get the CPU clock's potential parent clocks from the clock interface itself, rather than manually parsing the clocks property to find a phandle, looking at the clock-names property of that, and assuming that those are valid parent clocks for the cpu clock. This is necessary now that the clocks are

[PATCH v3 4/5] clk: Add consumer APIs for discovering possible parent clocks

Commit fc4a05d4b0eb ("clk: Remove unused provider APIs") removed __clk_get_num_parents() and clk_hw_get_parent_by_index(), leaving only true provider API versions that operate on struct clk_hw. qoriq-cpufreq needs these functions in order to determine the options it has for calling clk_set_parent(

[PATCH v3 3/5] clk: qoriq: Add ls2080a support.

LS2080A is the first implementation of the chassis 3 clockgen, which has a different register layout than previous chips. It is also little endian, unlike previous chips. Signed-off-by: Scott Wood --- v3: new patch drivers/clk/Kconfig | 2 +- drivers/clk/clk-qoriq.c | 77 +

[PATCH v3 2/5] clk: qoriq: Move chip-specific knowledge into driver

The device tree should describe the chips (or chip-like subblocks) in the system, but it generally does not describe individual registers -- it should identify, rather than describe, a programming interface. This has not been the case with the QorIQ clockgen nodes. The knowledge of what each bit

[PATCH v3 1/5] powerpc/fsl: Move fsl_guts.h out of arch/powerpc

Freescale's Layerscape ARM chips use the same structure. Signed-off-by: Scott Wood --- v3: was patch 2/5 arch/powerpc/include/asm/fsl_guts.h| 192 - arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +- arch

[PATCH v3 0/5] clk: qoriq: Move chip-specific knowledge into driver

The existing device tree bindings are error-prone and inflexible. Correct the mistake by moving the knowledge into the driver, which has more flexibility in describing the quirks of each chip. This leaves the device tree to its proper role of identifying a programming interface rather than descri

Re: [PATCH 2/4] powerpc/device-tree: bindings for DSP cores/clusters for Freescale SOCs

On Sat, 2015-09-19 at 23:46 +0530, Poonam Aggrwal wrote: > From: poonam aggrwal > > Device Tree Bindings for DSP CPU clusters and DSP CPUs for Freescale PowerPC > SOCs which have DSP CPUs in addition to PowerPC CPUs. > For example B4860 has 3 DSP clusters which have 2 SC3900 cores each. > > Sign

Re: [PATCH 0/7] Phy and mdiobus fixes

Le 09/18/15 02:46, Russell King - ARM Linux a écrit : > Hi, > > While looking at the phy code, I identified a number of weaknesses > where refcounting on device structures was being leaked, where > modules could be removed while in-use, and where the fixed-phy could > end up having unintended cons

[PATCH 2/4] powerpc/device-tree: bindings for DSP cores/clusters for Freescale SOCs

From: poonam aggrwal Device Tree Bindings for DSP CPU clusters and DSP CPUs for Freescale PowerPC SOCs which have DSP CPUs in addition to PowerPC CPUs. For example B4860 has 3 DSP clusters which have 2 SC3900 cores each. Signed-off-by: Poonam Aggrwal --- - based of: git://git.kernel.org/pub/scm

[PATCH 4/4]fsl/powerpc/b4420: Adds DSP cores/clusters and their L2 caches

B4420 has 1 DSP cluster, having 2 DSP cores (SC3900), and a shared L2 cache. Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal --- - based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git branch master arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 6 ++ arc

[PATCH 3/4]fsl/powerpc/b4860: Adds DSP cores/clusters and their L2 caches

B4860 has 3 DSP clusters, each cluster having 2 DSP cores (SC3900), and every cluster has a shared L2 cache. Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal --- - based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git branch master arch/powerpc/boot/dts/fsl/b4

[PATCH 1/4]fsl/powerpc/b4860: Renamed the L2 caches

To make provision for more than one L2 caches in the system, change the name from L2 to L2_1; same as in T4 platforms. * Also remove the L2 entry from common file "arch/powerpc/boot/dts/fsl/b4si-post.dtsi" Keep them only in separate files for b4860 and b4420. Signed-off-by: Shaveta Leekha S

Re: [RFC v2 3/7] powerpc: atomic: Implement atomic{,64}_{add,sub}_return_* variants

Hi Will, On Fri, Sep 18, 2015 at 05:59:02PM +0100, Will Deacon wrote: > On Wed, Sep 16, 2015 at 04:49:31PM +0100, Boqun Feng wrote: > > On powerpc, we don't need a general memory barrier to achieve acquire and > > release semantics, so __atomic_op_{acquire,release} can be implemented > > using "lw

[PATCH] powerpc/iommu: use iommu_num_pages() to calculate the number of iommu page

On PowerPC, currently we support different value of PAGE_SIZE and different value of IOMMU Page Size. In case the PAGE_SIZE is 4K and the IOMMU Page Size is 16M, and driver asked for some DMA less than 16M, the current calculation would return 0 and the following allocation in iommu_alloc() would