Hi David,
Thank you for your feedback, I'll address it and re-submit.
Regards,
Igal Liberman
> -Original Message-
> From: David Miller [mailto:da...@davemloft.net]
> Sent: Tuesday, December 01, 2015 11:28 PM
> To: Liberman Igal-B31950
> Cc: net...@vger.kernel.org; linuxppc-dev@lists.ozla
This test does a fork syscall inside a transaction. Basic sniff test to see
if we can enter the kernel during a transaction.
Signed-off-by: Rashmica Gupta
---
Updated description. No functional changes.
tools/testing/selftests/powerpc/tm/.gitignore | 1 +
tools/testing/selftests/powerpc/tm/Mak
If the transaction is aborted, the DSCR should be rolled back to the
checkpointed value before the transaction began. The value written to the
DSCR when transaction was suspended should only persist if the transaction
is successful.
Signed-off-by: Rashmica Gupta
---
No functional changes. Fixed w
If the transaction is aborted, the TAR should be rolled back to the
checkpointed value before the transaction began. The value written to the
TAR when the transaction is suspended should only remain there if the
transaction completes successfully.
Signed-off-by: Rashmica Gupta
---
Added more expl
In eeh_pe_loc_get(), the PE location code is retrieved from the
"ibm,loc-code" property of the device node for the bridge of the
PE's primary bus. It's not correct because the property indicates
the parent PE's location code.
This reads the correct PE location code from "ibm,io-base-loc-code"
or "
On Fri, 27 Nov 2015, Petr Mladek wrote:
> MN10300 has its own implementation for entering and exiting NMI
> handlers. It does not call nmi_enter() and nmi_exit(). Please, find
> below an updated patch that adds printk_nmi_enter() and
> printk_nmi_exit() to the custom entry points. Then we could
> On Nov 27, 2015, at 19:09, Petr Mladek wrote:
>
> Testing has shown that the backtrace sometimes does not fit
> into the 4kB temporary buffer that is used in NMI context.
>
> The warnings are gone when I double the temporary buffer size.
>
> Note that this problem existed even in the x86-spe
On Nov 27, 2015, at 19:09, Petr Mladek wrote:Testing has shown that the backtrace sometimes does not fitinto the 4kB temporary buffer that is used in NMI context.The warnings are gone when I double the temporary buffer size.Note that this problem existed even in the x86-specificimplementation that
On 12/02/2015 08:52 AM, Rashmica Gupta wrote:
> If the transaction is aborted, the TAR should be rolled back to the
> checkpointed value before the transaction began.
And if it does not abort, it should continue to hold the changed
(inside the transaction) TAR value after the transaction finishes.
Hi all,
We tested some 4.3 kernels on a P.A. Semi reference board. Ultimately,
ethernet does not work, though on the reference board, the interface is
detected, gets link, but will not pass any packets/traffic.
Somewhere in the source code of the commit "'powerpc-4.3-1' of
git://git.kernel.o
On 12/02/2015 09:10 AM, Michael Ellerman wrote:
> On Tue, 2015-12-01 at 13:38 +0530, Anshuman Khandual wrote:
>> > On 12/01/2015 10:38 AM, Rashmica Gupta wrote:
>>> > > Currently tbegin, tend etc are written as opcodes or asm instructions.
>>> > > So
>>> > > standardise these to asm instructions.
If the transaction is aborted, the TAR should be rolled back to the
checkpointed value before the transaction began.
Signed-off-by: Rashmica Gupta
---
Somehow had a missing brace and extra whitespace.
tools/testing/selftests/powerpc/tm/.gitignore | 1 +
tools/testing/selftests/powerpc/tm/Make
On Tue, 2015-12-01 at 13:38 +0530, Anshuman Khandual wrote:
> On 12/01/2015 10:38 AM, Rashmica Gupta wrote:
> > Currently tbegin, tend etc are written as opcodes or asm instructions. So
> > standardise these to asm instructions.
>
> I think the asm instructions can be used with only newer versions
If the transaction is aborted, the TAR should be rolled back to the
checkpointed value before the transaction began.
Signed-off-by: Rashmica Gupta
---
To check this yourself, undo the changes from the patch "powerpc/tm: Fix
context switching TAR, PPR and DSCR SPRs".
tools/testing/selftests/powe
On Fri, 2015-11-27 at 12:09 +0100, Petr Mladek wrote:
> printk() takes some locks and could not be used a safe way in NMI
> context.
>
> The chance of a deadlock is real especially when printing
> stacks from all CPUs. This particular problem has been addressed
> on x86 by the commit a9edc8809328
Hi Rashmica,
Just a few nits ...
Your subject: selftests/powerpc: Add test to check is DSCR is corrupted.
Looks like it might want to be "if DSCR is" ?
On Wed, 2015-12-02 at 11:02 +1100, Rashmica Gupta wrote:
> If the transaction is aborted, the DSCR should be rolled back to the
> checkpointed
2015-12-01 21:34 GMT-03:00 Daniel Axtens :
> "Geyslan G. Bem" writes:
>
>> The vcpu_book3s struct is assigned but never used. So remove it.
>
> Just out of interest, how did you find this? Compiler warning? Static
> analysis? Manual inspection?
Sorry, I should have done the patch self contained.
"Geyslan G. Bem" writes:
> The vcpu_book3s struct is assigned but never used. So remove it.
Just out of interest, how did you find this? Compiler warning? Static
analysis? Manual inspection?
Thanks in advance!
Regards,
Daniel
>
> Signed-off-by: Geyslan G. Bem
> ---
> arch/powerpc/kvm/book3s
If the transaction is aborted, the DSCR should be rolled back to the
checkpointed value before the transaction began.
Signed-off-by: Rashmica Gupta
---
To check this yourself, undo the changes from the patch "powerpc/tm: Fix
context switching TAR, PPR and DSCR SPRs".
tools/testing/selftests/pow
On Fri, Nov 27, 2015 at 12:09:30PM +0100, Petr Mladek wrote:
> What we can do, though, is to zap all printk locks. We already do this
> when a printk recursion is detected. This should be safe because
> the system is crashing and there shouldn't be any printk caller
> that would cause the deadlock.
The vcpu_book3s struct is assigned but never used. So remove it.
Signed-off-by: Geyslan G. Bem
---
arch/powerpc/kvm/book3s_64_mmu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c
index 774a253..9bf7031 100644
--- a/arch/p
As far as I'm aware, the kernel used to crash when forking inside a
transaction (see powerpc/tm: Fix crash when forking inside a
transaction). So this is to check that the transaction aborts rather
than your whole kernel crashing.
On 01/12/15 19:11, Anshuman Khandual wrote:
On 12/01/2015 10:3
On Tue, 2015-12-01 at 22:23 +1100, Michael Ellerman wrote:
> On Thu, 2015-10-29 at 11:43 +1100, Anton Blanchard wrote:
>
> > mtmsrd_isync() will do an mtmsrd followed by an isync on older
> > processors. On newer processors we avoid the isync via a feature fixup.
> >
> > diff --git a/arch/power
Hi folks,
The powerpc next branch is open, if you haven't already, please send your
patches for 4.5 now.
cheers
___
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On Tue, 2015-12-01 at 18:29 +0100, Torsten Duwe wrote:
> On Thu, Nov 26, 2015 at 01:04:19PM +0300, Denis Kirjanov wrote:
> > > diff --git a/arch/powerpc/kernel/entry_64.S
> > > b/arch/powerpc/kernel/entry_64.S
> > > index 8d56b16..3309dd8 100644
> > > --- a/arch/powerpc/kernel/entry_64.S
> > > +++
From:
Date: Mon, 30 Nov 2015 14:20:58 +0200
> +typedef irqreturn_t (fman_exceptions_cb)(struct fman *fman,
> + enum fman_exceptions exception);
Function and function pointer declarations and definitions should be
indented such that the second and subsequent l
On 11/25/2015 11:13 PM, Michael Ellerman wrote:
> On Tue, 2015-10-27 at 13:27 -0500, Nathan Fontenot wrote:
>
>> Add the ability to hotplug add cpus via rtas hotplug events by either
>> specifying the drc index of the CPU to add, or providing a count of the
>> number of CPUs to add.
>
> So I just
On 11/25/2015 11:02 PM, Michael Ellerman wrote:
> On Tue, 2015-10-27 at 13:26 -0500, Nathan Fontenot wrote:
>
>> Add the ability to dlpar remove CPUs via hotplug rtas events, either by
>> specifying the drc-index of the CPU to remove or providing a count of cpus
>> to remove.
>>
>> diff --git a/ar
On Thu, Nov 26, 2015 at 01:04:19PM +0300, Denis Kirjanov wrote:
> > diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
> > index 8d56b16..3309dd8 100644
> > --- a/arch/powerpc/kernel/entry_64.S
> > +++ b/arch/powerpc/kernel/entry_64.S
> Linux style for comments is the C89.
Hi All,
I compiled a lot of kernels for some git bisects and I have a result.
Test log
Kernel 4.3 git from Tue Sep 01, 2015 -> PA Semi Ethernet works
Kernel 4.3 git from Wed Sep 02, 2015 -> PA Semi Ethernet works
Kernel 4.3 git from Thu Sep 03, 2015 -> PA Semi Ethernet works
Kernel 4.3 git from
On Thu, Nov 26, 2015 at 10:41:53AM +1100, Michael Ellerman wrote:
> On Wed, 2015-11-25 at 17:16 +0100, Torsten Duwe wrote:
> > On Tue, Sep 15, 2015 at 03:48:34PM +1000, Ian Munsie wrote:
> > > --- a/drivers/misc/cxl/Makefile
> > > +++ b/drivers/misc/cxl/Makefile
> > > @@ -1,4 +1,4 @@
> > > -ccflags
On Tue, Dec 01, 2015 at 10:41:42AM -0200, Guilherme G. Piccoli wrote:
> On 11/30/2015 11:35 PM, Bjorn Helgaas wrote:
> >Thanks for your patience, Guilherme.
>
> Hello Bjorn, thank you for the very deep review of my patch. Much
> appreciated!
>
>
> >I applied this to pci/msi for v4.5. I reworked
On 11/30/2015 11:35 PM, Bjorn Helgaas wrote:
Thanks for your patience, Guilherme.
Hello Bjorn, thank you for the very deep review of my patch. Much
appreciated!
I applied this to pci/msi for v4.5. I reworked the changelog and made
pci_msi_setup_pci_dev() static, since I think it's now onl
This patch adds the following algorithms to the talitos driver:
* ecb(aes)
* ctr(aes)
* ecb(des)
* cbc(des)
* ecb(des3_ede)
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 83
drivers/crypto/talitos.h | 1 +
2 files changed, 84 ins
On Thu, 2015-10-29 at 11:43 +1100, Anton Blanchard wrote:
> mtmsrd_isync() will do an mtmsrd followed by an isync on older
> processors. On newer processors we avoid the isync via a feature fixup.
>
> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> index ef64219..5bf8
On Thu, 2015-10-29 at 11:44 +1100, Anton Blanchard wrote:
> Move the MSR modification into new c functions. Removing it from
> the low level functions will allow us to avoid costly MSR writes
> by batching them up.
>
> Move the check_if_tm_restore_required() check into these new functions.
> dif
Kernel prints respective warnings about various EPOW events for
user information/action after parsing EPOW interrupts. At times
below EPOW reset event warning is seen to be flooding kernel log
over a period of time.
May 25 03:46:34 alp kernel: Non critical power or cooling issue cleared
May 25 03:
On Tuesday 01 December 2015 14:51:38 Rashmica Gupta wrote:
> All users of QPACE have upgraded to QPACE2 so remove the Cell QPACE code.
>
> Signed-off-by: Rashmica Gupta
> ---
> Also removed the reference to QPACE in the Documentation.
>
Acked-by: Arnd Bergmann
_
On Tuesday 01 December 2015 09:16 AM, Michael Ellerman wrote:
On Mon, 2015-11-30 at 17:31 +0530, Vipin K Parashar wrote:
On Thursday 26 November 2015 02:50 PM, Vasant Hegde wrote:
On 11/18/2015 02:12 PM, Vipin K Parashar wrote:
Kernel prints respective warnings about various EPOW events for
On 12/01/2015 10:38 AM, Rashmica Gupta wrote:
> +int test_fork(void)
> +{
> + SKIP_IF(!have_htm());
> +
> + asm __volatile__(
> + "tbegin.;"
> + "blt1f; "
> + "li 0, 2;" /* fork syscall */
> + "sc ;"
> + "tend.;"
> +
On 12/01/2015 10:38 AM, Rashmica Gupta wrote:
> Currently tbegin, tend etc are written as opcodes or asm instructions. So
> standardise these to asm instructions.
I think the asm instructions can be used with only newer versions of GCC.
But not sure, does it work with the older gcc as well ?
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