Re: [PATCH 3/3] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers.

On 02/25/2016 10:25 AM, Mahesh J Salgaonkar wrote: > From: Mahesh Salgaonkar > > The current implementation of MCE early handling modifies CR0/1 registers > without saving its old values. Fix this by moving early check for > powersaving mode to

Re: [PATCH 02/12] powerpc/module: Mark module stubs with a magic value

On Thu, 2016-02-25 at 11:04 +1100, Balbir Singh wrote: > > On 25/02/16 01:28, Michael Ellerman wrote: > > -bool is_module_trampoline(u32 *p) > > +int module_trampoline_target(struct module *mod, unsigned long addr, > > +unsigned long *target) > > { > > - unsigned int i;

Re: [PATCH v5 1/9] selftests/powerpc: Test the preservation of FPU and VMX regs across syscall

On 2016/02/25 10:44AM, Cyril Bur wrote: > On Wed, 24 Feb 2016 19:57:38 +0530 > "Naveen N. Rao" wrote: > > > On 2016/02/23 02:38PM, Cyril Bur wrote: > > > Test that the non volatile floating point and Altivec registers get > > > correctly preserved across the

Re: [PATCH v5 1/9] selftests/powerpc: Test the preservation of FPU and VMX regs across syscall

On Tue, 23 Feb 2016 14:38:14 +1100 Cyril Bur wrote: > Test that the non volatile floating point and Altivec registers get > correctly preserved across the fork() syscall. > > fork() works nicely for this purpose, the registers should be the same for > both parent and child >

Re: [PATCH V4 05/18] powerpc/mm: Don't have conditional defines for real_pte_t

On 23/02/16 15:48, Aneesh Kumar K.V wrote: > We remove real_pte_t out of STRICT_MM_TYPESCHECK. > > Signed-off-by: Aneesh Kumar K.V > The changelog does not explain why Balbir ___ Linuxppc-dev mailing list

Re: [PATCH v2 1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

On Thu, 2016-02-25 at 05:55 +, Qiang Zhao wrote: > On Thu, 2016-02-25 at 11:12 AM, Scott Wood wrote: > > -Original Message- > > From: Scott Wood [mailto:o...@buserror.net] > > Sent: Thursday, February 25, 2016 11:12 AM > > To: Qiang Zhao ; Rob Herring

RE: [PATCH v2 1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

On Thu, 2016-02-25 at 11:12 AM, Scott Wood wrote: > -Original Message- > From: Scott Wood [mailto:o...@buserror.net] > Sent: Thursday, February 25, 2016 11:12 AM > To: Qiang Zhao ; Rob Herring > Cc: Yang-Leo Li ;

RE: [PATCH v2 1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

On Wed, 2016-02-24 at 04:20 AM, Scott Wood wrote: > -Original Message- > From: Scott Wood [mailto:o...@buserror.net] > Sent: Wednesday, February 24, 2016 4:20 AM > To: Rob Herring ; Qiang Zhao > Cc: Yang-Leo Li ;

Re: Problems with swapping in v4.5-rc on POWER

On Thu, 25 Feb 2016, Aneesh Kumar K.V wrote: > > Can you test the impact of the merge listed below ?(ie, revert the merge and > see if > we can reproduce and also verify with merge applied). This will give us a > set of commits to look closer. We had quiet a lot of page table > related changes

Re: [PATCH V4 11/18] powerpc/mm: Hugetlbfs is book3s_64 and fsl_book3e (32 or 64)

On Tue, Feb 23, 2016 at 10:18:13AM +0530, Aneesh Kumar K.V wrote: > We move large part of fsl related code to hugetlbpage-book3e.c. > Only code movement. This also avoid #ifdef in the code. > > Eventhough we allow hugetlbfs only for book3s 64 and fsl book3e, I am > still retaining the #ifdef in

Re: Problems with swapping in v4.5-rc on POWER

On Thu, 25 Feb 2016, Michael Ellerman wrote: > > I do run tests on G5, but obviously not rigorously enough. I kicked off a few > kernel builds on mine and it survived, though once it hits swap it's almost > unusably slow. I'll leave it running overnight and see if I hit anything. Oh yes, I'd

Re: [PATCH V4 04/18] powerpc/mm: Split pgtable types to separate header

On 25/02/16 14:12, Paul Mackerras wrote: > On Tue, Feb 23, 2016 at 10:18:06AM +0530, Aneesh Kumar K.V wrote: >> We move the page table accessors into a separate header. We will >> later add a big endian variant of the table which is needed for radix. >> No functionality change only code

Re: [net-next PATCH v3] ibmvnic: map L2/L3/L4 header descriptors to firmware

From: Thomas Falcon Date: Wed, 24 Feb 2016 21:34:43 -0600 > + > +static union sub_crq *build_hdr_descs_arr(struct sk_buff *skb, > + int *num_entries, > + union sub_crq subcrq, u8 hdr_field) >

RE: [PATCH v2 2/7] QE: Add ucc hdlc document to bindings

On Wen, Feb 24, 2016 at 04:22AM, Rob Herring wrote: > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Wednesday, February 24, 2016 4:22 AM > To: Qiang Zhao > Cc: o...@buserror.net; Yang-Leo Li ; linux- >

[PATCH] powerpc/p5040: Add device node for RAID Engine

From: Xuelin Shi add the missing RAID Engine device node for p5040. otherwise, the device can not be detected. Signed-off-by: Xuelin Shi --- arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 1 + arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 6 ++ 2

Re: [PATCH V4 02/18] mm: Some arch may want to use HPAGE_PMD related values as variables

On 23/02/16 15:48, Aneesh Kumar K.V wrote: > From: "Kirill A. Shutemov" In the changelog, strip from here <-- > With next generation power processor, we are having a new mmu model > [1] that require us to maintain a different linux page table format. > > Inorder

[PATCH 3/3] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers.

From: Mahesh Salgaonkar The current implementation of MCE early handling modifies CR0/1 registers without saving its old values. Fix this by moving early check for powersaving mode to machine_check_handle_early(). The power architecture 2.06 or later allows the

[PATCH 2/3] powernv: Rename pSeries to powenv from machine_check_pSeries_early.

From: Mahesh Salgaonkar The routine machine_check_pSeries_early() is only used on powernv, not pseries. Hence rename machine_check_pSeries_early to machine_check_powernv_early. Reported-by: Paul Mackerras Signed-off-by: Mahesh Salgaonkar

[PATCH 1/3] powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h

From: Mahesh Salgaonkar Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h so that MCE handler changes in subsequent patch can use it. No functionality change. Signed-off-by: Mahesh Salgaonkar --- arch/powerpc/include/asm/cpuidle.h | 14

Re: [PATCH V4 08/18] powerpc/mm: Copy pgalloc (part 1)

On Tue, Feb 23, 2016 at 10:18:10AM +0530, Aneesh Kumar K.V wrote: > This patch make a copy of pgalloc routines for book3s. The idea is to > enable a hash64 copy of these pgalloc routines which can be later > updated to have a radix conditional. Radix introduce a new page table > format with

Re: [PATCH V4 07/18] powerpc/mm: Update masked bits for linux page table

On Tue, Feb 23, 2016 at 10:18:09AM +0530, Aneesh Kumar K.V wrote: > We now use physical address in upper page table tree levels. Even though > they are aligned to their size, for the masked bits we use the > overloaded bit positions as per PowerISA 3.0. We keep the bad bits check > as it is, and

Re: [PATCH V4 05/18] powerpc/mm: Don't have conditional defines for real_pte_t

On Tue, Feb 23, 2016 at 10:18:07AM +0530, Aneesh Kumar K.V wrote: > We remove real_pte_t out of STRICT_MM_TYPESCHECK. > > Signed-off-by: Aneesh Kumar K.V Reviewed-by: Paul Mackerras ___ Linuxppc-dev

Re: [PATCH V4 06/18] powerpc/mm: Switch book3s 64 with 64K page size to 4 level page table

On Tue, Feb 23, 2016 at 10:18:08AM +0530, Aneesh Kumar K.V wrote: > This is needed so that we can support both hash and radix page table > using single kernel. Radix kernel uses a 4 level table. > > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/Kconfig

Re: Problems with swapping in v4.5-rc on POWER

Hugh Dickins writes: > I've plagiarized the subject from Paulus's "Problems with THP" mail > last weekend; but my similar problems are on PowerMac G5 baremetal, > with 4kB pages, not capable of THP and no THP configured in. > > Under heavily swapping load, running kernel builds

RE: [PATCH v2 3/7] QE: Add uqe_serial document to bindings

On Wed, Feb 24, 2016 at 04:24AM, Rob Herring wrote: > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Wednesday, February 24, 2016 4:24 AM > To: Qiang Zhao > Cc: o...@buserror.net; Yang-Leo Li ; linux- >

Re: [PATCH 01/12] powerpc/module: Only try to generate the ftrace_caller() stub once

On 25/02/16 10:55, Balbir Singh wrote: > > On 25/02/16 01:28, Michael Ellerman wrote: >> Currently we generate the module stub for ftrace_caller() at the bottom >> of apply_relocate_add(). However apply_relocate_add() is potentially >> called more than once per module, which means we will try to

Re: [PATCH V4 00/18] Book3s abstraction in preparation for new MMU model

On Tue, 2016-02-23 at 14:56 +0530, Aneesh Kumar K.V wrote: > "Aneesh Kumar K.V" writes: > > > Hello, > > > > This series mostly consisting of code movement. One new thing added in > > this series > > is to switch book3s 64 to 4 level page table. The changes are

Re: [PATCH V4 15/18] powerpc/mm: Move hash page table related functions to pgtable-hash64.c

On Tue, 2016-02-23 at 10:18 +0530, Aneesh Kumar K.V wrote: > > diff --git a/arch/powerpc/mm/pgtable-book3e.c b/arch/powerpc/mm/pgtable > -book3e.c > new file mode 100644 > index ..bdaa4376f838 > --- /dev/null > +++ b/arch/powerpc/mm/pgtable-book3e.c > @@ -0,0 +1,163 @@ > + > +/* > + *

Re: Problems with swapping in v4.5-rc on POWER

On Wed, 2016-02-24 at 18:10 -0800, Hugh Dickins via Linuxppc-dev wrote: > I've plagiarized the subject from Paulus's "Problems with THP" mail > last weekend; but my similar problems are on PowerMac G5 baremetal, > with 4kB pages, not capable of THP and no THP configured in. > > Under heavily

[net-next PATCH v3] ibmvnic: map L2/L3/L4 header descriptors to firmware

Allow the VNIC driver to provide descriptors containing L2/L3/L4 headers to firmware. This feature is needed for greater hardware compatibility and enablement of offloading technologies for some backing hardware. Signed-off-by: Thomas Falcon --- v2: Fixed typo error

Re: [PATCH V4 04/18] powerpc/mm: Split pgtable types to separate header

On Tue, Feb 23, 2016 at 10:18:06AM +0530, Aneesh Kumar K.V wrote: > We move the page table accessors into a separate header. We will > later add a big endian variant of the table which is needed for radix. > No functionality change only code movement. > > Signed-off-by: Aneesh Kumar K.V

Re: [PATCH v2 1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

On Thu, 2016-02-25 at 03:10 +, Qiang Zhao wrote: > On Wed, 2016-02-24 at 04:20 AM, Scott Wood wrote: > > -Original Message- > > From: Scott Wood [mailto:o...@buserror.net] > > Sent: Wednesday, February 24, 2016 4:20 AM > > To: Rob Herring ; Qiang Zhao

[PATCH v10 57/59] PCI: Introduce resource_disabled()

Current is using !flags, and we are going to use IORESOURCE_DISABLED instead of clearing resource flags. Let's convert all !flags to helper function resource_disabled(). resource_disabled will check !flags and IORESOURCE_DISABLED both. Cc: linux-al...@vger.kernel.org Cc:

[PATCH v10 09/59] powerpc/PCI: Add IORESOURCE_MEM_64 for 64-bit resource in OF parsing

For device resource PREF bit setting under bridge 64-bit pref resource, we need to make sure only set PREF for 64bit resource. This patch set IORESOUCE_MEM_64 for 64bit resource during OF device resource flags parsing. Link: https://bugzilla.kernel.org/show_bug.cgi?id=96261 Link:

[PATCH v10 51/59] PCI: Unify skip_ioresource_align()

There are powerpc generic version and x86 local version for skip_ioresource_align(). Move the powerpc version to setup-bus.c, and kill x86 local version. Also kill dummy version in microblaze. Cc: Michal Simek Cc: Paul Mackerras Cc: Michael Ellerman

Problems with swapping in v4.5-rc on POWER

I've plagiarized the subject from Paulus's "Problems with THP" mail last weekend; but my similar problems are on PowerMac G5 baremetal, with 4kB pages, not capable of THP and no THP configured in. Under heavily swapping load, running kernel builds on tmpfs in limited memory, I've been seeing

Re: [PATCH] cxl: Fix PSL timebase synchronization detection

Frederic Barrat writes: > The PSL timebase synchronization is seemingly failing for > configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver > shows the following trace in dmesg: > PSL: Timebase sync: giving up! > > The PSL timebase register is actually

Re: [PATCH 12/12] powerpc/ftrace: Disable profiling for some files

On 25/02/16 01:28, Michael Ellerman wrote: > From: Torsten Duwe > > Using -mprofile-kernel on early boot code not only confuses the > checker but is also useless, as the infrastructure is not yet in > place. Proceed like with -pg (remove it from CFLAGS), equally with > time.o,

Re: [PATCH 10/12] powerpc/ftrace: FTRACE_WITH_REGS configuration variables

On 25/02/16 01:28, Michael Ellerman wrote: > From: Torsten Duwe > > * arch/powerpc/Makefile: > - globally use -mprofile-kernel in case it's configured, > available and bug-free. > * arch/powerpc/gcc-mprofile-kernel-notrace.sh: > - make sure -mprofile-kernel works

Re: [PATCH 09/12] powerpc/ftrace: Use generic ftrace_modify_all_code()

On 25/02/16 01:28, Michael Ellerman wrote: > From: Torsten Duwe > > Convert powerpc's arch_ftrace_update_code() from its own version to use > the generic default functionality (without stop_machine -- our > instructions are properly aligned and the replacements atomic). > > With

Re: [PATCH 08/12] powerpc/ftrace: Rework ftrace_caller()

On 25/02/16 01:28, Michael Ellerman wrote: > The main change is to just use paca->kernel_toc, rather than a branch to > +4 and mflr etc. That makes the code simpler and should also perform > better. > > There was also a sequence after ftrace_call() where we load from > pt_regs->nip, move to LR,

Re: [PATCH 07/12] powerpc/ftrace: FTRACE_WITH_REGS implementation for ppc64le

On 25/02/16 01:28, Michael Ellerman wrote: > From: Torsten Duwe > > Implement FTRACE_WITH_REGS for powerpc64, on ELF ABI v2. > Initial work started by Vojtech Pavlik, used with permission. > > * arch/powerpc/kernel/entry_64.S: > - Implement an effective ftrace_caller that

Re: [PATCH] cxl: Fix PSL timebase synchronization detection

On 25/02/16 04:27, Frederic Barrat wrote: The PSL timebase synchronization is seemingly failing for configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver shows the following trace in dmesg: PSL: Timebase sync: giving up! The PSL timebase register is actually syncing correctly, but

Re: [PATCH 05/12] powerpc/ftrace: ftrace_graph_caller() needs to save/restore toc

On 25/02/16 01:28, Michael Ellerman wrote: > Signed-off-by: Michael Ellerman > --- > arch/powerpc/kernel/entry_64.S | 8 > 1 file changed, 8 insertions(+) > > Squash. > > diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S > index

Re: [PATCH 04/12] powerpc/ftrace: Prepare for -mprofile-kernel

On 25/02/16 01:28, Michael Ellerman wrote: > From: Torsten Duwe > > The gcc switch -mprofile-kernel, available for ppc64 on gcc > 4.8.5, > allows to call _mcount very early in the function, which low-level > ASM code and code patching functions need to consider. > Especially the

Re: [PATCH] cxl: Fix PSL timebase synchronization detection

Acked-by: Ian Munsie ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH 03/12] powerpc/module: Create a special stub for ftrace_caller()

On 25/02/16 01:28, Michael Ellerman wrote: > In order to support the new -mprofile-kernel ABI, we need to be able to > call from the module back to ftrace_caller() (in the kernel) without > using the module's r2. That is because the function in this module which > is calling ftrace_caller() may

Re: [PATCH 02/12] powerpc/module: Mark module stubs with a magic value

On 25/02/16 01:28, Michael Ellerman wrote: > When a module is loaded, calls out to the kernel go via a stub which is > generated at runtime. One of these stubs is used to call _mcount(), > which is the default target of tracing calls generated by the compiler > with -pg. > > If dynamic ftrace is

[PATCH 2/2] numa, mm, cleanup: remove redundant NODE_DATA macro from asm header files.

From: Ganapatrao Kulkarni NODE_DATA is defined across multiple asm header files. Moving generic definition to asm-generic/mmzone.h to remove redundant definitions. Reviewed-by: Robert Richter Signed-off-by: Ganapatrao Kulkarni

[PATCH 1/2] topology, cleanup: Avoid redefinition of cpumask_of_pcibus in asm header files.

From: Ganapatrao Kulkarni At present cpumask_of_pcibus is defined for !CONFIG_NUMA and moving out to common will allow to use for numa too. This also avoids redefinition of this macro in respective architecture header files. Reviewed-by: Robert Richter

[PATCH 0/2] NUMA related header file cleanups.

From: David Daney Refactor many architectures' cpumask_of_pcibus and NODE_DATA definitions by moving them to asm-generic. Tested on arm64. Build tested on ia64, m32r, powerpc, s390, sh, sparc(64), tile, x86 This patch set (arm64 portion) depends on this one:

Re: [PATCH 01/12] powerpc/module: Only try to generate the ftrace_caller() stub once

On 25/02/16 01:28, Michael Ellerman wrote: > Currently we generate the module stub for ftrace_caller() at the bottom > of apply_relocate_add(). However apply_relocate_add() is potentially > called more than once per module, which means we will try to generate > the ftrace_caller() stub multiple

Re: [PATCH v5 1/9] selftests/powerpc: Test the preservation of FPU and VMX regs across syscall

On Wed, 24 Feb 2016 19:57:38 +0530 "Naveen N. Rao" wrote: > On 2016/02/23 02:38PM, Cyril Bur wrote: > > Test that the non volatile floating point and Altivec registers get > > correctly preserved across the fork() syscall. > > > > fork() works nicely for this

Re: [PATCH 06/12] powerpc/module: Rework is_early_mcount_callsite()

On 25/02/16 01:28, Michael Ellerman wrote: > is_early_mcount_callsite() needs to detect either the two instruction or > the three instruction versions of the _mcount() sequence. > > But if we're running a kernel with the two instruction sequence, we need > to be careful not to read instruction -

[net-next PATCH v2] ibmvnic: map L2/L3/L4 header descriptors to firmware

From: root Allow the VNIC driver to provide descriptors containing L2/L3/L4 headers to firmware. This feature is needed for greater hardware compatibility and enablement of offloading technologies for some backing hardware. Signed-off-by: Thomas Falcon

Re: [PATCH v5 17/18] cxl: Adapter failure handling

Reviewed-by: Manoj Kumar --- Manoj Kumar On 2/23/2016 10:21 AM, Frederic Barrat wrote: From: Christophe Lombard Check the AFU state whenever an API is called. The hypervisor may issue a reset of the adapter when it detects a fault.

Re: [PATCH v5 16/18] cxl: Support the cxl kernel API from a guest

Reviewed-by: Manoj Kumar --- Manoj Kumar On 2/23/2016 10:21 AM, Frederic Barrat wrote: Like on bare-metal, the cxl driver creates a virtual PHB and a pci device for the AFU. The configuration space of the device is mapped to the configuration record of the AFU.

Re: [net-next PATCH] ibmvnic: map L2/L3/L4 header descriptors to firmware

Hi Thomas, [auto build test ERROR on net-next/master] url: https://github.com/0day-ci/linux/commits/Thomas-Falcon/ibmvnic-map-L2-L3-L4-header-descriptors-to-firmware/20160225-033734 config: powerpc-allmodconfig (attached as .config) reproduce: wget

[PATCH] powerpc: Fix misspellings in comments.

Signed-off-by: Adam Buchbinder --- arch/powerpc/boot/rs6000.h | 2 +- arch/powerpc/boot/treeboot-akebono.c | 2 +- arch/powerpc/boot/treeboot-currituck.c | 2 +- arch/powerpc/boot/treeboot-iss4xx.c | 2 +-

Re: [PATCH v5 15/18] cxl: Parse device tree and create cxl device(s) at boot

Fred, Christophe: See comment below. --- Manoj Kumar On 2/23/2016 10:21 AM, Frederic Barrat wrote: +module_init(cxl_base_init); Is this a remnant from when there were two modules? Do you really need two module_init() calls (can't one be called from the other)? What is the tear-down portion

Re: [PATCH v5 14/18] cxl: Support to flash a new image on the adapter from a guest

Fred, Christophe: See comments below. -- Manoj Kumar On 2/23/2016 10:21 AM, Frederic Barrat wrote: From: Christophe Lombard +#define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */ Where does this limit of 4 AFUs come from? Is this

[net-next PATCH] ibmvnic: map L2/L3/L4 header descriptors to firmware

Allow the VNIC driver to provide descriptors containing L2/L3/L4 headers to firmware. This feature is needed for greater hardware compatibility and enablement of offloading technologies for some backing hardware. Signed-off-by: Thomas Falcon ---

Re: [PATCH v5 13/18] cxl: sysfs support for guests

Reviewed-by: Manoj Kumar --- Manoj Kumar On 2/23/2016 10:21 AM, Frederic Barrat wrote: From: Christophe Lombard Filter out a few adapter parameters which don't make sense in a guest. Document the changes. Co-authored-by: Frederic

Re: [PATCH v5 12/18] cxl: Add guest-specific code

Reviewed-by: Manoj Kumar --- Manoj Kumar On 2/23/2016 10:21 AM, Frederic Barrat wrote: From: Christophe Lombard The new of.c file contains code to parse the device tree to find out about cxl adapters and AFUs. guest.c implements the

Re: [PATCH] cxl: Fix PSL timebase synchronization detection

Reviewed-by: Matthew R. Ochs ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH] cxl: Fix PSL timebase synchronization detection

On Wed, 2016-02-24 at 18:27 +0100, Frederic Barrat wrote: > The PSL timebase synchronization is seemingly failing for > configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver > shows the following trace in dmesg: > PSL: Timebase sync: giving up! > > The PSL timebase register is

[PATCH] cxl: Fix PSL timebase synchronization detection

The PSL timebase synchronization is seemingly failing for configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver shows the following trace in dmesg: PSL: Timebase sync: giving up! The PSL timebase register is actually syncing correctly, but the cxl driver is not detecting it. Fix is

Re: [BUG] random kernel crashes after THP rework on s390 (maybe also on PowerPC and ARM)

Christian Borntraeger writes: > On 02/24/2016 11:41 AM, Will Deacon wrote: >> On Wed, Feb 24, 2016 at 11:16:34AM +0100, Christian Borntraeger wrote: >>> On 02/23/2016 09:22 PM, Will Deacon wrote: On Tue, Feb 23, 2016 at 10:33:45PM +0300, Kirill A. Shutemov wrote:

Re: [PATCH v5 11/18] cxl: Separate bare-metal fields in adapter and AFU data structures

Reviewed-by: Manoj Kumar --- Manoj Kumar On 2/23/2016 10:21 AM, Frederic Barrat wrote: From: Christophe Lombard Introduce sub-structures containing the bare-metal specific fields in the structures describing the adapter (struct cxl)

Re: [BUG] random kernel crashes after THP rework on s390 (maybe also on PowerPC and ARM)

On Tue, 23 Feb 2016 22:33:45 +0300 "Kirill A. Shutemov" wrote: > On Tue, Feb 23, 2016 at 07:19:07PM +0100, Gerald Schaefer wrote: > > I'll check with Martin, maybe it is actually trivial, then we can > > do a quick test it to rule that one out. > > Oh. I found a bug in

Re: powerpc/eeh: Fix partial hotplug criterion

On Fri, 2016-12-02 at 05:03:05 UTC, Gavin Shan wrote: > During error recovery, the device could be removed as part of the > partial hotplug. The criterion used to come with partial hotplug > is: if the device driver provides error_detected(), slot_reset() > and resume() callbacks, it's immune from

Re: [V2] powerpc/mm/hash: Clear the invalid slot information correctly

On Sat, 2016-20-02 at 15:11:54 UTC, "Aneesh Kumar K.V" wrote: > We can get a hash pte fault with 4k base page size and find the pte > already inserted with 64K base page size. In that case we need to clear > the existing slot information from the old pte. Fix this correctly > > With THP, we also

Re: powerpc/powernv: don't create OPAL msglog sysfs entry if memcons init fails

On Thu, 2016-18-02 at 01:12:54 UTC, Andrew Donnellan wrote: > When initialising OPAL interfaces, there is a possibility that > opal_msglog_init() may fail to initialise the msglog/memory console. > > Fix opal_msglog_sysfs_init() so it doesn't try to create sysfs entry for > the msglog if this

Re: [v2,3/3] powerpc: Add POWER9 cputable entry

On Fri, 2016-19-02 at 00:16:24 UTC, Michael Neuling wrote: > Add a cputable entry for POWER9. More code is required to actually > boot and run on a POWER9 but this gets the base piece in which we can > start building on. > > Copies over from POWER8 except for: > - Adds a new CPU_FTR_ARCH_300 bit

Re: [v2,2/3] powerpc: Use defines for __init_tlb_power[78]

On Fri, 2016-19-02 at 00:16:23 UTC, Michael Neuling wrote: > Use defines for literals __init_tlb_power[78] rather than hand coding > them. > > Signed-off-by: Michael Neuling Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/15b1624b78075d4f52e170600c cheers

Re: [v2, 1/3] powerpc/powernv: Create separate subcores CPU feature bit

On Fri, 2016-19-02 at 00:16:22 UTC, Michael Neuling wrote: > Subcores isn't really part of the 2.07 architecture but currently we > turn it on using the 2.07 feature bit. Subcores is really a POWER8 > specific feature. > > This adds a new CPU_FTR bit just for subcores and moves the subcore >

Re: [PATCH v5 1/9] selftests/powerpc: Test the preservation of FPU and VMX regs across syscall

On 2016/02/23 02:38PM, Cyril Bur wrote: > Test that the non volatile floating point and Altivec registers get > correctly preserved across the fork() syscall. > > fork() works nicely for this purpose, the registers should be the same for > both parent and child > > Signed-off-by: Cyril Bur

[PATCH 12/12] powerpc/ftrace: Disable profiling for some files

From: Torsten Duwe Using -mprofile-kernel on early boot code not only confuses the checker but is also useless, as the infrastructure is not yet in place. Proceed like with -pg (remove it from CFLAGS), equally with time.o, ftrace and its helper files. *

[PATCH 11/12] powerpc/ftrace: Rework __ftrace_make_nop()

__ftrace_make_nop() needs to detect either the two instruction or the three instruction versions of the _mcount() sequence. But if we're running a kernel with the two instruction sequence, we need to be careful not to read from ip - 8, or we'll fault and (possibly) incorrectly declare the

[PATCH 10/12] powerpc/ftrace: FTRACE_WITH_REGS configuration variables

From: Torsten Duwe * arch/powerpc/Makefile: - globally use -mprofile-kernel in case it's configured, available and bug-free. * arch/powerpc/gcc-mprofile-kernel-notrace.sh: - make sure -mprofile-kernel works and has none of the known bugs. *

[PATCH 09/12] powerpc/ftrace: Use generic ftrace_modify_all_code()

From: Torsten Duwe Convert powerpc's arch_ftrace_update_code() from its own version to use the generic default functionality (without stop_machine -- our instructions are properly aligned and the replacements atomic). With this we gain error checking and the much-needed

[PATCH 08/12] powerpc/ftrace: Rework ftrace_caller()

The main change is to just use paca->kernel_toc, rather than a branch to +4 and mflr etc. That makes the code simpler and should also perform better. There was also a sequence after ftrace_call() where we load from pt_regs->nip, move to LR, then a few instructions later load from LRSAVE and move

[PATCH 07/12] powerpc/ftrace: FTRACE_WITH_REGS implementation for ppc64le

From: Torsten Duwe Implement FTRACE_WITH_REGS for powerpc64, on ELF ABI v2. Initial work started by Vojtech Pavlik, used with permission. * arch/powerpc/kernel/entry_64.S: - Implement an effective ftrace_caller that works from within the kernel binary as well as from

[PATCH 06/12] powerpc/module: Rework is_early_mcount_callsite()

is_early_mcount_callsite() needs to detect either the two instruction or the three instruction versions of the _mcount() sequence. But if we're running a kernel with the two instruction sequence, we need to be careful not to read instruction - 2, otherwise we might fall off the front of a page

[PATCH 05/12] powerpc/ftrace: ftrace_graph_caller() needs to save/restore toc

Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/entry_64.S | 8 1 file changed, 8 insertions(+) Squash. diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 2a7313cfbc7d..9e77a2c8f218 100644 ---

[PATCH 04/12] powerpc/ftrace: Prepare for -mprofile-kernel

From: Torsten Duwe The gcc switch -mprofile-kernel, available for ppc64 on gcc > 4.8.5, allows to call _mcount very early in the function, which low-level ASM code and code patching functions need to consider. Especially the link register and the parameter registers are still alive

[PATCH 03/12] powerpc/module: Create a special stub for ftrace_caller()

In order to support the new -mprofile-kernel ABI, we need to be able to call from the module back to ftrace_caller() (in the kernel) without using the module's r2. That is because the function in this module which is calling ftrace_caller() may not have setup r2, if it doesn't otherwise need it

[PATCH 02/12] powerpc/module: Mark module stubs with a magic value

When a module is loaded, calls out to the kernel go via a stub which is generated at runtime. One of these stubs is used to call _mcount(), which is the default target of tracing calls generated by the compiler with -pg. If dynamic ftrace is enabled (which it typicall is), another stub is used to

[PATCH 01/12] powerpc/module: Only try to generate the ftrace_caller() stub once

Currently we generate the module stub for ftrace_caller() at the bottom of apply_relocate_add(). However apply_relocate_add() is potentially called more than once per module, which means we will try to generate the ftrace_caller() stub multiple times. Although the current code deals with that

Re: [PATCH 1/2] powerpc/mm: Enable HugeTLB page migration

On 02/02/2016 11:49 AM, Anshuman Khandual wrote: > On 01/29/2016 02:45 PM, Anshuman Khandual wrote: >> > On 01/28/2016 08:14 PM, Aneesh Kumar K.V wrote: >> > Anshuman Khandual writes: >> > >> >>> >> This enables HugeTLB page migration for PPC64_BOOK3S

Re: [BUG] random kernel crashes after THP rework on s390 (maybe also on PowerPC and ARM)

On Wed, 24 Feb 2016, Martin Schwidefsky wrote: > On Tue, 23 Feb 2016 22:33:45 +0300 > "Kirill A. Shutemov" wrote: > > > On Tue, Feb 23, 2016 at 07:19:07PM +0100, Gerald Schaefer wrote: > > > I'll check with Martin, maybe it is actually trivial, then we can > > > do a quick

[PATCH v8] powerpc32: provide VIRT_CPU_ACCOUNTING

This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture. PPC32 doesn't have the PACA structure, so we use the task_info structure to store the accounting data. In order to reuse on PPC32 the PPC64 functions, all u64 data has been replaced by 'unsigned long' so that it is u32 on PPC32 and u64

Re: Question on follow_page_mask

On 02/24/2016 02:37 AM, Hugh Dickins via Linuxppc-dev wrote: > On Tue, 23 Feb 2016, Kirill A. Shutemov wrote: >> On Tue, Feb 23, 2016 at 06:45:05PM +0530, Anshuman Khandual wrote: >>> Not able to understand the first code block of follow_page_mask >>> function. follow_huge_addr function is

Re: Question on follow_page_mask

On 02/23/2016 07:33 PM, Kirill A. Shutemov wrote: > On Tue, Feb 23, 2016 at 06:45:05PM +0530, Anshuman Khandual wrote: >> Not able to understand the first code block of follow_page_mask >> function. follow_huge_addr function is expected to find the page >> struct for the given address if it turns

Re: [PATCH v8 8/8] livepatch: Detect offset for the ftrace location during build

On 24/02/16 20:23, Torsten Duwe wrote: > On Wed, Feb 24, 2016 at 05:55:35PM +1100, Balbir Singh wrote: >> >> >> We need to remove the SQUASH_TOC_SAVE_INSNS bits as well, now that the >> ppc64_profile_stub_insns does not save r2 > Sure -- this was meant to _replace_ the changes from patch 2/8,

Re: [BUG] random kernel crashes after THP rework on s390 (maybe also on PowerPC and ARM)

On Wed, Feb 24, 2016 at 11:51:47AM +0100, Christian Borntraeger wrote: > On 02/24/2016 11:41 AM, Will Deacon wrote: > > On Wed, Feb 24, 2016 at 11:16:34AM +0100, Christian Borntraeger wrote: > >> Without that fix we would clearly have stale tlb entries, no? > > > > Yes, but AFAIU the sequence on

Re: [BUG] random kernel crashes after THP rework on s390 (maybe also on PowerPC and ARM)

On 02/24/2016 11:41 AM, Will Deacon wrote: > On Wed, Feb 24, 2016 at 11:16:34AM +0100, Christian Borntraeger wrote: >> On 02/23/2016 09:22 PM, Will Deacon wrote: >>> On Tue, Feb 23, 2016 at 10:33:45PM +0300, Kirill A. Shutemov wrote: On Tue, Feb 23, 2016 at 07:19:07PM +0100, Gerald Schaefer

Re: [BUG] random kernel crashes after THP rework on s390 (maybe also on PowerPC and ARM)

On Wed, Feb 24, 2016 at 11:16:34AM +0100, Christian Borntraeger wrote: > On 02/23/2016 09:22 PM, Will Deacon wrote: > > On Tue, Feb 23, 2016 at 10:33:45PM +0300, Kirill A. Shutemov wrote: > >> On Tue, Feb 23, 2016 at 07:19:07PM +0100, Gerald Schaefer wrote: > >>> I'll check with Martin, maybe it

Re: [BUG] random kernel crashes after THP rework on s390 (maybe also on PowerPC and ARM)

On 02/23/2016 09:22 PM, Will Deacon wrote: > On Tue, Feb 23, 2016 at 10:33:45PM +0300, Kirill A. Shutemov wrote: >> On Tue, Feb 23, 2016 at 07:19:07PM +0100, Gerald Schaefer wrote: >>> I'll check with Martin, maybe it is actually trivial, then we can >>> do a quick test it to rule that one out. >>

Re: [RFC] Fix si->si_code for guard page access on PowerPC

Hi Gustavo, On Fri, 2016-22-01 at 16:23:31 UTC, Gustavo Romero wrote: > Fix si->si_code for guard page access on PowerPC > ... > > diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c > index a67c6d7..6954971 100644 > --- a/arch/powerpc/mm/fault.c > +++ b/arch/powerpc/mm/fault.c > @@

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