Signed-off-by: Cyril Bur
---
arch/powerpc/kernel/process.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 56444a6..7625976 100644
--- a/arch/powerpc/kernel/process.c
+++ b
Currently copy_thread() doesn't flush SPRs to the parent thread struct.
Currently this only affects the TAR register as perf takes care of some of the
others and the remaining ones are all Event Based Branch (EBB) registers which
are cleared across fork().
Signed-off-by: Cyril Bur
---
arch/power
Currently start_thread() doesn't sanitise TAR.
The TAR SPR register is a register that can be set and branched to, not
sanitising it presents an information leak to the new executable.
Other SPR registers such as the Performance registers used by perf (and are
managed entirely by perf) as well as
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/syscalls/Makefile | 3 +-
.../testing/selftests/powerpc/syscalls/spr_exec.c | 78 ++
2 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 tools/testing/selftests/powerpc/syscalls/spr_exec.c
diff -
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/syscalls/Makefile | 3 +-
.../testing/selftests/powerpc/syscalls/spr_fork.c | 78 ++
2 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 tools/testing/selftests/powerpc/syscalls/spr_fork.c
diff -
Samuel Mendoza-Jonas writes:
> Commit 2def86a7200c
> ("hvc: Convert to using interrupts instead of opal events")
> enabled the use of interrupts in the hvc_driver for OPAL platforms.
> However on machines with more than one hvc console, any console after
> the first will fail to register an interr
Hi Rashmica,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.5 next-20160322]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Rashmica-Gupta/powerpc-pagetable-Add-option
On Tue, Mar 22, 2016 at 11:34:55AM +1100, Alexey Kardashevskiy wrote:
> Uff, lost cc: list. Added back. Some comments below.
>
>
> On 03/21/2016 04:19 PM, David Gibson wrote:
> >On Fri, Mar 18, 2016 at 11:12:26PM +1100, Alexey Kardashevskiy wrote:
> >>On March 15, 2016 17:29:26 David Gibson wrot
On Wed, 2016-03-23 at 11:38 +1100, Michael Ellerman wrote:
> On Tue, 2016-22-03 at 00:34:55 UTC, Russell Currey wrote:
> >
> > In the configure_pe and configure_bridge RTAS calls, the spec states
> > that values of 9900-9905 can be returned, indicating that software
> > should delay for 10^x (wher
On Tue, 2016-22-03 at 00:34:55 UTC, Russell Currey wrote:
> In the configure_pe and configure_bridge RTAS calls, the spec states
> that values of 9900-9905 can be returned, indicating that software
> should delay for 10^x (where x is the last digit, i.e. 990x)
> milliseconds and attempt the call ag
On Tue, 2016-03-22 at 11:34 +1100, Russell Currey wrote:
> In the configure_pe and configure_bridge RTAS calls, the spec states
> that values of 9900-9905 can be returned, indicating that software
> should delay for 10^x (where x is the last digit, i.e. 990x)
> milliseconds and attempt the call aga
Hi Rashmica,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.5 next-20160322]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Rashmica-Gupta/powerpc-pagetable-Add-option
Hi Alok
Thanks for wanting to contribute to the Linux kernel!
On 22/03/16 20:43, mistryalok wrote:
Fixed spelling error.
Signed-off-by: Alok Mistry
---
/*
-* No CPU has hugepages but lacks no execute, so we
+* No CPU has huge pages but lacks no e
Acked-by: Ian Munsie
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Until now, when we connect gdb to the QEMU gdb-server, the
single-step mode is not managed.
This patch adds this, only for kvm-pr:
If KVM_GUESTDBG_SINGLESTEP is set, we enable single-step trace bit in the
MSR (MSR_SE) just before the __kvmppc_vcpu_run(), and disable it just after.
In kvmppc_handl
Hi,
Anyone has any comments on this patch-set? Please share your thoughts.
Thanks and best regards,
Codrin
> -Original Message-
> From: Codrin Ciubotariu [mailto:codrin.ciubota...@nxp.com]
> Sent: Monday, 07 March, 2016 5:34 PM
> To: io...@lists.linux-foundation.org
> Cc: scottw...@frees
On 22-03-16, 18:57, Shilpasri G Bhat wrote:
> Create sysfs attributes to export throttle information in
> /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats directory. The
> newly added sysfs files are as follows:
>
> 1)/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/turbo_stat
> 2)/sys/devic
Create sysfs attributes to export throttle information in
/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats directory. The
newly added sysfs files are as follows:
1)/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/turbo_stat
2)/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/sub-turbo_stat
On Tue, 2016-03-22 at 12:48 +1100, Alexey Kardashevskiy wrote:
>
> I suppose GPU from guest1 could trigger DMA from NPU to guest2 memory.
> Which puts a constrain to management tools not to pass NPU without their
> GPU counterparts.
Management tools will not be taught such constraints. The plan
I really wanted to Ack this time, but you know I am nitpicking again :(
On 22-03-16, 16:18, Shilpasri G Bhat wrote:
> static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy)
> {
> - int base, i;
> + int base, i, ret;
>
> base = cpu_first_thread_sibling(policy->cpu);
>
Sorry, I've sent this to the wrong list.
Philippe
Philippe Bergheaud wrote:
From: Vaibhav Jain
Adds a 5ms wait to phb3_msi_set_xive after the interrupt is masked so
that the kernel delays cleanup until an irq if its in-flight is
handled. The value 5ms is the worst case time needed by an irq t
Create sysfs attributes to export throttle information in
/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats directory. The
newly added sysfs files are as follows:
1)/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/turbo_stat
2)/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/sub-turbo_stat
From: Vaibhav Jain
Adds a 5ms wait to phb3_msi_set_xive after the interrupt is masked so
that the kernel delays cleanup until an irq if its in-flight is
handled. The value 5ms is the worst case time needed by an irq to be
presented to the host after its generated.
Signed-off-by: Vaibhav Jain
--
Fixed spelling error.
Signed-off-by: Alok Mistry
---
arch/powerpc/mm/hash64_64k.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c
index b2d659c..fe89a6d 100644
--- a/arch/powerpc/mm/hash64_64k.c
+++ b/arch/powerpc/mm/
Hi,
as Paolo has merged the test into kvm-unit-tests, this patch (and
original bug) can be now tested with it.
git://git.kernel.org/pub/scm/virt/kvm/kvm-unit-tests.git
at least:
be9b007 powerpc: add test to check invalid instruction trap
Run this with KVM-PR and check your dmesg:
qemu
On Mon, 2016-03-21 at 12:58 -0500, Scott Wood wrote:
> On Mon, 2016-03-21 at 11:48 +0100, Nora Björklund wrote:
> >
> > Enable the gpio-expander pca9672 on p2041rdb. The expander
> > has been present on the p2041rdb all along, however not in
> > the device tree.
> >
> > Signed-off-by: Nora Björkl
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