On Tue, Apr 19, 2016 at 8:53 AM, Geert Uytterhoeven
wrote:
> Below is the list of build error/warning regressions/improvements in
> v4.6-rc4[1] compared to v4.5[2].
>
> Summarized:
> - build errors: +11/-7
> - build warnings: +16376/-165
Sorry for the delay, initially I didn't realize why my
Cooling device is registered by ready callback. It's also invoked while
system resuming from sleep (Enabling non-boot cpus). Thus cooling device
may be multiple registered. Matchable unregistration is added to exit
callback to fix this issue.
Signed-off-by: Jia Hongtao
---
Changes for V2:
* Using
From: Pan Xinhui
Implement xchg{u8,u16}{local,relaxed}, and
cmpxchg{u8,u16}{,local,acquire,relaxed}.
It works on all ppc.
Suggested-by: Peter Zijlstra (Intel)
Signed-off-by: Pan Xinhui
---
change from V1:
rework totally.
---
arch/powerpc/include/asm/cmpxchg.h | 83 +++
Acked-by: Ian Munsie
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On 02/17/2016 02:44 PM, Gavin Shan wrote:
This renames traverse_pci_devices() to pci_traverse_device_nodes().
The function traverses all subordinate device nodes of the specified
one. Also, below cleanup applied to the function. No logical changes
introduced.
* Rename "pre" to "fn".
* Av
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This implements and exports pci_remove_device_node_info(). It's
used to remove the pdn (struct pci_dn) for the indicated device
node. The function is going to be used by PowerNV PCI hotplug
driver.
Signed-off-by: Gavin Shan
Kind of strange that there
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This renames update_dn_pci_info() to pci_add_device_node_info()
with corresponding adjustment on the parameter type and exports it.
The function is used to create pdn (struct pci_dn) for the indicated
device node. Another function add_pdn(), almost wrappe
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This renames pcibios_find_pci_bus() to pci_find_bus_by_node() to
avoid conflicts with those PCI subsystem weak function names, which
have prefix "pcibios". No logical changes introduced.
Signed-off-by: Gavin Shan
Reviewed-by: Alexey Kardashevskiy
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This renames pcibios_{add,remove}_pci_devices() to avoid conflicts
with names of the weak functions in PCI subsystem, which have the
prefix "pcibios". No logical changes introduced.
Signed-off-by: Gavin Shan
---
arch/powerpc/include/asm/pci-bridge.h |
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This support releasing PEs dynamically. Firstly, this moves
pnv_pci_ioda2_release_dma_pe() around, which is called to
release DMA resource on releasing IODA2 PE.
imho move would only make sense if we could get rid of the forward
declarations but this
On 02/17/2016 02:44 PM, Gavin Shan wrote:
pnv_pci_ioda_table_free_pages() can be reused to release the IODA1
TCE table when releasing IODA1 PE in subsequent patches.
This renames the following functions to support releasing IODA1 TCE
table: pnv_pci_ioda2_table_free_pages() to pnv_pci_ioda_table_
On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote:
> + pci0: pcie@f1008000 {
> + reg = <0xf1008000 0x1000>;
> + ranges = <0x0200 0x0 0x8000 0x8000 0x0
> 0x5000
> + 0x0100 0x0 0x 0xf000 0x0
> 0x0080>;
>
On 02/17/2016 02:44 PM, Gavin Shan wrote:
Currently, the PEs and their associated resources are assigned
in ppc_md.pcibios_fixup() except those used by SRIOV VFs.
But this new code does not affect IOV and VF's PEs will still be created
somewhere else rather than pnv_pci_setup_bridge()?
The
On Sat, Apr 09, 2016 at 03:44:31PM +0530, Bharata B Rao wrote:
> On Fri, Apr 08, 2016 at 12:27:44AM -0500, Nathan Fontenot wrote:
> > On 04/06/2016 04:44 AM, Bharata B Rao wrote:
> > > memory_hotplug_max() uses hot_add_drconf_memory_max() to get maxmimum
> > > addressable memory by referring to ibm
On 02/17/2016 02:44 PM, Gavin Shan wrote:
PE number for one particular PE can be allocated dynamically or
reserved according to the consumed M64 (64-bits prefetchable)
segments of the PE. The M64 resources, and hence their segments
and PE number are assigned/reserved in ascending order. The PE
nu
On 02/17/2016 02:44 PM, Gavin Shan wrote:
In current implementation, the PEs that are allocated or picked
from the reserved list are identified by PE number. The PE instance
has to be picked according to the PE number eventually. We have
same issue when PE is released.
For pnv_ioda_pick_m64_pe()
On 18/04/16 23:05, Christophe Lombard wrote:
In the POWERVM environement, the PHYP CoherentAccel component manages
environment
the state of the Coherant Accelerator Processor Interface adapter and
Coherent
virtualizes CAPI resources, handles CAPP, PSL, PSL Slice errors - and
interrupts -
On 02/17/2016 02:44 PM, Gavin Shan wrote:
Each PHB maintains an array helping to translate 2-bytes Request
ID (RID) to PE# with the assumption that PE# takes one byte, meaning
that we can't have more than 256 PEs. However, pci_dn->pe_number
already had 4-bytes for the PE#.
This extends the PE# c
On Mon, 2016-04-18 at 14:27 +1000, Stephen Rothwell wrote:
> Hi Jiri,
>
> Today's linux-next merge of the livepatching tree got a conflict in:
>
> arch/powerpc/kernel/process.c
>
> between commit:
>
> 7f92bc569455 ("powerpc: sparse: Include headers for __weak symbols")
>
> from the powerpc
On 02/17/2016 02:44 PM, Gavin Shan wrote:
In current implementation, the DMA32 segments required by one specific
PE isn't calculated with the information hold in the PE independently.
It conflicts with the PCI hotplug design: PE centralized, meaning the
PE's DMA32 segments should be calculated fr
On 04/18/2016 11:52 AM, Alistair Popple wrote:
Hi David,
On Fri, 15 Apr 2016 14:40:20 David Gibson wrote:
On Tue, Apr 12, 2016 at 06:37:50PM +1000, Alexey Kardashevskiy wrote:
IBM POWER8 NVlink systems come with Tesla K40-ish GPUs each of which
also has a couple of fast speed links (NVLink). T
On Mon, 2016-04-18 at 09:38 -0500, m...@linux.vnet.ibm.com wrote:
> Several properties in the DRC device tree format are replaced by
> more compact representations to allow, for example, for the encoding
> of vast amounts of memory, and or reduced duplication of information
> in related data struc
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Good afternoon everyone,
We're trying to get some performance gains in an older embedded design by
adding DMA to our NAND driver. The HW is an MPC8349 talking across a PCI
bus to a NAND controller and we have 512Mb of RAM. We're using the 3.18
kernel and the Freescale "fsl,mpc8349-dma" driver
On 04/18/2016 04:12 PM, Michael Kerrisk (man-pages) wrote:
> Hello Rasmus,
>
> On 04/09/2016 05:50 PM, Rasmus Villemoes wrote:
>> Hi Michael
>>
>> The other day, I was curious how the vdso was implemented on ppc, and I
>> noted that neither ppc32 or ppc64 handle the _COARSE versions of
>> CLOCK_{R
Hello Rasmus,
On 04/09/2016 05:50 PM, Rasmus Villemoes wrote:
> Hi Michael
>
> The other day, I was curious how the vdso was implemented on ppc, and I
> noted that neither ppc32 or ppc64 handle the _COARSE versions of
> CLOCK_{REALTIME,MONOTONIC} in the vdso, so they fall back to an actual
> sysc
Adds two tests. One is a simple test to ensure that the new registers
LMRR and LMSER are properly maintained. The other actually uses the
existing EBB test infrastructure to test that LMRR and LMSER behave as
documented.
Signed-off-by: Jack Miller
---
tools/testing/selftests/powerpc/pmu/ebb/Make
This enables new registers, LMRR and LMSER, that can trigger an EBB in
userspace code when a monitored load (via the new ldmx instruction)
loads memory from a monitored space. This facility is controlled by a
new FSCR bit, LM.
This patch disables the control bit on CPU setup and enables that bit
w
Previous spin:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-April/141846.html
Now with 100% less 32 bit build breakage.
Mikey already called me on this one, not sure how it got back in?
- Jack
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Previously we just saved the FSCR, but only restored it in some
settings, and never copied it thread to thread. This patch always
restores the FSCR and formalizes new threads inheriting its setting so
that later we can manipulate FSCR bits in start_thread.
Signed-off-by: Jack Miller
---
arch/pow
Hi Jack,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.6-rc4 next-20160418]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Jack-Miller/powerpc-Complete-FSCR-context
Adds two tests. One is a simple test to ensure that the new registers
LMRR and LMSER are properly maintained. The other actually uses the
existing EBB test infrastructure to test that LMRR and LMSER behave as
documented.
Signed-off-by: Jack Miller
---
tools/testing/selftests/powerpc/pmu/ebb/Make
This enables new registers, LMRR and LMSER, that can trigger an EBB in
userspace code when a monitored load (via the new ldmx instruction)
loads memory from a monitored space. This facility is controlled by a
new FSCR bit, LM.
This patch disables the control bit on CPU setup and enables that bit
w
Previously we just saved the FSCR, but only restored it in some
settings, and never copied it thread to thread. This patch always
restores the FSCR and formalizes new threads inheriting its setting so
that later we can manipulate FSCR bits in start_thread.
Signed-off-by: Jack Miller
---
arch/pow
Second spin of these patches:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-April/141609.html
Differences from v1:
- As part of the FSCR context switch patch, remove extra FSCR manipulation in
the DSCR case. If anything set FSCR.DSCR it should automatically be set
correctly now. If I
Reviewed-by: Matthew R. Ochs
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Several properties in the DRC device tree format are replaced by
more compact representations to allow, for example, for the encoding
of vast amounts of memory, and or reduced duplication of information
in related data structures.
"ibm,drc-info": This property, when present, replaces the following
On 17/04/16 03:49, Scott Wood wrote:
> On Thu, 2016-04-07 at 08:14 +0200, Valentin Longchamp wrote:
>> On 06/04/16 23:49, Scott Wood wrote:
>>> On Wed, 2016-04-06 at 15:37 +0200, Valentin Longchamp wrote:
Now that the FMAN mac driver has been merged the fman node is relevant.
The kmc
In the POWERVM environement, the PHYP CoherentAccel component manages
the state of the Coherant Accelerator Processor Interface adapter and
virtualizes CAPI resources, handles CAPP, PSL, PSL Slice errors - and
interrupts - and provides a new set of HCALLs for the OS APIs to utilize
AFUs.
During th
On Monday, April 18, 2016 05:59:39 PM Herbert Xu wrote:
> Christian Lamparter wrote:
> >
> > I tried to move ppc4xx-rng into crypto4xx (see attachment - patch #1).
> > The driver works as is. But I can't come up with a way to attach the
> > crypto4xx driver to the ppc4xx-rng OF node cleanly. Basi
From: Yongji Xie
> Sent: 18 April 2016 11:59
> We introduce a new pci_bus_flags, PCI_BUS_FLAGS_MSI_REMAP
> which indicates all devices on the bus are protected by the
> hardware which supports IRQ remapping(intel naming).
>
> This flag will be used to know whether it's safe to expose
> MSI-X table
This patch enables mmapping MSI-X tables if hardware supports
interrupt remapping which can ensure that a given pci device
can only shoot the MSIs assigned for it.
With MSI-X table mmapped, we also need to expose the
read/write interface which will be used to access MSI-X table.
Signed-off-by: Yo
Any IODA host bridge have the capability of IRQ remapping.
So we set PCI_BUS_FLAGS_MSI_REMAP when this kind of host birdge
is detected.
Signed-off-by: Yongji Xie
---
arch/powerpc/platforms/powernv/pci-ioda.c |8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/platforms/po
On ARM HW the capability of IRQ remapping is abstracted on
MSI controller side. MSI_FLAG_IRQ_REMAPPING is used to advertise
this [1].
To have a universal flag to test this capability for different
archs on PCI side, we set PCI_BUS_FLAGS_MSI_REMAP for PCI buses
when MSI_FLAG_IRQ_REMAPPING is set.
The capability of IRQ remapping is abstracted on IOMMU side on
some archs. There is a existing flag IOMMU_CAP_INTR_REMAP for this.
To have a universal flag to test this capability for different
archs on PCI side, we set PCI_BUS_FLAGS_MSI_REMAP for PCI buses
when IOMMU_CAP_INTR_REMAP is set.
Signe
We introduce a new pci_bus_flags, PCI_BUS_FLAGS_MSI_REMAP
which indicates all devices on the bus are protected by the
hardware which supports IRQ remapping(intel naming).
This flag will be used to know whether it's safe to expose
MSI-X tables of PCI BARs to userspace. Because the capability
of IRQ
Current vfio-pci implementation disallows to mmap
sub-page(size < PAGE_SIZE) MMIO BARs because these BARs' mmio
page may be shared with other BARs.
But we should allow to mmap these sub-page MMIO BARs if we can
make sure these BARs' mmio page will not be shared with other BARs.
To acheive that, w
Now we use the IORESOURCE_STARTALIGN to identify bridge resources
in __assign_resources_sorted(). That's quite fragile. We can't
make sure that the PCI devices' resources will not use
IORESOURCE_STARTALIGN any more.
In this patch, we try to use a more robust way to identify
bridge resources.
Sign
When vfio passthrough a PCI device of which MMIO BARs are
smaller than PAGE_SIZE, guest will not handle the mmio
accesses to the BARs which leads to mmio emulations in host.
This is because vfio will not allow to passthrough one BAR's
mmio page which may be shared with other BARs. Otherwise,
there
When using resource_alignment kernel parameter, the current
implement reassigns the alignment by changing resources' size
which can potentially break some drivers. For example, the driver
uses the size to locate some register whose length is related
to the size.
This patch adds a new option "nores
The resource_alignment will releases memory resources allocated
by firmware so that kernel can reassign new resources later on.
But this will cause the problem that no resources can be
allocated by kernel if PCI_PROBE_ONLY was set, e.g. on pSeries
platform because PCI_PROBE_ONLY force kernel to use
Current vfio-pci implementation disallows to mmap
sub-page(size < PAGE_SIZE) MMIO BARs and MSI-X table. This is because
sub-page BARs' mmio page may be shared with other BARs and MSI-X table
should not be accessed directly from the guest for security reasons.
But it will easily cause some performa
From: Anton Blanchard
The REAL_LE feature entry in the ibm_pa_feature struct is missing an MMU
feature value, meaning all the remaining elements initialise the wrong
values.
This means instead of checking for byte 5, bit 0, we check for byte 0,
bit 0, and then we incorrectly set the CPU feature
On 18-04-16, 15:59, Jia Hongtao wrote:
> When THERMAL_OF is undefined the cooling device messages should not be
> shown. -ENOSYS is returned from of_cpufreq_cooling_register() when
> THERMAL_OF is undefined.
>
> Signed-off-by: Jia Hongtao
> ---
> drivers/cpufreq/qoriq-cpufreq.c | 4 ++--
> 1 fil
On 18-04-16, 15:59, Jia Hongtao wrote:
> Cooling device is registered by ready callback. It's also invoked while
> system resuming from sleep (Enabling non-boot cpus). Thus cooling device
> may be multiple registered. Stop_cpu callback is invoked during suspend
> (Disabling non-boot cpus). So match
On 2016年04月17日 03:43, Arnd Bergmann wrote:
> On Wednesday 13 April 2016 19:15:17 Pan Xinhui wrote:
>> Hello Peter,
>>
>> On 2016年04月12日 22:30, Peter Zijlstra wrote:
>>> On Sun, Apr 10, 2016 at 10:17:28PM +0800, Pan Xinhui wrote:
On 2016年04月08日 15:47, Peter Zijlstra wrote:
> On Fri,
On 15-04-16, 11:58, Akshay Adiga wrote:
> static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb,
> - unsigned long action, void *unused)
> +unsigned long action, void *unused)
Unrelated change.. better don't add su
On 15-04-16, 11:58, Akshay Adiga wrote:
> From: Shilpasri G Bhat
>
> commit 1b0289848d5d ("cpufreq: powernv: Add sysfs attributes to show
> throttle stats") used policy->driver_data as a flag for one-time creation
> of throttle sysfs files. Instead of this use 'kernfs_find_and_get()' to
> check i
Christian Lamparter wrote:
>
> I tried to move ppc4xx-rng into crypto4xx (see attachment - patch #1).
> The driver works as is. But I can't come up with a way to attach the
> crypto4xx driver to the ppc4xx-rng OF node cleanly. Basically,
> I'm looking for a way to have one driver (with one contex
On Saturday 20 February 2016 10:32 AM, Anju T wrote:
This short patch series adds the ability to sample the interrupted
machine state for each hardware sample.
To test this patchset,
Eg:
$ perf record -I? # list supported registers
output:
available registers: r0 r1 r2 r3 r4 r5 r6 r7 r8
On 04/07/2016 11:07 AM, Anshuman Khandual wrote:
> This patch series enables HugeTLB page migration on POWER platform.
> This series has some core VM changes (patch 1, 2, 3) and some powerpc
> specific changes (patch 4, 5, 6, 7, 8, 9, 10). Comments, suggestions
> and inputs are welcome.
>
> Anshum
On 04/07/2016 02:46 PM, kbuild test robot wrote:
> Hi Anshuman,
>
> [auto build test ERROR on powerpc/next]
> [also build test ERROR on v4.6-rc2 next-20160407]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improving the system]
>
> url:
> https://github.c
On 04/11/2016 11:34 AM, Anshuman Khandual wrote:
> On 04/07/2016 03:04 PM, kbuild test robot wrote:
>> > All errors (new ones prefixed by >>):
>> >
>> >mm/hugetlb.c: In function 'follow_huge_pud':
>> >>> >> mm/hugetlb.c:4360:3: error: implicit declaration of function
>> >>> >> 'pud_pa
Thanks Andrew!
Reviewed-by: fbar...@linux.vnet.ibm.com
Fred
Le 18/04/2016 07:03, Andrew Donnellan a écrit :
Make a couple more variables static. Found by sparse.
Signed-off-by: Andrew Donnellan
---
drivers/misc/cxl/flash.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
Cooling device is registered by ready callback. It's also invoked while
system resuming from sleep (Enabling non-boot cpus). Thus cooling device
may be multiple registered. Stop_cpu callback is invoked during suspend
(Disabling non-boot cpus). So matchable unregistration is added to fix
this issue.
When THERMAL_OF is undefined the cooling device messages should not be
shown. -ENOSYS is returned from of_cpufreq_cooling_register() when
THERMAL_OF is undefined.
Signed-off-by: Jia Hongtao
---
drivers/cpufreq/qoriq-cpufreq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Add support for the Artesyn MVME7100 Single Board Computer.
The MVME7100 is a 6U form factor VME64 computer with:
- A two e600 cores Freescale MPC8641D CPU
- 2 GB of DDR2 onboard memory
- Four Gigabit Ethernets
- Five 16550 compatible UARTs
- One USB 2.0 port
- Two PCI/PCI
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