Re: [PATCH 3/3] powerpc/eeh: Drop unnecessary label in eeh_pe_change_owner()

On Thu, Apr 21, 2016 at 09:53:07PM +1000, Gavin Shan wrote: > The label "reset" in eeh_pe_change_owner() is used only for once. > No need to keep it and just drop it. No logicial changes introduced. > > Signed-off-by: Gavin Shan Reviewed-by: David Gibson

Re: [PATCH 2/2] cxl: Poll for outstanding IRQs when detaching a context

Acked-by: Ian Munsie ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH 1/2] cxl: Keep IRQ mappings on context teardown

Acked-by: Ian Munsie ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH 2/2] cxl: Poll for outstanding IRQs when detaching a context

On 22/04/16 14:57, Michael Neuling wrote: When detaching contexts, we may still have interrupts in the system which are yet to be delivered to any CPU and be acked in the PSL. This can result in a subsequent unrelated process getting an spurious IRQ or an interrupt for a non-existent context.

Re: [PATCH 1/2] cxl: Keep IRQ mappings on context teardown

On 22/04/16 14:57, Michael Neuling wrote: Keep IRQ mappings on context teardown. This won't leak IRQs as if we allocate the mapping again, the generic code will give the same mapping used last time. Doing this works around a race in the generic code. Masking the interrupt introduces a race

[PATCH 2/2] cxl: Poll for outstanding IRQs when detaching a context

When detaching contexts, we may still have interrupts in the system which are yet to be delivered to any CPU and be acked in the PSL. This can result in a subsequent unrelated process getting an spurious IRQ or an interrupt for a non-existent context. This polls the PSL to ensure that the PSL is

[PATCH 1/2] cxl: Keep IRQ mappings on context teardown

Keep IRQ mappings on context teardown. This won't leak IRQs as if we allocate the mapping again, the generic code will give the same mapping used last time. Doing this works around a race in the generic code. Masking the interrupt introduces a race which can crash the kernel or result in IRQ

Re: [PATCH v8 36/45] powerpc/powernv: Support PCI slot ID

On Wed, 20 Apr 2016 14:14:13 Alexey Kardashevskiy wrote: > > > >> > >> btw how will new OPAL react if old kernel is running, i.e. not passing > >> @state > >> at all? If it is initialized to NULL somewher - fine but what exactly does > >> this initialization and makes sure that OPAL won't see

Re: [PATCH V3] powerpc: Implement {cmp}xchg for u8 and u16

On Fri, Apr 22, 2016 at 09:59:22AM +0800, Pan Xinhui wrote: > On 2016年04月21日 23:52, Boqun Feng wrote: > > On Thu, Apr 21, 2016 at 11:35:07PM +0800, Pan Xinhui wrote: > >> On 2016年04月20日 22:24, Peter Zijlstra wrote: > >>> On Wed, Apr 20, 2016 at 09:24:00PM +0800, Pan Xinhui wrote: > >>> >

Re: [PATCH V3] powerpc: Implement {cmp}xchg for u8 and u16

On 2016年04月21日 23:52, Boqun Feng wrote: > On Thu, Apr 21, 2016 at 11:35:07PM +0800, Pan Xinhui wrote: >> On 2016年04月20日 22:24, Peter Zijlstra wrote: >>> On Wed, Apr 20, 2016 at 09:24:00PM +0800, Pan Xinhui wrote: >>> +#define __XCHG_GEN(cmp, type, sfx, skip, v)

Re: [PATCH 1/2] powerpc/85xx: adapt QorIQ eSDHC to the new clocking model

On Wed, 2016-04-20 at 18:20 +0800, Yangbo Lu wrote: > Provide clocks property instead of clock-frequency for QorIQ eSDHC > dts node to adapt to the new clocking model, so that the driver > could get clock value by the common clk API and the u-boot could > remove the clock fixup. > >

Re: [PATCH V2] powerpc/infiniband: Use cache inhibitted and guarded mapping on powerpc

On Wed, 2016-04-20 at 03:58 -0400, Aneesh Kumar K.V wrote: > The driver was requesting for a writethrough mapping. But with thoses > flags we will end up with a SAO mapping because we now have memory > conherence always enabled. ie, the existing mapping will end up with > a WIMG value 0b1110 which

Re: [PATCH v1 00/23] ata: sata_dwc_460ex: make it working again

On Thursday, April 21, 2016 09:15:21 PM Andy Shevchenko wrote: > The last approach in the commit 8b3444852a2b ("sata_dwc_460ex: move to generic > DMA driver") to switch to generic DMA engine API wasn't tested on bare metal. > Besides that we expecting new board support coming with the same SATA IP

Re: [PATCH v1 23/23] powerpc/4xx: Device tree update for the 460ex DWC SATA

On Thu, Apr 21, 2016 at 1:15 PM, Andy Shevchenko wrote: > Device tree update for the Applied micro processor 460ex on-chip SATA to use > "dmas" property. > Signed-off-by: Andy Shevchenko > --- >

Re: [PATCH 00/14] DT: Fix spelling of standard properties

On Wed, Apr 20, 2016 at 6:58 PM, Rob Herring wrote: > On Wed, Apr 20, 2016 at 10:32 AM, Geert Uytterhoeven > wrote: >> Hi all, >> >> This patch series fixes misspellings of various standard DT properties >> in DT binding documentation, DTS

Re: [PATCH 14/14] regulator: ti-abb: DT spelling s/#{address, size}-cell/#{address, size}-cells/

On Wed, Apr 20, 2016 at 10:32 AM, Geert Uytterhoeven wrote: > Signed-off-by: Geert Uytterhoeven > --- > .../devicetree/bindings/regulator/ti-abb-regulator.txt | 10 > +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff

[PATCH v1 17/23] ata: sata_dwc_460ex: supply physical address of FIFO to DMA

DMA operates with physical addresses which is not exactly the same as ioremap() returns. Introduce variable to keep physical address of the SATA FIFO register and supply it when prepare DMA channel. Signed-off-by: Andy Shevchenko ---

[PATCH v1 19/23] ata: sata_dwc_460ex: use readl/writel_relaxed()

From: Mans Rullgard Rename the register access macros and use standard _relaxed() ops instead of __raw variants with explicit byte swapping. The original driver used the ppc-specific in/out_le32(). When it was adapted to other systems, these were added to the driver under

[PATCH v1 21/23] ata: sata_dwc_460ex: use devm_ioremap

This simplifies error handling and cleanup by using devm to manage IO mappings. Signed-off-by: Mans Rullgard --- drivers/ata/sata_dwc_460ex.c | 30 +++--- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/drivers/ata/sata_dwc_460ex.c

[PATCH v1 22/23] ata: sata_dwc_460ex: make debug messages neat

There is a duplication in the debug messages when accessing SCR registers. Remove duplication to make the messages neat. Signed-off-by: Andy Shevchenko --- drivers/ata/sata_dwc_460ex.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[PATCH v1 23/23] powerpc/4xx: Device tree update for the 460ex DWC SATA

Device tree update for the Applied micro processor 460ex on-chip SATA to use "dmas" property. Signed-off-by: Andy Shevchenko --- arch/powerpc/boot/dts/canyonlands.dts | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git

[PATCH v1 20/23] ata: sata_dwc_460ex: tidy up sata_dwc_clear_dmacr()

From: Mans Rullgard This consolidates the reads from each of the if/else branches to one place making the code a lot nicer to look at. Signed-off-by: Mans Rullgard --- drivers/ata/sata_dwc_460ex.c | 14 ++ 1 file changed, 6 insertions(+), 8

[PATCH v1 10/23] ata: sata_dwc_460ex: add phy support

From: Mans Rullgard This adds support for powering on an optional PHY when activating the device. Signed-off-by: Mans Rullgard --- drivers/ata/Kconfig | 1 + drivers/ata/sata_dwc_460ex.c | 22 ++ 2 files changed, 23 insertions(+)

[PATCH v1 11/23] ata: sata_dwc_460ex: get rid of global data

From: Mans Rullgard This moves all global data into the driver private struct, thus permitting multiple devices of this type to be used. The core_scr_read/write() functions are replaced with equivalent calls to the existing sata_dwc_scr_read/write(). Signed-off-by: Mans

[PATCH v1 18/23] ata: sata_dwc_460ex: switch to new dmaengine_terminate_* API

Convert dmaengine_terminate_all() calls to synchronous and asynchronous versions where appropriate. Signed-off-by: Andy Shevchenko --- drivers/ata/sata_dwc_460ex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/sata_dwc_460ex.c

[PATCH v1 15/23] ata: sata_dwc_460ex: get rid of incorrect cast

From: Mans Rullgard The (void *__iomem) cast is wrong. Change the target type of the "base" pointer to void __iomem instead and drop the cast. Signed-off-by: Mans Rullgard --- drivers/ata/sata_dwc_460ex.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH v1 16/23] ata: sata_dwc_460ex: add __iomem to register base pointer

From: Mans Rullgard The pointer to the mmio register base is missing the __iomem annotation. Fix this. Signed-off-by: Mans Rullgard --- drivers/ata/sata_dwc_460ex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v1 08/23] ata: sata_dwc_460ex: don't call ata_sff_qc_issue() on DMA commands

ata_sff_qc_issue() can't handle DMA commands and thus we have to avoid it for them. Do call ata_bmdma_qc_issue() instead for this case. Suggested-by: Christian Lamparter Signed-off-by: Andy Shevchenko --- drivers/ata/sata_dwc_460ex.c

[PATCH v1 13/23] ata: sata_dwc_460ex: remove empty libata callback

From: Mans Rullgard The sata_dwc_qc_prep() does nothing. Use the default ata_noop_qc_prep instead. Signed-off-by: Mans Rullgard --- drivers/ata/sata_dwc_460ex.c | 22 -- 1 file changed, 22 deletions(-) diff --git

[PATCH v1 14/23] ata: sata_dwc_460ex: get rid of some pointless casts

From: Mans Rullgard Casting a pointer to unsigned long only to immediately cast it back to a pointer makes no sense. Fix this. Signed-off-by: Mans Rullgard --- drivers/ata/sata_dwc_460ex.c | 30 +++--- 1 file changed, 15 insertions(+),

[PATCH v1 09/23] ata: sata_dwc_460ex: use "dmas" DT property to find dma channel

From: Mans Rullgard Currently this driver only works with a DesignWare DMA engine which it registers manually using the second "reg" address range and interrupt number from the DT node. This patch makes the driver instead use the "dmas" property if present, otherwise optionally

[PATCH v1 06/23] ata: sata_dwc_460ex: select only core part of DMA driver

There is no need to have a platform driver compiled since the DMA driver is used as a library. Signed-off-by: Andy Shevchenko --- drivers/ata/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig

[PATCH v1 12/23] ata: sata_dwc_460ex: correct HOSTDEV{P}_FROM_*() macros

Here we refactor HOSTDEV{P}_FROM_*() macros to fit one line and fix the definition of HSDEV_FROM_HSDEVP() where wrong name of the parameter waas used. Signed-off-by: Andy Shevchenko --- drivers/ata/sata_dwc_460ex.c | 17 ++--- 1 file changed, 6

[PATCH v1 00/23] ata: sata_dwc_460ex: make it working again

The last approach in the commit 8b3444852a2b ("sata_dwc_460ex: move to generic DMA driver") to switch to generic DMA engine API wasn't tested on bare metal. Besides that we expecting new board support coming with the same SATA IP but with different DMA. This series is targetting the following

[PATCH v1 05/23] ata: sata_dwc_460ex: DMA is always a flow controller

In the original code the DMA is always a flow controller. Set this accordingly in updated code. Signed-off-by: Andy Shevchenko --- drivers/ata/sata_dwc_460ex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/sata_dwc_460ex.c

[PATCH v1 07/23] ata: sata_dwc_460ex: skip dma setup for non-dma commands

From: Mans Rullgard Calling dmaengine_prep_slave_sg() for non-dma ATA commands is unnecessary at best and could be harmful if the dma driver reacts badly to this. It also causes this driver to print a bogus error message in these cases. This patch changes sata_dwc_qc_issue() to

[PATCH v1 01/23] ata: sata_dwc_460ex: remove incorrect locking

From: Mans Rullgard This lock is already taken in ata_scsi_queuecmd() a few levels up the call stack so attempting to take it here is an error. Moreover, it is pointless in the first place since it only protects a single, atomic assignment. Enabling lock debugging gives the

[PATCH v1 03/23] ata: sata_dwc_460ex: set dma_boundary to 0x1fff

The original code states: Make sure a LLI block is not created that will span 8K max FIS boundary. If the block spans such a FIS boundary, there is a chance that a DMA burst will cross that boundary -- this results in an error in the host controller. Since we have

[PATCH v1 04/23] ata: sata_dwc_460ex: burst size must be in items not bytes

The burst size as defined by DMAengine API is in items of address width. Derive burst size from AHB_DMA_BRST_DFLT (64 bytes) by dividing it to DMA_SLAVE_BUSWIDTH_4_BYTES (4 bytes) that gives us 16 items. Signed-off-by: Andy Shevchenko ---

[PATCH v1 02/23] ata: sata_dwc_460ex: fix crash on offline links without an attached drive

From: Christian Lamparter This patch fixes Machine Check "Data Write PLB Error" which happens when libata-sff's ata_sff_dev_select is trying to write into the device_addr in order to select a drive. However, SATA has no master or slave devices like the old ATA Bus,

Re: [PATCH V3] powerpc: Implement {cmp}xchg for u8 and u16

On Thu, Apr 21, 2016 at 11:35:07PM +0800, Pan Xinhui wrote: > yes, you are right. more load/store will be done in C code. > However such xchg_u8/u16 is just used by qspinlock now. and I did not see any > performance regression. > So just wrote in C, for simple. :) Which is fine; but worthy of a

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

On 13/04/2016 07:14, Michael Ellerman wrote: > On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote: >> On 07/04/2016 23:49, Michael Ellerman wrote: >>> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour >>> wrote: This series is required to handle TM state in

Re: [PATCH V3] powerpc: Implement {cmp}xchg for u8 and u16

On Thu, Apr 21, 2016 at 11:35:07PM +0800, Pan Xinhui wrote: > On 2016年04月20日 22:24, Peter Zijlstra wrote: > > On Wed, Apr 20, 2016 at 09:24:00PM +0800, Pan Xinhui wrote: > > > >> +#define __XCHG_GEN(cmp, type, sfx, skip, v) > >> \ > >> +static __always_inline

Re: [PATCH V3] powerpc: Implement {cmp}xchg for u8 and u16

On 2016年04月20日 22:24, Peter Zijlstra wrote: > On Wed, Apr 20, 2016 at 09:24:00PM +0800, Pan Xinhui wrote: > >> +#define __XCHG_GEN(cmp, type, sfx, skip, v) \ >> +static __always_inline unsigned long >> \ >> +__cmpxchg_u32##sfx(v

Re: [PATCH V2 35/68] powerpc/mm: Abstraction for switch_mmu_context

On 09/04/16 16:13, Aneesh Kumar K.V wrote: > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/mmu_context.h | 25 + > arch/powerpc/kernel/swsusp.c | 2 +- > arch/powerpc/mm/mmu_context_nohash.c | 3 ++- >

[PATCH 9/9] powerpc/powernv: Use deepest stop state when cpu is offlined

If hardware supports stop state, use the deepest stop state when the cpu is offlined. Signed-off-by: Shreyas B. Prabhu --- arch/powerpc/platforms/powernv/idle.c| 15 +-- arch/powerpc/platforms/powernv/powernv.h | 1 +

[PATCH 8/9] cpuidle/powernv: Add support for POWER ISA v3 idle states

POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. Supported idle states and value to be written to PSSCR register to enter any idle

[PATCH 6/9] powerpc/powernv: set power_save func after the idle states are initialized

pnv_init_idle_states discovers supported idle states from the device tree and does the required initialization. Set power_save function pointer only after this initialization is done Signed-off-by: Shreyas B. Prabhy --- arch/powerpc/platforms/powernv/idle.c | 3 +++

[PATCH 7/9] powerpc/powernv: Add platform support for stop instruction

POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. PSSCR has

[PATCH 5/9] powerpc/powernv: Move idle related macros to cpuidle.h

Move idle related macros to a common location asm/cpuidle.h so that they can be used for stop instruction support. Signed-off-by: Shreyas B. Prabhy --- arch/powerpc/include/asm/cpuidle.h | 27 +++ arch/powerpc/kernel/idle_power7.S | 26

[PATCH 3/9] powerpc/powernv: Move idle code usable by multiple hardware to common location

CPU-idle related code like context save/restore functions idle_power7.S can reused for adding stop instruction support. Move this code to a new commonly accessible location. Signed-off-by: Shreyas B. Prabhu --- arch/powerpc/kernel/Makefile| 1 +

Re: [v4,3/3] ppc64/book3s: remove __end_handlers marker

On Thu, 2016-07-04 at 22:00:34 UTC, Hari Bathini wrote: > __end_handlers marker was intended to mark down upto code that gets > called from exception prologs. But that hasn't kept pace with code > changes. Case in point, slb_miss_realmode being called from exception > prolog code but isn't below

[PATCH 4/9] powerpc/powernv: Make power7_powersave_common more generic

power7_powersave_common does common steps needed before entering idle state and eventually changes MSR to MSR_IDLE and does rfid to power7_enter_nap_mode. Make it more generic by passing the rfid address as a function parameter. Also make function name more generic. Signed-off-by: Shreyas B.

[PATCH 2/9] powerpc/kvm: make hypervisor state restore a function

In the current code, when the thread wakes up in reset vector, some of the state restore code and check for whether a thread needs to branch to kvm is duplicated. Reorder the code such that this duplication is avoided. At a higher level this is what the change looks like- Before this patch -

[PATCH 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header

CHECK_HMI_INTERRUPT is used to check for HMI's in reset vector. Move the macro to a common location (exception-64s.h) This patch does not change any functionality. Signed-off-by: Shreyas B. Prabhu --- arch/powerpc/include/asm/exception-64s.h | 18 ++

[PATCH 0/9] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states

POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction.

Re: [PATCH V2 34/68] powerpc/mm/radix: Add radix callback for vmemmap and map_kernel page

On 09/04/16 16:13, Aneesh Kumar K.V wrote: > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/book3s/64/pgtable.h | 12 > arch/powerpc/include/asm/book3s/64/radix.h | 6 ++ > arch/powerpc/mm/pgtable-radix.c | 20

Re: [V11, 2/4] perf/powerpc: add support for sampling intr machine state

On Sat, 2016-20-02 at 05:02:46 UTC, Anju T wrote: > The perf infrastructure uses a bit mask to find out valid > registers to display. Define a register mask for supported > registers defined in asm/perf_regs.h. The bit positions also > correspond to register IDs which is used by perf

Re: [PATCH V11 0/4]perf/powerpc: Add ability to sample intr machine state in powerpc

On Wed, 2016-04-20 at 10:16 -0300, Arnaldo Carvalho de Melo wrote: > Em Wed, Apr 20, 2016 at 02:55:58PM +1000, Michael Ellerman escreveu: > > On Wed, 2016-04-20 at 00:57 -0300, Arnaldo Carvalho de Melo wrote: > > > Even the bits in tools/perf/ are arch specific, so I guess this goes via > > > the

Re: [v2] ppc64/book3s: fix branching to out of line handlers in relocation kernel

On Tue, 2016-29-03 at 18:34:37 UTC, Hari Bathini wrote: > Some of the interrupt vectors on 64-bit POWER server processors are > only 32 bytes long (8 instructions), which is not enough for the full > first-level interrupt handler. For these we need to branch to an out- > of-line (OOL) handler.

Re: [V11,1/4] perf/powerpc: assign an id to each powerpc register

On Sat, 2016-20-02 at 05:02:45 UTC, Anju T wrote: > The enum definition assigns an 'id' to each register in "struct pt_regs" > of arch/powerpc. The order of these values in the enum definition are > based on the corresponding macros in arch/powerpc/include/uapi/asm/ptrace.h. > > Signed-off-by:

Re: [V2,4/4] tool/perf: Add sample_reg_mask to include all perf_regs

On Sat, 2016-20-02 at 05:02:48 UTC, Anju T wrote: > From: Madhavan Srinivasan > > Add sample_reg_mask array with pt_regs registers. > This is needed for printing supported regs ( -I? option). > > Signed-off-by: Madhavan Srinivasan Applied to

Re: [V11,3/4] tools/perf: Map the ID values with register names

On Sat, 2016-20-02 at 05:02:47 UTC, Anju T wrote: > Map ID values with corresponding register names. These names are then > displayed when user issues perf record with the -I option > followed by perf report/script with -D option. > > To test this patchset, > Eg: > $ perf record -I ls # record

Re: [PATCH V2 33/68] powerpc/mm: Abstraction for vmemmap and map_kernel_page

On 09/04/16 16:13, Aneesh Kumar K.V wrote: > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/book3s/64/hash.h| 8 > arch/powerpc/include/asm/book3s/64/pgtable.h | 20 >

Re: [PATCH V2 32/68] powerpc/mm/radix: Add radix callback for early init routines

On 09/04/16 16:13, Aneesh Kumar K.V wrote: > This add routines for early setup w.r.t radix. We use device tree > property ibm,processor-radix-AP-encodings to find supported page sizes. > If we don't find above we consider 64K and 4K as supported page sizes. > > We do map vmemap using 2M page

[PATCH 2/3] powerpc/eeh: Restore config from edev in eeh_pe_reset_and_recover()

The function eeh_pe_reset_and_recover() is used to recover EEH error when the passthrou device are transferred to guest and backwords. The content in the device's config space will be lost on PE reset issued in the middle of the recovery. The function saves/restores it before/after the reset.

[PATCH 3/3] powerpc/eeh: Drop unnecessary label in eeh_pe_change_owner()

The label "reset" in eeh_pe_change_owner() is used only for once. No need to keep it and just drop it. No logicial changes introduced. Signed-off-by: Gavin Shan --- arch/powerpc/kernel/eeh.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git

[PATCH 1/3] powerpc/eeh: Ignore error handlers in eeh_pe_reset_and_recover()

The function eeh_pe_reset_and_recover() is used to recover EEH error when the passthrou device are transferred to guest and backwords, meaning the device's driver is vfio-pci or none. When the driver is vfio-pci that provides error_detected() error handler only, the handler simply stops the guest

[PATCH v5 4/4] printk/nmi: flush NMI messages on the system panic

In NMI context, printk() messages are stored into per-CPU buffers to avoid a possible deadlock. They are normally flushed to the main ring buffer via an IRQ work. But the work is never called when the system calls panic() in the very same NMI handler. This patch tries to flush NMI buffers

[PATCH v5 3/4] printk/nmi: increase the size of NMI buffer and make it configurable

Testing has shown that the backtrace sometimes does not fit into the 4kB temporary buffer that is used in NMI context. The warnings are gone when I double the temporary buffer size. This patch doubles the buffer size and makes it configurable. Note that this problem existed even in the

[PATCH v5 2/4] printk/nmi: warn when some message has been lost in NMI context

We could not resize the temporary buffer in NMI context. Let's warn if a message is lost. This is rather theoretical. printk() should not be used in NMI. The only sensible use is when we want to print backtrace from all CPUs. The current buffer should be enough for this purpose.

[PATCH v5 1/4] printk/nmi: generic solution for safe printk in NMI

printk() takes some locks and could not be used a safe way in NMI context. The chance of a deadlock is real especially when printing stacks from all CPUs. This particular problem has been addressed on x86 by the commit a9edc8809328 ("x86/nmi: Perform a safe NMI stack trace on all CPUs"). The

[PATCH v5 0/4] Cleaning printk stuff in NMI context

This patch set generalizes the already existing solution for printing NMI messages. The main idea comes from Peter Zijlstra. v5 adds changes suggested by Sergey Senozhatsky. It should not longer conflict with his async printk patchset. There are some conflicts with the nmi_backtrace improvements

Re: [PATCH V2 29/68] powerpc/mm: Move hugetlb and THP related pmd accessors to pgtable.h

On 21/04/16 19:59, Michael Ellerman wrote: > On Thu, 2016-04-21 at 19:53 +1000, Balbir Singh wrote: >> On 09/04/16 16:13, Aneesh Kumar K.V wrote: >>> +static inline int pgd_huge(pgd_t pgd) >>> +{ >>> + /* >>> +* leaf pte for huge page >>> +*/ >>> + return !!(pgd_val(pgd) &

Re: [PATCH V2 30/68] powerpc/mm/radix: Add radix callback for pmd accessors

On 09/04/16 16:13, Aneesh Kumar K.V wrote: > This only does 64k linux page support for now. 64k hash linux config > THP need to differentiate it from hugetlb huge page because with THP > we need to track hash pte slot information with respect to each subpage. > This is not needed with hugetlb

Re: [PATCH V11 2/4] perf/powerpc: add support for sampling intr machine state

On 2016/02/20 10:32AM, Anju T wrote: > The perf infrastructure uses a bit mask to find out valid > registers to display. Define a register mask for supported > registers defined in asm/perf_regs.h. The bit positions also > correspond to register IDs which is used by perf infrastructure > to fetch

Re: [PATCH V11 1/4] perf/powerpc: assign an id to each powerpc register

On 2016/02/20 10:32AM, Anju T wrote: > The enum definition assigns an 'id' to each register in "struct pt_regs" > of arch/powerpc. The order of these values in the enum definition are > based on the corresponding macros in arch/powerpc/include/uapi/asm/ptrace.h. > > Signed-off-by: Anju T

[PATCH v2] powerpc/perf: Replace raw event hex values with #def

Minor cleanup patch to replace the raw event hex values in power8-pmu.c with #def. Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/power8-events-list.h | 40 + arch/powerpc/perf/power8-pmu.c | 41

Re: [PATCH V2 29/68] powerpc/mm: Move hugetlb and THP related pmd accessors to pgtable.h

On Thu, 2016-04-21 at 19:53 +1000, Balbir Singh wrote: > On 09/04/16 16:13, Aneesh Kumar K.V wrote: > > +static inline int pgd_huge(pgd_t pgd) > > +{ > > + /* > > +* leaf pte for huge page > > +*/ > > + return !!(pgd_val(pgd) & _PAGE_PTE); > > +} > > +#define pgd_huge pgd_huge > > + >

Re: [PATCH] powerpc/mm: Always use STRICT_MM_TYPECHECKS

On Thursday 21 April 2016 13:37:59 Michael Ellerman wrote: > Testing done by Paul Mackerras has shown that with a modern compiler > there is no negative effect on code generation from enabling > STRICT_MM_TYPECHECKS. > > So remove the option, and always use the strict type definitions. > >

Re: [PATCH V2 29/68] powerpc/mm: Move hugetlb and THP related pmd accessors to pgtable.h

On 09/04/16 16:13, Aneesh Kumar K.V wrote: > Here we create pgtable-64/4k.h and move pmd accessors that is common > between hash and radix there. We can't do much sharing with 4k linux > page size [1]. So for now it is empty. In later patches we will add > functions that does conditional

ATA errors with Fedora 23 Kexec

Hi All At Rackspace, we are working with our Barreleye servers that runs a Fedora 23 Live Hypervisor. We usually do NOT hit any issues with the mSATA device during bootup / Kexec from Petitboot. But with Fedora 23 OS, we noticed an issue we are hitting, while we kexec from Fedora 23 Live

Re: [PATCH] kvm-pr: manage illegal instructions

On 15.03.2016 21:18, Laurent Vivier wrote: > While writing some instruction tests for kvm-unit-tests for powerpc, > I've found that illegal instructions are not managed correctly with kvm-pr, > while it is fine with kvm-hv. > > When an illegal instruction (like ".long 0") is processed by kvm-pr,

Re: [PATCH]powerpc/perf: Replace raw event hex values with #def

On Thursday 21 April 2016 12:08 PM, Michael Ellerman wrote: > On Thu, 2016-04-21 at 09:30 +0530, Madhavan Srinivasan wrote: >> @@ -488,17 +489,17 @@ static int power8_compute_mmcr(u64 event[], int n_ev, >> >> /* Table of alternatives, sorted by column 0 */ >> static const unsigned int

Re: [PATCH]powerpc/perf: Replace raw event hex values with #def

On Thu, 2016-04-21 at 09:30 +0530, Madhavan Srinivasan wrote: > @@ -488,17 +489,17 @@ static int power8_compute_mmcr(u64 event[], int n_ev, > > /* Table of alternatives, sorted by column 0 */ > static const unsigned int event_alternatives[][MAX_ALT] = { > - { 0x10134, 0x301e2 },

Re: [PATCH] powerpc/mm: Always use STRICT_MM_TYPECHECKS

On Thu, 2016-04-21 at 14:15 +1000, Balbir Singh wrote: > > On 21/04/16 13:37, Michael Ellerman wrote: > > Testing done by Paul Mackerras has shown that with a modern compiler > > there is no negative effect on code generation from enabling > > STRICT_MM_TYPECHECKS. > > > > So remove the option,