On Tue, Apr 26, 2016 at 04:42:09PM +1000, Cyril Bur wrote:
Hi Chris,
Patch looks good. Looks like you've put 8 spaces (instead of a tab) on the
PPC_CP_ABORT line.
Argh. I'm not sure how that happened, thanks.
Apart from that,
Reviewed-by: Cyril Bur
Cheers,
-c
__
On 2016/4/26 13:41, Alexey Kardashevskiy wrote:
On 04/18/2016 08:56 PM, Yongji Xie wrote:
When vfio passthrough a PCI device of which MMIO BARs are
smaller than PAGE_SIZE, guest will not handle the mmio
accesses to the BARs which leads to mmio emulations in host.
This is because vfio will not
On 26/04/16 14:58, Daniel Axtens wrote:
> Sparse doesn't seem to be passing -maltivec around properly, leading
> to lots of errors:
>
> .../include/altivec.h:34:2: error: Use the "-maltivec" flag to enable PowerPC
> AltiVec support
> arch/powerpc/lib/xor_vmx.c:27:16: error: Expected ; at end of
On Tue, 26 Apr 2016 10:28:50 +1000
Chris Smart wrote:
> The copy paste facility introduced in POWER9 provides an optimised
> mechanism for a userspace application to copy a cacheline. This is
> provided by a pair of instructions, copy and paste, while a third,
> cp_abort (copy paste abort), provi
> -Original Message-
> From: Yangbo Lu
> Sent: Tuesday, April 26, 2016 2:19 PM
> To: 'Scott Wood'; linux-...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; devicet...@vger.kernel.org
> Cc: ulf.hans...@linaro.org; Rob Herring; Scott Wood
> Subject: RE: [PATCH 1/2] powerpc/85xx: adapt
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> With radix there is no mmu cache. Hence we don't need to do much
> in update_mmu_cache.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/mm/mem.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/powerpc/mm/mem.c b/arch/powerp
On 23/04/16 13:29, Aneesh Kumar K.V wrote:
> Michael Neuling writes:
>
>> Aneesh,
>>
>> I'm not sure why we need this patch.
>>
>> It seems to be moving the initialisation of some global variables into
>> init functions from the definitions. And renames some things.
>
>
> because the value t
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Friday, April 22, 2016 7:08 AM
> To: Yangbo Lu; linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> devicet...@vger.kernel.org
> Cc: ulf.hans...@linaro.org; Rob Herring; Scott Wood
> Subject: Re: [PATCH 1/2]
On Fri, Apr 22, 2016 at 11:28:02PM +1000, Gavin Shan wrote:
> The function eeh_pe_reset_and_recover() is used to recover EEH
> error when the passthrough device are transferred to guest and
> backwards, meaning the device's driver is vfio-pci or none.
> When the driver is vfio-pci that provides err
On 04/18/2016 08:56 PM, Yongji Xie wrote:
When vfio passthrough a PCI device of which MMIO BARs are
smaller than PAGE_SIZE, guest will not handle the mmio
accesses to the BARs which leads to mmio emulations in host.
This is because vfio will not allow to passthrough one BAR's
mmio page which may
On Tue, 2016-04-26 at 15:02 +1000, Andrew Donnellan wrote:
> Found by smatch.
>
> Signed-off-by: Andrew Donnellan
Acked-by: Russell Currey
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Found by smatch.
Signed-off-by: Andrew Donnellan
---
arch/powerpc/kernel/eeh_pe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index eea48d8..f0520da 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/ke
Sparse doesn't seem to be passing -maltivec around properly, leading
to lots of errors:
.../include/altivec.h:34:2: error: Use the "-maltivec" flag to enable PowerPC
AltiVec support
arch/powerpc/lib/xor_vmx.c:27:16: error: Expected ; at end of declaration
arch/powerpc/lib/xor_vmx.c:27:16: error:
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/book3s/64/hash.h| 14 +++---
> arch/powerpc/include/asm/book3s/64/pgtable.h | 15 ---
> arch/powerpc/include/asm/book3s/64/radix.h | 21 +
>
Hi Scott and Leo,
> -Original Message-
> From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
> ow...@vger.kernel.org] On Behalf Of Scott Wood
> Sent: Saturday, April 23, 2016 7:23 AM
> To: Yangbo Lu; linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> linux-arm-ker...@lists.i
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> ---
> arch/powerpc/mm/pgtable.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
> index 115a0a19d5a2..0a9658fbf8b9 100644
> --- a/arch/powerpc/mm/pgtable.c
> +++ b/arch/powerpc/mm/pgta
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/book3s/64/pgalloc.h | 34
>
> arch/powerpc/include/asm/book3s/64/pgtable.h | 10 ++--
> arch/powerpc/mm/hash_utils_64.c | 7 ++
> arc
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> pgtable_page_dtor for nohash is now moved to pte_fragment_free_mm()
>
> Signed-off-by: Aneesh Kumar K.V
This needs a better changelog
> ---
> arch/powerpc/include/asm/book3s/64/pgalloc.h | 147
> +++
> arch/powerpc/include
Hi Mark,
> -Original Message-
> From: Mark Rutland [mailto:mark.rutl...@arm.com]
> Sent: Friday, April 22, 2016 9:12 PM
> To: Yangbo Lu
> Cc: linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.
On 04/21/2016 01:20 PM, Alexey Kardashevskiy wrote:
On 04/21/2016 10:21 AM, Gavin Shan wrote:
On Fri, Apr 08, 2016 at 04:36:44PM +1000, Alexey Kardashevskiy wrote:
When SRIOV is disabled, the existing code presumes there is no
virtual function (VF) in use and destroys all associated PEs.
Howeve
On 23/04/16 18:30, Benjamin Herrenschmidt wrote:
> On Thu, 2016-04-21 at 14:12 +1000, Balbir Singh wrote:
>>> + } while (cpu_to_be64(old_pte) != __cmpxchg_u64((unsigned long *)ptep,
>>> +cpu_to_be64(old_pte),
>>> +
The copy paste facility introduced in POWER9 provides an optimised
mechanism for a userspace application to copy a cacheline. This is
provided by a pair of instructions, copy and paste, while a third,
cp_abort (copy paste abort), provides a clean up of the state in case of
a failure.
The copy ins
On Tuesday, April 19, 2016 02:41:51 PM Viresh Kumar wrote:
> On 19-04-16, 17:00, Jia Hongtao wrote:
> > .exit callback (qoriq_cpufreq_cpu_exit()) is also used during suspend.
> > So __exit macro should be removed or the function will be discarded.
> >
> > Signed-off-by: Jia Hongtao
> > ---
> > d
On Monday, April 18, 2016 04:03:45 PM Viresh Kumar wrote:
> On 18-04-16, 15:59, Jia Hongtao wrote:
> > When THERMAL_OF is undefined the cooling device messages should not be
> > shown. -ENOSYS is returned from of_cpufreq_cooling_register() when
> > THERMAL_OF is undefined.
> >
> > Signed-off-by: J
In the ppc64 big endian ABI, function symbols point to function
descriptors. The symbols which point to the function entry points
have a dot in front of the function name. Consequently, when the
ftrace filter mechanism searches for the symbol corresponding to
an entry point address, it gets the dot
The CCSR_SSI_SOR is a register that clears the TX and/or the RX fifo
on the i.MX SSI port. The fsl_ssi_trigger writes this register in
order to clear the fifo at trigger time.
However, since the CCSR_SSI_SOR register is not in the volatile list,
the caching mechanism prevented the register write
On Mon, Apr 25, 2016 at 10:50:24AM -0700, Caleb Crome wrote:
> Due to caching, SOR wasn't written when it should have been. This
> patch simply adds SOR to the volatile list.
Could you expand on when it wasn't written and why it needed to be
please?
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___
On Mon, Apr 25, 2016 at 11:06 AM, Mark Brown wrote:
> On Mon, Apr 25, 2016 at 10:50:24AM -0700, Caleb Crome wrote:
>
>> Due to caching, SOR wasn't written when it should have been. This
>> patch simply adds SOR to the volatile list.
>
> Could you expand on when it wasn't written and why it needed
Due to caching, SOR wasn't written when it should have been. This
patch simply adds SOR to the volatile list.
Signed-off-by: Caleb Crome
---
sound/soc/fsl/fsl_ssi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 216e3cb..2f3bf9c 10064
Hi Vinod,
On Mon, Apr 25, 2016 at 5:26 PM, Vinod Koul wrote:
> On Wed, Apr 20, 2016 at 05:32:11PM +0200, Geert Uytterhoeven wrote:
>> Signed-off-by: Geert Uytterhoeven
>> ---
>> Documentation/devicetree/bindings/sound/davinci-mcbsp.txt | 2 +-
>
> This change does not apply for me, can you pleas
gcc-6 correctly warns about a out of bounds access
arch/powerpc/kernel/ptrace.c:407:24: warning: index 32 denotes an offset
greater than size of 'u64[32][1] {aka long long unsigned int[32][1]}'
[-Warray-bounds]
offsetof(struct thread_fp_state, fpr[32][0]));
^
che
On Mon, Apr 25, 2016 at 06:10:51PM +0800, Pan Xinhui wrote:
> > So I'm not actually _that_ familiar with the PPC LL/SC implementation;
> > but there are things a CPU can do to optimize these loops.
> >
> > For example, a CPU might choose to not release the exclusive hold of the
> > line for a numb
On Wed, Apr 20, 2016 at 05:32:11PM +0200, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven
> ---
> Documentation/devicetree/bindings/sound/davinci-mcbsp.txt | 2 +-
This change does not apply for me, can you please split it up and send the
sound ones thru sound tree
--
~Vinod
> d
LivePatch framework deserves some documentation, definitely.
This is an attempt to provide some basic info. I hope that
it will be useful for both LivePatch producers and also
potential developers of the framework itself.
Signed-off-by: Petr Mladek
---
This version incorporates feedback from all
On Wed, Apr 20, 2016 at 05:32:17PM +0200, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven
Applied, thanks.
Rob
> ---
> Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bind
On Wed, Apr 20, 2016 at 05:32:16PM +0200, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven
Applied, thanks.
Rob
> ---
> Documentation/devicetree/bindings/pci/hisilicon-pcie.txt | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/dev
On Wed, Apr 20, 2016 at 05:32:15PM +0200, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven
Applied, thanks.
Rob
> ---
> Documentation/devicetree/bindings/sram/sram.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/sram/
On Monday 25 April 2016 01:45 PM, Alexander Graf wrote:
>
>> Am 25.04.2016 um 10:08 schrieb Madhavan Srinivasan
>> :
>>
>>
>>
>>> On Friday 08 April 2016 09:24 PM, Thomas Huth wrote:
>>> The SIAR register is available twice, one time as SPR 780 (unprivileged,
>>> but read-only), and one time as
On 2016年04月22日 00:13, Peter Zijlstra wrote:
> On Thu, Apr 21, 2016 at 11:35:07PM +0800, Pan Xinhui wrote:
>> yes, you are right. more load/store will be done in C code.
>> However such xchg_u8/u16 is just used by qspinlock now. and I did not see
>> any performance regression.
>> So just wrote in
Hi Alex,
Any comment?
Thanks,
Yongji
On 2016/4/18 18:53, Yongji Xie wrote:
Current vfio-pci implementation disallows to mmap
sub-page(size < PAGE_SIZE) MMIO BARs and MSI-X table. This is because
sub-page BARs' mmio page may be shared with other BARs and MSI-X table
should not be accessed direc
On 04/25/2016 11:16 AM, Thomas Huth wrote:
On 25.04.2016 10:15, Alexander Graf wrote:
Am 25.04.2016 um 10:08 schrieb Madhavan Srinivasan :
On Friday 08 April 2016 09:24 PM, Thomas Huth wrote:
The SIAR register is available twice, one time as SPR 780 (unprivileged,
but read-only), and one t
On 25.04.2016 10:15, Alexander Graf wrote:
>
>
>> Am 25.04.2016 um 10:08 schrieb Madhavan Srinivasan
>> :
>>
>>
>>
>>> On Friday 08 April 2016 09:24 PM, Thomas Huth wrote:
>>> The SIAR register is available twice, one time as SPR 780 (unprivileged,
>>> but read-only), and one time as SPR 796 (pr
On Sun, Apr 24, 2016 at 11:00:06PM -0700, Khem Raj wrote:
> gcc-6 correctly warns about a out of bounds access
>
> arch/powerpc/kernel/ptrace.c:407:24: warning: index 32 denotes an offset
> greater than size of 'u64[32][1] {aka long long unsigned int[32][1]}'
> [-Warray-bounds]
> offseto
> Am 25.04.2016 um 10:08 schrieb Madhavan Srinivasan :
>
>
>
>> On Friday 08 April 2016 09:24 PM, Thomas Huth wrote:
>> The SIAR register is available twice, one time as SPR 780 (unprivileged,
>> but read-only), and one time as SPR 796 (privileged, but read and write).
>> The Linux kernel code
On Friday 08 April 2016 09:24 PM, Thomas Huth wrote:
> The SIAR register is available twice, one time as SPR 780 (unprivileged,
> but read-only), and one time as SPR 796 (privileged, but read and write).
> The Linux kernel code currently uses SPR 780 - and while this is OK for
> reading, writing
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