On Tue, 2016-05-31 at 17:16 +1000, Oliver O'Halloran wrote:
> Power ISAv3 extends the width of the decrementer register from 32 bits.
> The enlarged register width is implementation dependent, but reads from
> these registers are automatically sign extended to produce a 64 bit
> output when operati
Hi Michael,
> I'd really rather __find_linux_pte_or_hugepte() was an internal
> detail, rather than the standard API.
>
> We do already have quite a few uses, but adding more just further
> spreads the details about how the implementation works.
>
> So I'm going to drop this in favor of Aneesh's
On Tue, 2016-05-31 at 17:16 +1000, Oliver O'Halloran wrote:
> POWER ISA v3 adds large decrementer (LD) mode of operation which
> increases
> the size of the decrementer register from 32 bits to an implementation
> defined with of up to 64 bits.
>
> This patch adds support for the LD on processors
On Sun, 2016-29-05 at 12:03:52 UTC, Anton Blanchard wrote:
> From: Anton Blanchard
>
> In many cases we disable interrupts right before calling
> find_linux_pte_or_hugepte().
>
> find_linux_pte_or_hugepte() first checks interrupts are disabled
> before calling __find_linux_pte_or_hugepte():
>
>
On Tue, 2016-05-31 at 19:20 +0530, Shreyas B Prabhu wrote:
> On 05/30/2016 07:56 PM, Daniel Lezcano wrote:
> > On 05/24/2016 03:15 PM, Shreyas B. Prabhu wrote:
> > > +psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val),
> > > +GFP_KERNEL);
> > > +rc = of_prope
On Tue, 2016-05-31 at 20:09 +1000, Anton Blanchard wrote:
> > Huh? Make it an unsigned long please, which is the type of the msr
> > field in struct pt_regs to work on both 32 and 64 bit processors.
>
> Thanks, not sure what I was thinking there. Will respin.
I'll fix it up here.
cheers
___
On 20/05/16 16:41, Gavin Shan wrote:
The macro defined in arch/powerpc/platforms/powernv/pci.c isn't
used by anyone. Just remove it.
Signed-off-by: Gavin Shan
Looks like the only user of it disappeared in late 2014...
Reviewed-by: Andrew Donnellan
--
Andrew Donnellan OzLabs, A
On Tue, 31 May 2016, Benjamin Herrenschmidt wrote:
> On Mon, 2016-05-30 at 09:39 -0700, Hugh Dickins wrote:
> > I don't mean to be churlish, and subtract from your triumph in tracking
> > this down (assuming you have), but that commit log... okay, it's intended
> > for powerpc mmu experts, not me,
On Tue, 31 May 2016 16:26:30 +0530
Anju T wrote:
> Instructions which can be emulated are suppliants for
> optimization. Before optimization ensure that the address range
> between the detour buffer allocated and the instruction being probed
> is within +/- 32MB.
>
> Signed-off-by: Anju T
> ---
On 05/31/2016 04:21 PM, Russell King - ARM Linux wrote:
> On Tue, May 31, 2016 at 04:19:31PM +0200, Krzysztof Kozlowski wrote:
>> Remove __init annotation from all of console->setup implementations
>> because:
>> 1. The pointer to it is stored in a struct console which is not
>>marked with __in
Remove __init annotation from all of console->setup implementations
because:
1. The pointer to it is stored in a struct console which is not
marked with __initdata.
2. It is referenced by register_console() from kernel which is not
marked with __init.
Signed-off-by: Krzysztof Kozlowski
---
Definition of function should start from new line.
Signed-off-by: Krzysztof Kozlowski
---
drivers/tty/serial/pnx8xxx_uart.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/pnx8xxx_uart.c
b/drivers/tty/serial/pnx8xxx_uart.c
index 84c4efdde8dc..9eaedd6a049
Hi Daniel,
On 05/30/2016 07:56 PM, Daniel Lezcano wrote:
> On 05/24/2016 03:15 PM, Shreyas B. Prabhu wrote:
>> POWER ISA v3 defines a new idle processor core mechanism. In summary,
>> a) new instruction named stop is added.
>> b) new per thread SPR named PSSCR is added which controls the behav
This switch few of the page table accessor to use the __raw variant
and does the cpu to big endian conversion of constants. This helps in
generating better code.
For ex: a pgd_none(pgd) check with and without fix is listed below
Without fix:
2240:20 00 61 eb ld r2
Signed-off-by: Anju T
---
Documentation/features/debug/optprobes/arch-support.txt | 2 +-
arch/powerpc/Kconfig| 1 +
arch/powerpc/kernel/Makefile| 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/featu
Instructions which can be emulated are suppliants for
optimization. Before optimization ensure that the address range
between the detour buffer allocated and the instruction being probed
is within +/- 32MB.
Signed-off-by: Anju T
---
arch/powerpc/kernel/optprobes.c | 351 +
Detour buffer contains instructions to create an in memory pt_regs.
After the execution of prehandler a call is made for instruction emulation.
The NIP is decided after the probed instruction is executed. Hence a branch
instruction is created to the NIP returned by emulate_step().
Instruction slot
Here are the RFC V3 patchset of the kprobes jump optimization
(a.k.a OPTPROBES)for powerpc. Kprobe being an inevitable tool
for kernel developers,enhancing the performance of kprobe has
got much importance.
Currently kprobes inserts a trap instruction to probe a running kernel.
Jump optimization a
On Tue, 2016-05-31 at 12:19 +0200, Thomas Huth wrote:
> On 31.05.2016 12:04, Michael Ellerman wrote:
> > On Tue, 2016-05-31 at 07:51 +0200, Thomas Huth wrote:
> > > If we do not provide the PVR for POWER8NVL, a guest on this
> > > system currently ends up in PowerISA 2.06 compatibility mode on
> >
On 31.05.2016 12:04, Michael Ellerman wrote:
> On Tue, 2016-05-31 at 07:51 +0200, Thomas Huth wrote:
>
>> If we do not provide the PVR for POWER8NVL, a guest on this
>> system currently ends up in PowerISA 2.06 compatibility mode on
>> KVM, since QEMU does not provide a generic PowerISA 2.07 mode
On Thu, 2016-12-05 at 11:29:11 UTC, Thomas Huth wrote:
> We are already using the privileged versions of MMCR0, MMCR1
> and MMCRA in the kernel, so for MMCR2, we should better use
> the privileged versions, too, to be consistent.
>
> Suggested-by: Paul Mackerras
> Signed-off-by: Thomas Huth
> Ac
On Thu, 2016-12-05 at 11:26:44 UTC, Thomas Huth wrote:
> The SIAR and SDAR registers are available twice, one time as SPRs
> 780 / 781 (unprivileged, but read-only), and one time as the SPRs
> 796 / 797 (privileged, but read and write). The Linux kernel code
> currently uses the unprivileged SPRs
On Thu, 2016-07-04 at 06:28:27 UTC, Russell Currey wrote:
> The RTAS calls "ibm,configure-pe" and "ibm,configure-bridge" perform the
> same actions, however the former can skip configuration if unnecessary.
> The existing code treats them as different tokens even though only one
> will ever be call
On Thu, 2016-07-04 at 06:28:26 UTC, Russell Currey wrote:
> In the "ibm,configure-pe" and "ibm,configure-bridge" RTAS calls, the
> spec states that values of 9900-9905 can be returned, indicating that
> software should delay for 10^x (where x is the last digit, i.e. 990x)
> milliseconds and attempt
On Sat, May 21, 2016 at 02:03:38PM +0200, Andrea Gelmini wrote:
> Signed-off-by: Andrea Gelmini
Applied.
--
Email: Herbert Xu
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
___
Linuxppc-dev mail
> Huh? Make it an unsigned long please, which is the type of the msr
> field in struct pt_regs to work on both 32 and 64 bit processors.
Thanks, not sure what I was thinking there. Will respin.
Anton
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On Fri, May 27, 2016 at 11:32:36AM +0200, Christophe Leroy wrote:
>
> + sg_count = sg_to_link_tbl_offset(src, sg_count, offset, len,
> + &edesc->link_tbl[tbl_off])
> + if (sg_count == 1) {
> + /* Only one segment now, so no link tbl needed*/
Hi,
> current_stack_pointeur() is a single instruction function. it
> It is not worth breaking the execution flow with a bl/blr for a
> single instruction
Check out bfe9a2cfe91a ("powerpc: Reimplement __get_SP() as a function
not a define") to see why we made it a function.
Anton
___
On Tue, 2016-05-31 at 07:51 +0200, Thomas Huth wrote:
> If we do not provide the PVR for POWER8NVL, a guest on this
> system currently ends up in PowerISA 2.06 compatibility mode on
> KVM, since QEMU does not provide a generic PowerISA 2.07 mode yet.
> So some new instructions from POWER8 (like "m
Power ISAv3 extends the width of the decrementer register from 32 bits.
The enlarged register width is implementation dependent, but reads from
these registers are automatically sign extended to produce a 64 bit
output when operating in large mode. The HDEC always operates in large
mode while the D
POWER ISA v3 adds large decrementer (LD) mode of operation which increases
the size of the decrementer register from 32 bits to an implementation
defined with of up to 64 bits.
This patch adds support for the LD on processors with the CPU_FTR_ARCH_300
cpu feature flag set. For CPUs with this featu
On Tue, May 31, 2016 at 4:25 PM, Michael Neuling wrote:
> On Tue, 2016-05-10 at 14:57 +1000, Oliver O'Halloran wrote:
>> static int decrementer_set_next_event(unsigned long evt,
>> struct clock_event_device *dev);
>> @@ -503,7 +504,7 @@ static void __timer_inte
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