On Thu, 2016-06-02 at 15:10 +0530, Aneesh Kumar K.V wrote:
> We need to se HR bit LPCR for radix partitions.
Again (:-) please a better changeset description. In fact this
one is actually incorrect, this is not a partition.
Something like "The processor requires the MMU mode (radix vs. ha
On Thu, 2016-06-02 at 15:16 +0530, Aneesh Kumar K.V wrote:
>
>
> +/*
> + * flush the page walk cache for the address
> + */
> +void flush_tlb_pgtable(struct mmu_gather *tlb, unsigned long address)
> +{
> + struct mm_struct *mm = tlb->mm;
> + /*
> + * flush the page table walk c
On 01/06/16 15:28, Michael Neuling wrote:
> On Tue, 2016-05-31 at 17:16 +1000, Oliver O'Halloran wrote:
>> POWER ISA v3 adds large decrementer (LD) mode of operation which
>> increases
>> the size of the decrementer register from 32 bits to an implementation
>> defined with of up to 64 bits.
>>
>
Hi, Alex
On 2016/6/2 21:11, Alex Williamson wrote:
AFAICT, you posted this *3* days ago, has something changed here or is
this just expedited nagging for review? This also depends on a
non-upstream series and crosses multiple functional areas, all of which
make it difficult for maintainers to
Benjamin Herrenschmidt writes:
> On Thu, 2016-06-02 at 15:16 +0530, Aneesh Kumar K.V wrote:
>>
>>
>> +/*
>> + * flush the page walk cache for the address
>> + */
>> +void flush_tlb_pgtable(struct mmu_gather *tlb, unsigned long address)
>> +{
>> + struct mm_struct *mm = tlb->mm;
>> +
There is an ordering issue with spin_unlock_wait() on powerpc, because
the spin_lock primitive is an ACQUIRE and an ACQUIRE is only ordering
the load part of the operation with memory operations following it.
Therefore the following event sequence can happen:
CPU 1 CPU 2
On 2016年06月03日 09:32, Benjamin Herrenschmidt wrote:
On Fri, 2016-06-03 at 11:32 +1000, Benjamin Herrenschmidt wrote:
On Thu, 2016-06-02 at 17:22 +0800, Pan Xinhui wrote:
Base code to enable qspinlock on powerpc. this patch add some
#ifdef
here and there. Although there is no paravirt related
On Fri, 2016-06-03 at 12:10 +0800, xinhui wrote:
> On 2016年06月03日 09:32, Benjamin Herrenschmidt wrote:
> > On Fri, 2016-06-03 at 11:32 +1000, Benjamin Herrenschmidt wrote:
> >> On Thu, 2016-06-02 at 17:22 +0800, Pan Xinhui wrote:
> >>>
> >>> Base code to enable qspinlock on powerpc. this patch add
On 02/06/16 19:44, Aneesh Kumar K.V wrote:
> Semantic Issue: comparison of constant 18446744073709551615 with
> expression of type 'unsigned int' is always false.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/mm/tlb-radix.c | 8
> 1 file changed, 4 insertions(+), 4 deletion
The policy already has this pointer set, use it instead.
Signed-off-by: Viresh Kumar
---
Documentation/cpu-freq/cpu-drivers.txt | 1 -
drivers/cpufreq/amd_freq_sensitivity.c | 3 +--
drivers/cpufreq/cpufreq.c | 4 ++--
drivers/cpufreq/cpufreq_ondemand.c | 11 +--
driv
This routine can't fail unless the frequency table is invalid and
doesn't contain any valid entries.
Make it return the index and WARN() in case it is used for an invalid
table.
Signed-off-by: Viresh Kumar
---
Documentation/cpu-freq/cpu-drivers.txt | 7 +++
drivers/cpufreq/amd_freq_sensiti
On 31/05/16 20:59, Aneesh Kumar K.V wrote:
> This switch few of the page table accessor to use the __raw variant
> and does the cpu to big endian conversion of constants. This helps in
> generating better code.
>
> For ex: a pgd_none(pgd) check with and without fix is listed below
>
> Without f
On 31/05/16 16:26, Aneesh Kumar K.V wrote:
> LPCR cannot be updated when running in guest mode.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/mm/pgtable-radix.c | 23 ++-
> 1 file changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/arch/powerpc/mm/pgtabl
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