On 07/05/2016 10:48 AM, Michael Ellerman wrote:
On 06/24/2016 10:56 AM, Michael Ellerman wrote:
On Wed, 2016-22-06 at 19:25:26 UTC, Hari Bathini wrote:
...
While the code is moved to kernel/params.c file, there is no change in logic
for crashkernel parameter parsing as the moved code is invo
Hi Dave,
On Tue, Jul 05, 2016 at 09:25:56AM +0800, Dave Young wrote:
> On 07/04/16 at 03:58pm, AKASHI Takahiro wrote:
> > Hi,
> >
> > On Fri, Jul 01, 2016 at 12:46:31PM -0300, Thiago Jung Bauermann wrote:
> > > Am Freitag, 01 Juli 2016, 14:11:12 schrieb AKASHI Takahiro:
> > > > I'm not sure wheth
On Mon, Jul 04, 2016 at 07:50:19PM -0300, Thiago Jung Bauermann wrote:
> Hello,
>
> Am Montag, 04 Juli 2016, 15:58:15 schrieb AKASHI Takahiro:
> > On Fri, Jul 01, 2016 at 12:46:31PM -0300, Thiago Jung Bauermann wrote:
> > > I agree that it would be better if we could have a system call where a
> >
On Thu, 2016-30-06 at 14:34:37 UTC, Oliver O'Halloran wrote:
> This patch adds an OPAL console backend to the powerpc boot wrapper so
> that decompression failures inside the wrapper can be reported to the
> user. This is important since it typically indicates data corruption in
> the firmware and
Hi Michael,
On Tue, Jul 05, 2016 at 03:40:40PM +1000, Michael Ellerman wrote:
> On Wed, 2016-06-04 at 07:00:12 UTC, Simon Guo wrote:
> > These 2 fields track whether user process has used Altivec/VSX
> > registers or not. They are used by kernel to setup signal frame
> > on user stack correctly reg
The PSL Slice Error Register (PSL_SERR_An) reports implementation
dependent AFU errors, in the form of a bitmap. The PSL_SERR_An
register content is printed in the form of hex dump debug message.
This patch decodes the PSL_ERR_An register contents, and prints a
specific error message for each poss
Hi Xinhui,
2016-06-28 22:43 GMT+08:00 Pan Xinhui :
> This is to fix some lock holder preemption issues. Some other locks
> implementation do a spin loop before acquiring the lock itself. Currently
> kernel has an interface of bool vcpu_is_preempted(int cpu). It take the cpu
> as parameter and retur
On 07/05/2016 11:51 AM, Jason Cooper wrote:
> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Tuesday, July 05, 2016 11:51 AM
> To: Qiang Zhao
> Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@
On 07/05/2016 11:19 AM, Jason Cooper wrote:
> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Tuesday, July 05, 2016 11:19 AM
> To: Qiang Zhao
> Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@v
On 07/04/2016 11:55 PM, Benjamin Herrenschmidt wrote:
Have you considered instead adding a kref to the PHB and only freeing
it when all devices have been freed ? Or it's too hard to tract device
creation ?
Yes, considered it, but felt leery of possibly leaving the PHB unfreed
(or block until it
Morning!
On Tue, Jul 05, 2016 at 07:38:49AM +, Qiang Zhao wrote:
> On 07/05/2016 11:51 AM, Jason Cooper wrote:
> > On Tue, Jul 05, 2016 at 09:46:59AM +0800, Zhao Qiang wrote:
...
> > >
> > > Signed-off-by: Zhao Qiang
> > > ---
> > > drivers/irqchip/qe_ic.c| 83
> > > +++
On Thu, 2016-16-06 at 23:33:45 UTC, Chris Smart wrote:
> Calling ISA 3.0 instructions copy, copy_first, paste and paste_last
> generates an alignment fault when copying or pasting unaligned
> data (128 byte). We catch this and send SIGBUS to the userspace
> process that caused it.
>
> We do not em
On Thu, 2016-03-03 at 23:06:39 UTC, Cyril Bur wrote:
> Signed-off-by: Cyril Bur
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/94fa56a96a39914551694673fd
cheers
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On Sun, 2016-26-06 at 17:37:04 UTC, Madhavan Srinivasan wrote:
> Factor out some of the power8 pmu macros to
> new a header file to share with power9 pmu code.
> Just code movement and no logic change.
>
> Signed-off-by: Madhavan Srinivasan
Series applied to powerpc next, thanks.
https://git.ke
On Thu, 2016-03-03 at 23:06:40 UTC, Cyril Bur wrote:
> Currently it doesn't appear the resulting binary actually uses any Altivec
> or VSX instructions the solution is to explicitly tell GCC to use vector
> instructions and use vector types in the code.
>
> Part of this this issue can be GCC versi
On Thu, 2016-16-06 at 23:34:47 UTC, Chris Smart wrote:
> Test that an ISA 3.0 compliant machine performing an unaligned copy,
> copy_first, paste or paste_last is sent a SIGBUS.
>
> Signed-off-by: Chris Smart
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/4375088072295b09cc5d
On Tue, 2016-05-07 at 01:43:21 UTC, Oliver O'Halloran wrote:
> This patch adds the kernel command line parameter "no_tb_segs" which
> forces the kernel to use 256MB rather than 1TB segments. Forcing the use
> of 256MB segments makes it considerably easier to test code that depends
> on an SLB miss
On Thu, 2016-30-06 at 14:34:37 UTC, Oliver O'Halloran wrote:
> This patch adds an OPAL console backend to the powerpc boot wrapper so
> that decompression failures inside the wrapper can be reported to the
> user. This is important since it typically indicates data corruption in
> the firmware and
On Fri, 2016-18-03 at 06:36:33 UTC, Andrew Donnellan wrote:
> If ppc_rtas() is called with args.nargs == 16 and args.nret == 0, args.rets
> is set to point to &args.args[16], which is beyond the end of the args.args
> array. This results in a minor read overrun of the array when we check the
> firs
On Tue, 2016-08-03 at 21:26:17 UTC, Rasmus Villemoes wrote:
> cmm_mem_going_offline is (only) called from cmm_memory_cb(), which
> sends the return value through notifier_from_errno(). The latter
> expects 0 or -errno (notifier_to_errno(notifier_from_errno(x)) is 0
> for any x >= 0, so passing a po
On Wed, 2015-25-11 at 23:45:49 UTC, Anton Blanchard wrote:
> Check the assembler supports -maltivec by wrapping it with
> call as-option.
>
> Signed-off-by: Anton Blanchard
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/9ddf0075f9184f1e1dabf7bfea
cheers
_
On Fri, 2016-01-07 at 06:20:39 UTC, Oliver O'Halloran wrote:
> Power ISAv3 adds a large decrementer (LD) mode which increases the size
> of the decrementer register. The size of the enlarged decrementer
> register is between 32 and 64 bits with the exact size being dependent
> on the implementation
On Thu, 2016-02-06 at 12:02:01 UTC, Michael Ellerman wrote:
> These are useful little loops for smoke testing performance.
>
> Signed-off-by: Michael Ellerman
Applied to powerpc next.
https://git.kernel.org/powerpc/c/0c63e8b7b97fb72ef38c8edbfb
cheers
___
On Tue, Jul 05, 2016 at 07:27:21AM +, Qiang Zhao wrote:
> On 07/05/2016 11:19 AM, Jason Cooper wrote:
> > -Original Message-
> > From: Jason Cooper [mailto:ja...@lakedaemon.net]
> > Sent: Tuesday, July 05, 2016 11:19 AM
> > To: Qiang Zhao
> > Cc: o...@buserror.net; t...@linutronix.de;
On Tue, 2016-01-03 at 04:26:36 UTC, Cyril Bur wrote:
> Excerpt from man 2 perf_event_open:
>
> /proc/sys/kernel/perf_event_paranoid
> The perf_event_paranoid file can be set to restrict access to the
> performance counters.
> 2 allow only user-space measurements.
> 1 allow both kernel
On Fri, Jul 01, 2016 at 08:19:45AM +1000, Anton Blanchard wrote:
> From: Anton Blanchard
>
> Use the vector polynomial multiply-sum instructions in POWER8 to
> speed up crc32c.
>
> This is just over 41x faster than the slice-by-8 method that it
> replaces. Measurements on a 4.1 GHz POWER8 show i
Acked-by: Ian Munsie
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On 07/05/2016 11:19 AM, Jason Cooper wrote:
> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Tuesday, July 05, 2016 10:22 PM
> To: Qiang Zhao
> Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@
On 04/07/16 23:22, Ian Munsie wrote:
From: Ian Munsie
This extends the check that the adapter is in a CAPI capable slot so
that it may be called by external users in the kernel API. This will be
used by the upcoming Mellanox CX4 support, which needs to know ahead of
time if the card can be swit
On 04/07/16 23:21, Ian Munsie wrote:
From: Ian Munsie
The support for using the Mellanox CX4 in cxl mode will require
additions to the PHB code. In preparation for this, move the existing
cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things
more organised.
Signed-off-by: Ia
On 04/07/16 23:22, Ian Munsie wrote:
+static int setup_cxl_protocol_area(struct pci_dev *dev)
+{
+ u8 val;
+ int rc;
+ int vsec = find_cxl_vsec(dev);
+
+ if (!vsec) {
+ dev_info(&dev->dev, "CXL VSEC not found\n");
+ return -ENODEV;
+ }
+
+
On 04/07/16 23:22, Ian Munsie wrote:
From: Ian Munsie
Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus
master to be enabled in order for the CAPI traffic to flow. This should
be harmless to enable for other cxl devices, so unconditionally enable
it in the adapter init flow.
With Radix, it can be NULL even on !BOOKE these days so replace
the ifdef with a NULL check which is cleaner anyway.
Signed-off-by: Benjamin Herrenschmidt
---
Currently only compile tested
arch/powerpc/kernel/misc_64.S | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/a
Just using the hash ops won't work anymore since radix will have
NULL in there. Instead create an mmu_cleanup_all() function which
will do the right thing based on the MMU mode.
For Radix, for now I clear UPRT and the PTCR, effectively switching
back to Radix with no partition table setup.
Curren
Currently we turn the MMU off after copying the image, and we make
sure there is no overlap between the hash table and the target pages
in that case.
That doesn't work for Radix however. In that case, the page tables
are scattered and we can't really enforce that the target of the
image isn't over
The only difference is now the TCE table check which doesn't need
to be ifdef'ed out, it will basically do nothing on BookE (it is
only useful for ancient IBM machines).
Signed-off-by: Benjamin Herrenschmidt
---
Currently only compile tested
arch/powerpc/kernel/machine_kexec_64.c | 16 -
On Tue, Jul 05, 2016 at 04:05:58PM +1000, David Gibson wrote:
> On Tue, Jul 05, 2016 at 03:19:23PM +1000, Sam Bobroff wrote:
> > Signed-off-by: Sam Bobroff
>
> Ok, so the usual procedure for updates to linux-headers is this:
>1. Get the change merged on the kernel side
>
>2. Use scripts/
On 04/07/16 23:22, Ian Munsie wrote:
From: Ian Munsie
The CX4 card cannot cope with a context with PE=0 due to a hardware
limitation, resulting in:
[ 34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939
[ 34.166580] mlx5_core :01:00.1: Failed allocating uar, aborti
At the start of __tm_recheckpoint we save the kernel stack pointer
(r1) in SPRG SCRATCH0 (SPRG2) so that we can restore it after the
trecheckpoint.
Unfortunately, the same SPRG is used in the SLB miss handler. If an
SLB miss is taken between the save and restore of r1 to the SPRG, the
SPRG is cha
Hi, wanpeng
On 2016年07月05日 17:57, Wanpeng Li wrote:
Hi Xinhui,
2016-06-28 22:43 GMT+08:00 Pan Xinhui :
This is to fix some lock holder preemption issues. Some other locks
implementation do a spin loop before acquiring the lock itself. Currently
kernel has an interface of bool vcpu_is_preempted(
On Wed, Jul 06, 2016 at 02:41:52PM +1000, Sam Bobroff wrote:
> On Tue, Jul 05, 2016 at 04:05:58PM +1000, David Gibson wrote:
> > On Tue, Jul 05, 2016 at 03:19:23PM +1000, Sam Bobroff wrote:
> > > Signed-off-by: Sam Bobroff
> >
> > Ok, so the usual procedure for updates to linux-headers is this:
>
Use "Delta" to refer to the difference between measurements, rather than
"Error", so scripts that look for "Error" aren't confused into thinking
there was a failure.
Signed-off-by: Michael Ellerman
---
tools/testing/selftests/powerpc/pmu/ebb/instruction_count_test.c | 2 +-
1 file changed, 1 ins
There are a few issues with our handling of the ibm,pa-features
HTM bit:
- We don't support transactional memory in PR KVM, so don't tell
the OS that we do.
- In full emulation we have a minimal implementation of HTM that always
fails, so for performance reasons lets not tell the OS that we
Signed-off-by: Sam Bobroff
---
linux-headers/linux/kvm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index e60e21b..37cb3e8 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -866,6 +866,7 @@ struct kvm_ppc_smmu_
Advertise HTM support in ibm, pa-features if KVM indicates support when
queried via a new capability (KVM_CAP_PPC_HTM).
If KVM returns false for the capability (which may indicate that the
host kernel doesn't support the capability itself) attempt to
determine availability using a fallback method
Here's version 2.
Changes v1 -> v2:
Patch 2/3: spapr: Set ibm, pa-features HTM from KVM_CAP_PPC_HTM
* Improve readability of HTM bit set code.
* Move the test for KVM into kvmppc_get_htm_support().
Sam Bobroff (3):
spapr: Disable ibm, pa-features HTM bit
Add KVM_CAP_PPC_HTM to linux/kvm.h
Introduce a new KVM capability, KVM_CAP_PPC_HTM, that can be queried to
determine if a PowerPC KVM guest should use HTM (Hardware Transactional
Memory).
This will be used by QEMU to populate the pa-features bits in the
guest's device tree.
Signed-off-by: Sam Bobroff
---
arch/powerpc/kvm/powerp
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/qe_ic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, N
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/qe_ic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, N
qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- modify subject and commit msg
- return 0 and add pu
Cc Paolo, kvm ml
2016-07-06 12:58 GMT+08:00 xinhui :
> Hi, wanpeng
>
> On 2016年07月05日 17:57, Wanpeng Li wrote:
>>
>> Hi Xinhui,
>> 2016-06-28 22:43 GMT+08:00 Pan Xinhui :
>>>
>>> This is to fix some lock holder preemption issues. Some other locks
>>> implementation do a spin loop before acquiring t
On Tue, Jun 28, 2016 at 10:43:07AM -0400, Pan Xinhui wrote:
> change fomr v1:
> a simplier definition of default vcpu_is_preempted
> skip mahcine type check on ppc, and add config. remove dedicated macro.
> add one patch to drop overload of rwsem_spin_on_owner and
> mutex_spin_on
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