When we know we will reassign all resources, trying (and failing)
to allocate them initially is fairly pointless and leads to a lot
of scary messages in the kernel log
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/kernel/pci-common.c | 6 --
1 file changed, 4 insertions(+), 2 deleti
If the firmware encounters an error (internal or HW) during initialization
of a PHB, it might leave the device-node in the tree but mark it disabled
using the "status" property. We should check it.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/platforms/powernv/pci-ioda.c | 3 +++
1 fil
M64's are the configurable 64-bit windows that cover the 64-bit MMIO
space. We used to hard code 16 windows. Newer chips might have a
variable number and might need to reserve some as well (for example
on PHB4/POWER9, M32 and M64 are actually unified and we use M64#0
to map the 32-bit space).
So n
If we don't find registers for the PHB or don't know the model
specific invalidation method, use OPAL calls instead.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/platforms/powernv/pci-ioda.c | 33 +++
1 file changed, 29 insertions(+), 4 deletions(-)
diff --
It's architected, always in a known place, so there is no need
to keep a separate pointer to it, we use the existing "regs",
and we complement it with a real mode variant.
Signed-off-by: Benjamin Herrenschmidt
# Conflicts:
# arch/powerpc/platforms/powernv/pci-ioda.c
# arch/powerpc/pl
We have some obsolete code in pnv_pci_p7ioc_tce_invalidate()
to handle some internal lab tools that have stopped being
useful a long time ago. Remove that along with the definition
and test for the TCE_PCI_SWINV_* flags whose value is basically
always the same.
Signed-off-by: Benjamin Herrenschmid
The TCE invalidation functions are fairly implementation specific,
and while the IODA specs more/less describe the register, in practice
various implementation workarounds may be required. So name the
functions after the target PHB.
Note today and for the foreseeable future, there's a 1:1 relation
Replace the old generic opal_call_realmode() with proper per-call
wrappers similar to the normal ones and convert callers.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/opal-api.h| 10 +++-
arch/powerpc/include/asm/opal.h| 6 +++
arch/powerpc/ker
That was used by some old IBM internal bringup tools and is
no longer relevant.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/platforms/pseries/iommu.c | 53 +-
1 file changed, 1 insertion(+), 52 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/i
We instanciate them as IODA2. We also change the MSI EOI hack
to only kick on PHB3 since it will not be needed on any new
implementation.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/platforms/powernv/pci-ioda.c | 3 ++-
arch/powerpc/platforms/powernv/pci.c | 4
2 files chang
This adds a new XICS backend that uses OPAL calls, which can be
used when we don't have native support for the platform interrupt
controller.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/xics.h| 8 +-
arch/powerpc/sysdev/xics/Makefile | 2 +-
arch/powerpc/s
Calling this function with interrupts soft-disabled will cause
a replay of the external interrupt vector when they are re-enabled.
This will be used by the OPAL XICS backend (and latter by the native
XIVE code) to handle EOI signaling that there are more interrupts to
fetch from the hardware since
This will be delivering external interrupts from the XIVE to the
Hypervisor. We treat it as a normal external interrupt for the
lazy irq disable code (so it will be replayed as a 0x500) and
route it to do_IRQ.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/exception-64s.h |
OPAL provides an emulated XICS interrupt controller to
use as a fallback on newer processors that don't have a
XICS. It's meant as a way to provide backward compatibility
with future processors. Add the corresponding interfaces.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/
If hardware supports stop state, use the deepest stop state when
the cpu is offlined.
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
- No changes since v1
arch/powerpc/platforms/powernv/idle.c| 15 +--
arch/powerpc/platforms/powernv/powernv.h | 1 +
arch/p
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
Supported idle states and value to be written to PSSCR register to enter
any idle stat
- Use stack instead of kzalloc'ed memory for variables while probing
device tree for idle states.
- Set cap for number of idle states that can be added to
cpuidle_state_table
- Minor change in way we check of_property_read_u32_array for error
for sake of consistency
- Drop unnecessary
Use cpuidle's CPUIDLE_STATE_MAX macro instead of powernv specific
MAX_POWERNV_IDLE_STATES.
Cc: Rafael J. Wysocki
Cc: Daniel Lezcano
Cc: linux...@vger.kernel.org
Acked-by: Daniel Lezcano
Signed-off-by: Shreyas B. Prabhu
---
- No changes after v5
Changes in v5
=
- New in v5
driv
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
b) new per thread SPR named Processor Stop Status and Control Register
(PSSCR) is added which controls th
Create a function for saving SPRs before entering deep idle states.
This function can be reused for POWER9 deep idle states.
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
- No changes since v3
Changes in v3:
=
- Newly added in v3
arch/powerpc/kernel/idle_bo
pnv_powersave_common does common steps needed before entering idle
state and eventually changes MSR to MSR_IDLE and does rfid to
pnv_enter_arch207_idle_mode.
Move the updation of HSTATE_HWTHREAD_STATE to pnv_powersave_common
from pnv_enter_arch207_idle_mode and make it more generic by passing the
Functions like power7_wakeup_loss, power7_wakeup_noloss,
power7_wakeup_tb_loss are used by POWER7 and POWER8 hardware. They can
also be used by POWER9. Hence rename these functions hardware agnostic
names.
Suggested-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
- No changes since v
idle_power7.S handles idle entry/exit for POWER7, POWER8 and in next
patch for POWER9. Rename the file to a non-hardware specific
name.
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
Changes in v7:
=
- File renamed to idle_book3s.S instead of idle_power_common.
In the current code, when the thread wakes up in reset vector, some
of the state restore code and check for whether a thread needs to
branch to kvm is duplicated. Reorder the code such that this
duplication is avoided.
At a higher level this is what the change looks like-
Before this patch -
powe
Signed-off-by: Shreyas B. Prabhu
---
-No changes since v4
Changes in v4
=
- New in v4
arch/powerpc/kernel/idle_power7.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/idle_power7.S
b/arch/powerpc/kernel/idle_power7.S
index 470ceeb..705c867 1
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
The generic allocation code may sometimes decide to assign a prefetchable
64-bit BAR to the M32 window. In fact it may also decide to allocate
a 64-bit non-prefetchable BAR to the M64 one ! So using the resource
flags as a test to decide which window was used for PE allocation is
just wrong and lea
On Thu, Jul 07, 2016 at 11:21:18PM +1000, Benjamin Herrenschmidt wrote:
> I think the right fix is that if a restore_sigcontext() has the MSR bits set,
> it should set the corresponding used_* flag.
>
> Or is there a reason why that won't work ?
That sounds reaonable to me.
I will prepare a patch
Kees Cook writes:
> On Thu, Jul 7, 2016 at 4:01 AM, Arnd Bergmann wrote:
>> On Wednesday, July 6, 2016 3:25:20 PM CEST Kees Cook wrote:
>>> +
>>> + /* Allow kernel rodata region (if not marked as Reserved). */
>>> + if (ptr >= (const void *)__start_rodata &&
>>> + end <= (const v
Hi Michael,
On Wednesday 06 July 2016 03:38 PM, Michael Ellerman wrote:
Ravi Bangoria writes:
On Thursday 30 June 2016 11:51 AM, Michael Ellerman wrote:
On Thu, 2016-06-30 at 11:44 +0530, Ravi Bangoria wrote:
diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c
index 36a5825
From: Naveen N. Rao
Powerpc has long list of branch instructions and hardcoding them in
table appears to be error-prone. So, add new function to find
instruction instead of creating table. This function dynamically
create table(list of 'struct ins'), and instead of creating object
every time, fir
Change current data structures and function to enable cross arch
annotate.
Current implementation does not contain logic of record on one arch
and annotating on other. This remote annotate is partially possible
with current implementation for x86 (or may be arm as well) only.
But, to make remote a
Define macro for each normalized arch name and use them instead
of using arch name as string
Signed-off-by: Ravi Bangoria
---
Changes in v4:
- Moved position of patch
tools/perf/arch/common.c | 36 ++--
tools/perf/arch/common.h | 11
Perf can currently only support code navigation (branches and calls) in
annotate when run on the same architecture where perf.data was recorded.
But cross arch annotate is not supported.
This patchset enables cross arch annotate. Currently I've used x86
and arm instructions which are already avail
> > >
> > > @@ -439,7 +540,18 @@ timebase_resync:
> > > */
> > > bne cr4,clear_lock
> > >
> > > - /* Restore per core state */
> > > + /*
> > > + * First thread in the core to wake up and its waking up
> > > with
> > > + * complete hypervisor state loss. Restore per core
> > > hyperv
On 07/08/2016 07:50 AM, Michael Neuling wrote:
>
>> diff --git a/arch/powerpc/include/asm/cpuidle.h
>> b/arch/powerpc/include/asm/cpuidle.h
>> index d2f99ca..3d7fc06 100644
>> --- a/arch/powerpc/include/asm/cpuidle.h
>> +++ b/arch/powerpc/include/asm/cpuidle.h
>> @@ -13,6 +13,8 @@
>> #ifndef _
On Fri, 2016-07-08 at 12:55 +1000, Balbir Singh wrote:
> +
> > +/* For use by kexec */
> > +void mmu_cleanup_all(void)
> > +{
> > + if (radix_enabled())
> > + radix__mmu_cleanup_all();
>
>
> Should this be more than just radix -- cpu_has_feature(CPU_FTR_ARCH_300)?
I don't underst
This is so we can use the powernv_flash mtd driver as an block
device.
Signed-off-by: Michael Neuling
---
arch/powerpc/configs/powernv_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs/powernv_defconfig
b/arch/powerpc/configs/powernv_defconfig
index 959d32b..c35
On 07/07/2016 04:49 PM, Daniel Walker wrote:
> On 07/07/2016 02:23 PM, Scott Wood wrote:
>>
>> I suspect that add the usage of cspr_ext into the driver would fix the
>> issue we have. It reads like you would find that acceptable ?
>> What specifically is the problem you're having? Is it that CSPR_
On 06/07/16 14:35, Benjamin Herrenschmidt wrote:
> Currently we turn the MMU off after copying the image, and we make
> sure there is no overlap between the hash table and the target pages
> in that case.
>
> That doesn't work for Radix however. In that case, the page tables
> are scattered and
Hi Arnd,
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Thursday, July 07, 2016 4:30 PM
> To: Yangbo Lu
> Cc: Scott Wood; linuxppc-dev@lists.ozlabs.org; Mark Rutland; Ulf Hansson;
> linux-ker...@vger.kernel.org; linux-...@vger.kernel.org; linux-
> c...@vger.kern
On 06/07/16 14:34, Benjamin Herrenschmidt wrote:
> Just using the hash ops won't work anymore since radix will have
> NULL in there. Instead create an mmu_cleanup_all() function which
> will do the right thing based on the MMU mode.
>
> For Radix, for now I clear UPRT and the PTCR, effectively s
Except for the issue with patch 7 I've already commented on the rest of
this series is good with me. FWIW:
Acked-by: Michael Neuling
Thanks.
On Fri, 2016-07-08 at 02:17 +0530, Shreyas B. Prabhu wrote:
> POWER ISA v3 defines a new idle processor core mechanism. In summary,
> a) new instruction
> /*
> @@ -230,7 +238,7 @@ static int powernv_add_idle_states(void)
> strcpy(powernv_states[nr_idle_states].desc,
> "FastSleep");
> powernv_states[nr_idle_states].flags =
> CPUIDLE_FLAG_TIMER_STOP;
> powernv_states[nr
Quoting Scott Wood (2016-07-06 21:13:23)
> On Wed, 2016-07-06 at 18:30 -0700, Michael Turquette wrote:
> > Quoting Scott Wood (2016-06-15 23:21:25)
> > >
> > > -static struct device_node *cpu_to_clk_node(int cpu)
> > > +static struct clk *cpu_to_clk(int cpu)
> > > {
> > > - struct device_no
> diff --git a/arch/powerpc/include/asm/cpuidle.h
> b/arch/powerpc/include/asm/cpuidle.h
> index d2f99ca..3d7fc06 100644
> --- a/arch/powerpc/include/asm/cpuidle.h
> +++ b/arch/powerpc/include/asm/cpuidle.h
> @@ -13,6 +13,8 @@
> #ifndef __ASSEMBLY__
> extern u32 pnv_fastsleep_workaround_at_entr
On Thu, Jul 07, 2016 at 10:25PM , Jason Cooper wrote:
> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Thursday, July 07, 2016 10:25 PM
> To: Qiang Zhao
> Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com; linuxppc-
> d...@lists.ozlabs.org; lin
On 07/07/2016 03:37 PM, Scott Wood wrote:
On 07/07/2016 05:01 PM, Daniel Walker wrote:
On 07/07/2016 02:59 PM, Scott Wood wrote:
On 07/07/2016 04:49 PM, Daniel Walker wrote:
On 07/07/2016 02:23 PM, Scott Wood wrote:
I suspect that add the usage of cspr_ext into the driver would fix the
issue
On 07/07/2016 02:44 PM, Daniel Walker wrote:
> It seems natual that if cspr is in the device tree, you would also want
> cspr_ext because both are used to identify the device. The fact that
> it's missing to me is strange. As I said in my prior email, even if
> uboot sets those, you could have c
On 07/07/2016 05:01 PM, Daniel Walker wrote:
> On 07/07/2016 02:59 PM, Scott Wood wrote:
>> On 07/07/2016 04:49 PM, Daniel Walker wrote:
>>> On 07/07/2016 02:23 PM, Scott Wood wrote:
I suspect that add the usage of cspr_ext into the driver would fix the
issue we have. It reads like you wo
On 07/07/2016 02:59 PM, Scott Wood wrote:
On 07/07/2016 04:49 PM, Daniel Walker wrote:
On 07/07/2016 02:23 PM, Scott Wood wrote:
I suspect that add the usage of cspr_ext into the driver would fix the
issue we have. It reads like you would find that acceptable ?
What specifically is the problem
On 07/07/2016 03:52 PM, Daniel Walker wrote:
> On 07/07/2016 01:34 PM, Scott Wood wrote:
>> On 07/07/2016 02:44 PM, Daniel Walker wrote:
>>> It seems natual that if cspr is in the device tree, you would also want
>>> cspr_ext because both are used to identify the device. The fact that
>>> it's miss
On 07/07/2016 02:23 PM, Scott Wood wrote:
I suspect that add the usage of cspr_ext into the driver would fix the
issue we have. It reads like you would find that acceptable ?
What specifically is the problem you're having? Is it that CSPR_EXT is
not getting written to, and thus the device does
On 07/07/2016 10:48 AM, Daniel Walker wrote:
> On 07/06/2016 05:57 PM, Scott Wood wrote:
>> On 07/06/2016 03:23 PM, Daniel Walker wrote:
>>> Hi,
>>>
>>> We are using the t1040 platform, and we have found that we need to
>>> populate this register. In the Technical Reference Manual it's
>>> descript
On 07/07/2016 01:34 PM, Scott Wood wrote:
On 07/07/2016 02:44 PM, Daniel Walker wrote:
It seems natual that if cspr is in the device tree, you would also want
cspr_ext because both are used to identify the device. The fact that
it's missing to me is strange. As I said in my prior email, even if
If hardware supports stop state, use the deepest stop state when
the cpu is offlined.
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
- No changes since v1
arch/powerpc/platforms/powernv/idle.c| 15 +--
arch/powerpc/platforms/powernv/powernv.h | 1 +
arch/p
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
Supported idle states and value to be written to PSSCR register to enter
any idle stat
- Use stack instead of kzalloc'ed memory for variables while probing
device tree for idle states.
- Set cap for number of idle states that can be added to
cpuidle_state_table
- Minor change in way we check of_property_read_u32_array for error
for sake of consistency
- Drop unnecessary
Use cpuidle's CPUIDLE_STATE_MAX macro instead of powernv specific
MAX_POWERNV_IDLE_STATES.
Cc: Rafael J. Wysocki
Cc: Daniel Lezcano
Cc: linux...@vger.kernel.org
Acked-by: Daniel Lezcano
Signed-off-by: Shreyas B. Prabhu
---
- No changes after v5
Changes in v5
=
- New in v5
driv
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
b) new per thread SPR named Processor Stop Status and Control Register
(PSSCR) is added which controls th
Create a function for saving SPRs before entering deep idle states.
This function can be reused for POWER9 deep idle states.
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
- No changes since v3
Changes in v3:
=
- Newly added in v3
arch/powerpc/kernel/idle_bo
pnv_powersave_common does common steps needed before entering idle
state and eventually changes MSR to MSR_IDLE and does rfid to
pnv_enter_arch207_idle_mode.
Move the updation of HSTATE_HWTHREAD_STATE to pnv_powersave_common
from pnv_enter_arch207_idle_mode and make it more generic by passing the
Functions like power7_wakeup_loss, power7_wakeup_noloss,
power7_wakeup_tb_loss are used by POWER7 and POWER8 hardware. They can
also be used by POWER9. Hence rename these functions hardware agnostic
names.
Suggested-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
- No changes since v
idle_power7.S handles idle entry/exit for POWER7, POWER8 and in next
patch for POWER9. Rename the file to a non-hardware specific
name.
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
Changes in v7:
=
- File renamed to idle_book3s.S instead of idle_power_common.S
In the current code, when the thread wakes up in reset vector, some
of the state restore code and check for whether a thread needs to
branch to kvm is duplicated. Reorder the code such that this
duplication is avoided.
At a higher level this is what the change looks like-
Before this patch -
powe
Signed-off-by: Shreyas B. Prabhu
---
-No changes since v4
Changes in v4
=
- New in v4
arch/powerpc/kernel/idle_power7.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/idle_power7.S
b/arch/powerpc/kernel/idle_power7.S
index 470ceeb..705c867 1
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
On Thu, 2016-07-07 at 10:30 +0200, Arnd Bergmann wrote:
> On Thursday, July 7, 2016 2:35:33 AM CEST Yangbo Lu wrote:
> >
> > Hi Arnd,
> >
> > Could you reply when you see the email?
> > If your method doesn’t resolve the problem, we still want to use our old
> > patchset.
> >
> > This guts drive
On 07/07/2016 12:26 PM, Scott Wood wrote:
On 07/07/2016 10:48 AM, Daniel Walker wrote:
On 07/06/2016 05:57 PM, Scott Wood wrote:
On 07/06/2016 03:23 PM, Daniel Walker wrote:
Hi,
We are using the t1040 platform, and we have found that we need to
populate this register. In the Technical Referen
On Thu, 7 Jul 2016, Kees Cook wrote:
> On Thu, Jul 7, 2016 at 3:42 AM, Thomas Gleixner wrote:
> > I'd rather make that a weak function returning 1 which can be replaced by
> > x86 for CONFIG_FRAME_POINTER=y. That also allows other architectures to
> > implement their specific frame checks.
>
> Ye
On Thu, Jul 7, 2016 at 12:35 AM, Michael Ellerman wrote:
> Kees Cook writes:
>
>> Under CONFIG_HARDENED_USERCOPY, this adds object size checking to the
>> SLUB allocator to catch any copies that may span objects.
>>
>> Based on code from PaX and grsecurity.
>>
>> Signed-off-by: Kees Cook
>
>> di
Am Donnerstag, 07 Juli 2016, 11:00:25 schrieb AKASHI Takahiro:
> On Wed, Jul 06, 2016 at 04:29:18PM -0300, Thiago Jung Bauermann wrote:
> > Hi,
> >
> > Am Mittwoch, 06 Juli 2016, 16:52:26 schrieb AKASHI Takahiro:
> > > +linux,usable-memory
> > > +---
> > > +
> > > +This property is
Yes, You are right,
-Now Return type of 'qe_muram_alloc' is 'unsigned long', That Was trying
to assigned in member of this structure 'ucc_geth_private' . This
structure variable are 'unsigned int'. So before assignment need a
proper type casting.
-Passing value in IS_ERR_VALUE() is wrong. So
-Return type of 'qe_muram_alloc' is 'unsigned long', That Was trying to
assigned in ucc_fast_tx_virtual_fifo_base_offset and
ucc_fast_rx_virtual_fifo_base_offset. These variable are 'unsigned int'.
So before assginment need a proper type casting.
-Passing value in IS_ERR_VALUE() is wrong, as they
Hi Kees,
On Thu, Jul 07, 2016 at 01:25:21PM -0400, Kees Cook wrote:
> On Thu, Jul 7, 2016 at 1:37 AM, Baruch Siach wrote:
> > On Wed, Jul 06, 2016 at 03:25:20PM -0700, Kees Cook wrote:
> >> +#ifdef CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR
> >
> > Should be CONFIG_HARDENED_USERCOPY to match the sla
Ping ?
On Tue, 21 Jun 2016 11:02:01 +0200
Greg Kurz wrote:
> On Wed, 15 Jun 2016 22:26:41 +0200
> Greg Kurz wrote:
>
> > A strange behaviour is observed when comparing PCI hotplug in QEMU, between
> > x86 and pseries. If you consider the following steps:
> > - start a VM
> > - add a PCI device
On Thu, Jul 7, 2016 at 12:35 PM, Rik van Riel wrote:
> On Wed, 2016-07-06 at 15:25 -0700, Kees Cook wrote:
>>
>> + /* Allow kernel rodata region (if not marked as Reserved).
>> */
>> + if (ptr >= (const void *)__start_rodata &&
>> + end <= (const void *)__end_rodata)
>> +
On Thu, Jul 7, 2016 at 4:01 AM, Arnd Bergmann wrote:
> On Wednesday, July 6, 2016 3:25:20 PM CEST Kees Cook wrote:
>> This is the start of porting PAX_USERCOPY into the mainline kernel. This
>> is the first set of features, controlled by CONFIG_HARDENED_USERCOPY. The
>> work is based on code by Pa
On Thu, Jul 7, 2016 at 3:42 AM, Thomas Gleixner wrote:
> On Wed, 6 Jul 2016, Kees Cook wrote:
>> +
>> +#if defined(CONFIG_FRAME_POINTER) && defined(CONFIG_X86)
>> + const void *frame = NULL;
>> + const void *oldframe;
>> +#endif
>
> That's ugly
Yeah, I'd like to have this be controlled by
On Thu, Jul 7, 2016 at 3:30 AM, Christian Borntraeger
wrote:
> On 07/07/2016 12:25 AM, Kees Cook wrote:
>> Hi,
>>
>> This is a start of the mainline port of PAX_USERCOPY[1]. After I started
>> writing tests (now in lkdtm in -next) for Casey's earlier port[2], I
>> kept tweaking things further and
On Thu, Jul 7, 2016 at 1:37 AM, Baruch Siach wrote:
> Hi Kees,
>
> On Wed, Jul 06, 2016 at 03:25:20PM -0700, Kees Cook wrote:
>> +#ifdef CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR
>
> Should be CONFIG_HARDENED_USERCOPY to match the slab/slub implementation
> condition.
>
>> +const char *__check_heap_
On Thu, Jul 7, 2016 at 6:07 AM, Mark Rutland wrote:
> Hi,
>
> On Wed, Jul 06, 2016 at 03:25:23PM -0700, Kees Cook wrote:
>> Enables CONFIG_HARDENED_USERCOPY checks on arm64. As done by KASAN in -next,
>> renames the low-level functions to __arch_copy_*_user() so a static inline
>> can do additiona
On Thu, Jul 07, 2016 at 09:30:14PM +0530, Arvind Yadav wrote:
> Passing value in IS_ERR_VALUE() is wrong, as they pass an 'int'
> into a function that takes an 'unsigned long' argument.This happens
> to work because the type is sign-extended on 64-bit architectures
> before it gets converted into a
Yes, You are right,
-Now Return type of 'qe_muram_alloc' is 'unsigned long', That Was trying
to assigned in ucc_fast_tx_virtual_fifo_base_offset and
ucc_fast_rx_virtual_fifo_base_offset. These variable are 'unsigned int'.
So before assignment need a proper type casting.
-Passing value in IS_E
-Return type of 'qe_muram_alloc' is 'unsigned long', That Was trying to
assigned in ucc_fast_tx_virtual_fifo_base_offset and
ucc_fast_rx_virtual_fifo_base_offset. These variable are 'unsigned int'.
So before assginment need a proper type casting.
-Passing value in IS_ERR_VALUE() is wrong, as they
If the SRAM region parameters are missing the SRAM driver
probing exits and the L2 region is configured as L2 cache
entirely. This is the expected default behaviour, so it
makes no sense to report it as an error.
Signed-off-by: Claudiu Manoil
---
v2: drop info print
arch/powerpc/sysdev/fsl_85x
On Wed, 2016-07-06 at 15:25 -0700, Kees Cook wrote:
>
> + /* Allow kernel rodata region (if not marked as Reserved).
> */
> + if (ptr >= (const void *)__start_rodata &&
> + end <= (const void *)__end_rodata)
> + return NULL;
>
One comment here.
__check_object_size get
On Thu, Jul 07, 2016 at 08:57:29PM +0530, Arvind Yadav wrote:
> Passing value in IS_ERR_VALUE() is wrong, as they
> pass an 'int' into a function that takes an 'unsigned long'
> argument. This happens to work because the type is sign-extended
> on 64-bit architectures before it gets con
This uses all the infrastructure built up by the previous patches
in the series to load an ELF vmlinux file and an initrd. It uses the
flattened device tree at initial_boot_params as a base and adjusts memory
reservations and its /chosen node for the next kernel.
elf64_apply_relocate_add was exten
This purgatory implementation comes from kexec-tools, almost unchanged.
The only changes were that the sha256_regions global variable was
renamed to sha_regions to match what kexec_file_load expects, and to
use the sha256.c file from x86's purgatory to avoid adding yet another
SHA-256 implementati
Adds the basic machinery needed by kexec_file_load.
Signed-off-by: Josh Sklar
Signed-off-by: Thiago Jung Bauermann
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
---
arch/powerpc/Kconfig | 13 +
arch/powerpc/include/asm/systbl.h | 1 +
arch
A little endian kernel might need to kexec a big endian kernel (the
opposite is less likely but could happen as well), so we can't just cast
the buffer with the binary to ELF structs and use them as is done
elsewhere.
This patch adds functions which do byte-swapping as necessary when
populating th
The kexec_file_load system call needs to relocate the purgatory, so
factor out the module relocation code so that it can be shared.
This patch's purpose is to move the ELF relocation logic from
apply_relocate_add to elf_util_64.c with as few changes as
possible. The following changes were needed:
When apply_relocate_add is called, modules are already loaded at their
final location in memory so Elf64_Shdr.sh_addr can be used for accessing
the section contents as well as the base address for relocations.
This is not the case for kexec's purgatory, because it will only be
copied to its final
Adapt all callers to the new function prototype.
In addition, change the type of kexec_buf.buffer from char * to void *.
There is no particular reason for it to be a char *, and the change
allows us to get rid of 3 existing casts to char * in the code.
Signed-off-by: Thiago Jung Bauermann
Cc: Er
kexec_locate_mem_hole will be used by the PowerPC kexec_file_load
implementation to find free memory for the purgatory stack.
Signed-off-by: Thiago Jung Bauermann
Cc: Eric Biederman
Cc: Dave Young
---
include/linux/kexec.h | 1 +
kernel/kexec_file.c | 25 -
2 files c
Hello,
Note: We are currently discussing whether we need a new syscall so that
userspace can provide a custom device tree for the new kernel. Even if
that ends up being the way forward, it would affect only patches 7 and 8,
and even in those patches a significant part of the code would stay
the sa
Allow architectures to specify a different memory walking function for
kexec_add_buffer. x86 uses iomem to track reserved memory ranges, but
PowerPC uses the memblock subsystem.
Signed-off-by: Thiago Jung Bauermann
Cc: Eric Biederman
Cc: Dave Young
---
include/linux/kexec.h | 29
On Wed, 2016-07-06 at 15:25 -0700, Kees Cook wrote:
> This is the start of porting PAX_USERCOPY into the mainline kernel.
> This
> is the first set of features, controlled by CONFIG_HARDENED_USERCOPY.
> The
> work is based on code by PaX Team and Brad Spengler, and an earlier
> port
> from Casey Sc
Passing value in IS_ERR_VALUE() is wrong, as they pass an 'int'
into a function that takes an 'unsigned long' argument.This happens
to work because the type is sign-extended on 64-bit architectures
before it gets converted into an unsigned type.
Passing an 'unsigned short' or 'unsigned int'argumen
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