Architectures like ppc64 want to use page table deposit/withraw
even with huge pmd dax entries. Allow arch to override the
vma_is_anonymous check by moving that to pmd_move_must_withdraw
function
Acked-by: Kirill A. Shutemov
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64
Add arch specific callback in the generic THP page cache code that will
deposit and withdarw preallocated page table. Archs like ppc64 use
this preallocated table to store the hash pte slot information.
Testing:
kernel build of the patch series on tmpfs mounted with option huge=always
The related
From: Madalin Bucur
Date: Fri, 11 Nov 2016 10:20:00 +0200
> @@ -8,3 +8,12 @@ menuconfig FSL_DPAA_ETH
> supporting the Freescale QorIQ chips.
> Depends on Freescale Buffer Manager and Queue Manager
> driver and Frame Manager Driver.
> +
> +if FSL_DPAA_ETH
> +config FSL_DPAA
The Kconfig currently controlling compilation of this code is:
drivers/soc/fsl/Kconfig:config FSL_GUTS
drivers/soc/fsl/Kconfig:bool
...meaning that it currently is not being built as a module by anyone.
Lets remove the modular code that is essentially orphaned, so that
when reading the d
This series of commits is a part of a larger project to ensure
people don't reference modular support functions in non-modular
code. Overall there was roughly 5k lines of dead code in the
kernel due to this. So far we've fixed several areas, like tty,
x86, net, gpio ... and we continue to work on
On 11/11/16 16:55, Paul Mackerras wrote:
> This changes the way that we support the new ISA v3.00 HPTE format.
> Instead of adapting everything that uses HPTE values to handle either
> the old format or the new format, depending on which CPU we are on,
> we now convert explicitly between old and
Version v3.00 of the ISA added a new compat level to the processor
compatibility register (PCR), an ISA v2.07 compatibility mode.
Upstream QEMU already supports this so it may as well go into the kernel
now.
Change Log:
V1 -> V2:
- Reworked logic to set and mask the PCR, no functional change
V
ISA 3.00 adds the logical PVR value 0x0f05, so add a definition for
this.
Define PCR_ARCH_207 to reflect ISA 2.07 compatibility mode in the processor
compatibility register (PCR).
The next patch changes the algorithm used to determine the required PCR
value in the function kvmppc_set_arch_com
The function kvmppc_set_arch_compat() is used to determine the value of the
processor compatibility register (PCR) for a guest running in a given
compatibility mode. There is currently no support for v3.00 of the ISA.
Add support for v3.00 of the ISA which adds an ISA v2.07 compatilibity mode
to t
It helps clarify that the action taken is just for the primary
CPU and more action might be required for in the secondaries
in early_init_mmu_secondary. This patch does not introduce
a functional change
Signed-off-by: Balbir Singh
---
arch/powerpc/include/asm/book3s/64/mmu.h | 10 +-
ar
On Sun, Nov 13, 2016 at 08:30:25PM +0530, Aneesh Kumar K.V wrote:
> Add arch specific callback in the generic THP page cache code that will
> deposit and withdarw preallocated page table. Archs like ppc64 use
> this preallocated table to store the hash pte slot information.
>
> Testing:
> kernel b
The first patch sets up AMOR in hypervisor mode. AMOR
needs to be setup before IAMR (details of AMOR/IAMR in
each patch). The second patch enables detection of exceptions
generated due to instruction fetch violations caused
and OOPSs' the task. The third patch enables IAMR for
both hypervisor and g
AMOR should be setup in HV mode, we set it up once
and let the generic kernel handle IAMR. This patch is
used to enable storage keys in a following patch as
defined in ISA 3
Reported-by: Aneesh Kumar K.V
Signed-off-by: Balbir Singh
---
arch/powerpc/mm/pgtable-radix.c | 21 +
ISA 3 allows for prevention of instruction fetch and execution
of user mode pages. If such an error occurs, SRR1 bit 35
reports the error. We catch and report the error in do_page_fault()
Signed-off-by: Balbir Singh
---
arch/powerpc/mm/fault.c | 4
1 file changed, 4 insertions(+)
diff --gi
ISA 3 defines new encoded access authority that allows instruction
access prevention in privileged mode and allows normal access
to problem state. This patch just enables IAMR (Instruction Authority
Mask Register), enabling AMR would require more work.
I've tested this with a buggy driver and a si
On 11/10/16 at 05:27pm, Hari Bathini wrote:
> Traditionally, kdump is used to save vmcore in case of a crash. Some
> architectures like powerpc can save vmcore using architecture specific
> support instead of kexec/kdump mechanism. Such architecture specific
> support also needs to reserve memory,
On 14/11/16 02:00, Aneesh Kumar K.V wrote:
> Architectures like ppc64 want to use page table deposit/withraw
> even with huge pmd dax entries. Allow arch to override the
> vma_is_anonymous check by moving that to pmd_move_must_withdraw
> function
>
I think the changelog can be reworded a bit
I
Currently there's some CMO (Cooperative Memory Overcommit) code, in
plpar_wrappers.h. Some of it is #ifdef CONFIG_PSERIES and some of it
isn't. The end result being if a file includes plpar_wrappers.h it won't
build with CONFIG_PSERIES=n.
Fix it by moving the CMO code into platforms/pseries. The t
Hi Michael,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.9-rc5 next-2016]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Michael-Ellerman/powerpc-pseries-Move-CMO-cod
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