On 06/02/17 12:07, Andrew Donnellan wrote:
Commit 14a3ae34bfd0 ("cxl: Prevent read/write to AFU config space while AFU
not configured") introduced a rwsem to fix an invalid memory access that
occurred when someone attempts to access the config space of an AFU on a
vPHB whilst the AFU is deconfigu
On Tuesday 21 February 2017 10:13 AM, Balbir Singh wrote:
On Sun, Feb 19, 2017 at 03:37:08PM +0530, Aneesh Kumar K.V wrote:
In followup patch we want to increase the va range which will result
in us requiring high_slices to have more than 64 bits. To enable this
convert high_slices to bitmap.
On 02/21/2017 08:05 AM, Nicholas Piggin wrote:
> On Tue, 21 Feb 2017 07:21:56 +0530
> Mahesh J Salgaonkar wrote:
>
>> +enum MCE_TlbErrorType {
>> +MCE_TLB_ERROR_INDETERMINATE = 0,
>> +MCE_TLB_ERROR_PARITY = 1,
>> +MCE_TLB_ERROR_MULTIHIT = 2,
>> +MCE_TLB_ERROR_TLBIEL_PROG_ERROR = 3
在 2017/2/21 09:58, Guilherme G. Piccoli 写道:
Currently the xmon debugger is set only via kernel boot command-line.
It's disabled by default, and can be enabled with "xmon=on" on the
command-line. Also, xmon may be accessed via sysrq mechanism.
But we cannot enable/disable xmon in runtime, it nee
The CAS process has been updated to change how the host to guest
negotiation is done for the new hash/radix mmu as well as the nest mmu,
process tables and guest translation shootdown (GTSE).
The host tells the guest which options it supports in
ibm,arch-vec-5-platform-support. The guest then choo
CAS now requires the guest to tell the host whether it would like to use
a hash or radix mmu. It is possible to disable radix by passing
"disable_radix" on the command line. The next patch will add support for
the new CAS format, thus we need to parse the command line before calling
CAS so we can c
On 2017-02-20 16:25, abdul wrote:
Hi,
next-20170220 fails to build on Power 8 (PowerVM LPAR) with these
errors.
with same config, next-20170215 builds fine.
the config file used is attached, by default
CONFIG_VIRT_CPU_ACCOUNTING_NATIVE was not set.
(X) Simple tick based cputime accounting
Michael Ellerman writes:
> "Guilherme G. Piccoli" writes:
...
>
> Imagine you're debugging a machine and you drop into xmon to check
> something, then drop out again.
>
> Then you go away and leave the box, and it crashes into xmon, but xmon
> doesn't print a backtrace because you've already been
"Guilherme G. Piccoli" writes:
> Subject: Re: [PATCH 2/3] powerpc/xmon: drop the nobt option from xmon plus
> minor fixes
In future please use the same version number for all patches of a
series.
ie. This should include a v2, like the rest of the patches in the series.
It confuses the tools to
Douglas Miller writes:
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 9c0e17c..6249975 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -2334,9 +2338,49 @@ static void dump_pacas(void)
> }
> #endif
>
> +static void dump_by_size(unsigned
On Sun, Feb 19, 2017 at 03:37:10PM +0530, Aneesh Kumar K.V wrote:
> With current kernel, we use the top 4 context for the kernel. Kernel VSIDs
> are built
> using these top context values and effective segemnt ID. In the following
> patches,
> we want to increase the max effective address to 512T
On Sun, Feb 19, 2017 at 03:37:09PM +0530, Aneesh Kumar K.V wrote:
> This avoid copying the slice_mask struct as function return value
>
> Signed-off-by: Aneesh Kumar K.V
> ---
Makes sense, since we are no longer restricted to u64
Acked-by: Balbir Singh
On Tue, 21 Feb 2017 09:47:53 +0530
Mahesh Jagannath Salgaonkar wrote:
> On 02/21/2017 08:17 AM, Nicholas Piggin wrote:
> > On Tue, 21 Feb 2017 07:22:56 +0530
> > Mahesh J Salgaonkar wrote:
> >
> >> From: Mahesh Salgaonkar
> >>
> >> Delay it until we are done with machine_check_early() call.
On Sun, Feb 19, 2017 at 03:37:08PM +0530, Aneesh Kumar K.V wrote:
> In followup patch we want to increase the va range which will result
> in us requiring high_slices to have more than 64 bits. To enable this
> convert high_slices to bitmap. We keep the number bits same in this patch
> and later ch
From: Mahesh Salgaonkar
machine_check_early() gets called in real mode. The very first time when
add_taint() is called, it prints a warning which ends up calling opal
call (that uses OPAL_CALL wrapper) for writing it to console. If we get a
very first machine check while we are in opal we are doo
From: Mahesh Salgaonkar
Some interrupt handler's may not be happy to call printk and would lead to
unexpected behavior or kernel panic. e.g. machine_check_early() from MCE
handler on OPAL based system. Introduce add_taint variant that does not call
printk.
Signed-off-by: Mahesh Salgaonkar
---
On 02/21/2017 08:17 AM, Nicholas Piggin wrote:
> On Tue, 21 Feb 2017 07:22:56 +0530
> Mahesh J Salgaonkar wrote:
>
>> From: Mahesh Salgaonkar
>>
>> Delay it until we are done with machine_check_early() call. Turn on MSR[ME]
>> once opal is done with processing MCE.
>
> Why? This seems like quit
> On 20-Feb-2017, at 8:27 PM, Jason Baron wrote:
>
> Hi,
>
> On 02/19/2017 09:07 AM, Sachin Sant wrote:
>> While booting next-20170217 on a POWER8 LPAR following
>> warning is displayed.
>>
>> Reverting the following commit helps boot cleanly.
>> commit 3821fd35b5 : jump_label: Reduce the siz
> "Uma" == Uma Krishnan writes:
Uma> From: "Matthew R. Ochs" Add support for
Uma> a future IBM Coherent Accelerator (CXL) flash AFU with an ID of
Uma> 0x0624.
Applied to 4.11/scsi-queue.
--
Martin K. Petersen Oracle Linux Engineering
On Tue, Feb 21, 2017 at 01:38:54PM +1100, Alexey Kardashevskiy wrote:
> The iommu_table_ops callbacks are declared CPU endian as they take and
> return "unsigned long"; underlying hardware tables are big-endian.
>
> However get() was missing be64_to_cpu(), this adds the missing conversion.
>
> Th
On Tue, 21 Feb 2017 07:22:56 +0530
Mahesh J Salgaonkar wrote:
> From: Mahesh Salgaonkar
>
> Delay it until we are done with machine_check_early() call. Turn on MSR[ME]
> once opal is done with processing MCE.
Why? This seems like quite a regression -- the MCE handler today
has about 60 instruc
On POWERNV platform, in order to do DMA via IOMMU (i.e. 32bit DMA in
our case), a device needs an iommu_table pointer set via
set_iommu_table_base().
The codeflow is:
- pnv_pci_ioda2_setup_dma_pe()
- pnv_pci_ioda2_setup_default_config()
- pnv_ioda_setup_bus_dma() [1]
pnv_pci_ioda2
PNV_IODA_PE_DEV is only used for NPU devices (emulated PCI bridges
representing NVLink). These are added to IOMMU groups with corresponding
NVIDIA devices after all non-NPU PEs are setup; a special helper -
pnv_pci_ioda_setup_iommu_api() - handles this in pnv_pci_ioda_fixup().
The pnv_pci_ioda2_se
The iommu_table_ops callbacks are declared CPU endian as they take and
return "unsigned long"; underlying hardware tables are big-endian.
However get() was missing be64_to_cpu(), this adds the missing conversion.
The only caller of this is crash dump at arch/powerpc/kernel/iommu.c,
iommu_table_cl
On Tue, 21 Feb 2017 07:21:56 +0530
Mahesh J Salgaonkar wrote:
> +enum MCE_TlbErrorType {
> + MCE_TLB_ERROR_INDETERMINATE = 0,
> + MCE_TLB_ERROR_PARITY = 1,
> + MCE_TLB_ERROR_MULTIHIT = 2,
> + MCE_TLB_ERROR_TLBIEL_PROG_ERROR = 3,
> +};
The new TLBIE error isn't really a TLB error
New version of the series was sent, please ignore this one.
Thanks,
Guilherme
Currently the xmon debugger is set only via kernel boot command-line.
It's disabled by default, and can be enabled with "xmon=on" on the
command-line. Also, xmon may be accessed via sysrq mechanism.
But we cannot enable/disable xmon in runtime, it needs kernel reload.
This patch introduces a debug
From: Pan Xinhui
Once xmon is triggered by sysrq-x, it is enabled always afterwards even
if it is disabled during boot. This will cause a system reset interrupt
fail to dump. So keep xmon in its original state after exit.
We have several ways to set xmon on or off.
1) by a build config CONFIG_XM
The xmon parameter nobt was added long time ago, by commit 26c8af5f01df
("[POWERPC] print backtrace when entering xmon"). The problem that time
was that during a crash in a machine with USB keyboard, xmon wouldn't
respond to commands from the keyboard, so printing the backtrace wouldn't
be possible
This series contains some improvements and fixes to xmon:
1) Pan Xinhui fixed a long-term bug, in which the xmon debugger got
stuck enabled after invoked by sysrq, regardless the state it was
set in the kernel command-line.
2) A debugfs entry was added in order to allow users to enable/disable
xm
From: Mahesh Salgaonkar
Print out details about new MCE errors from Power9.
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/kernel/mce.c | 68 +
1 file changed, 68 insertions(+)
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
From: Mahesh Salgaonkar
For MCE that hit while in use mode MSR(HV=1,PR=1), print the task info on the
console MCE error log. This will help to identify application that stumbled
upon MCE error.
After this patch the MCE console log would look like:
[2.246155] Severe Machine check interrupt [
From: Mahesh Salgaonkar
For D-side errors we print data load/store address as 'Effective address'
that caused MC. In addition to that print NIP also at which interrupt was
taken.
After this patch the MCE console log would look like:
[1150485.962090] Severe Machine check interrupt [Recovered]
[1
From: Mahesh Salgaonkar
Delay it until we are done with machine_check_early() call. Turn on MSR[ME]
once opal is done with processing MCE.
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/kernel/exceptions-64s.S | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
From: Mahesh Salgaonkar
Once we get high level MCE error event from opal, process it and figure
out if it recoverable or not. If yes, take corrective actions.
TODO:
- Rework on handling of asynchronous MCE errors.
- Update opal_recover_mce() to ignore async errors.
- Update flush_and_reload_sl
From: Mahesh Salgaonkar
This is a RFC implementation that proposes an approach where linux would
still take an MCE interrupt but it would make opal call to handle all
chip specific processing to extract the error reason.
Opal will support OPAL_HANDLE_MACHINE_CHECK token if it implements
machine
From: Mahesh Salgaonkar
Going forward from Power9, linux would take firmware's (OPAL) help to
exract MCE error reason. OPAL will now handle all chip specific processing
to extract the error reason and send high level information through this
machine check event structure. Hence this structure is
This RFC patch series adds machine check handling for Power9. Starting from
power9 linux will depend on OPAL to handle chip specific processing for
extracting MCE error reason. This will allow linux to not worry about
chip/CPU specific bit encoding to find out MCE reason. Linux will make
OPAL call
With the inclusion of:
powerpc/pseries: Implement indexed-count hotplug memory remove
powerpc/pseries: Implement indexed-count hotplug memory add
we now have complete handling of the RTAS hotplug event format
as described by PAPR via ACR "PAPR Changes for Hotplug RTAS Events".
This capabilit
Nathan Fontenot writes:
> On 02/15/2017 10:34 PM, Michael Ellerman wrote:
>> Nathan Fontenot writes:
>>
>>> Revert the patch patch to auto-online hotplugged memory, commit
>>> id ec999072442a. Using the auto-online acpability does online added
>>> memory but does not update the associated devic
This patch series adds the ability to configure the THREAD_SHIFT value and
thereby alter the stack size on powerpc systems. We are particularly interested
in configuring for a 32k stack on PPC64.
Using an NXP T2081 (e6500 PPC64 cores) we are observing stack overflows as a
result of applying a DTS
Shift the logic for defining THREAD_SHIFT logic to Kconfig in order to
allow override by users.
Signed-off-by: Hamish Martin
Reviewed-by: Chris Packham
---
arch/powerpc/Kconfig | 10 ++
arch/powerpc/include/asm/thread_info.h | 10 +-
2 files changed, 11 inserti
Fix an assembler error when the THREAD_SIZE is greater than 16k.
Signed-off-by: Hamish Martin
Reviewed-by: Chris Packham
---
arch/powerpc/kernel/head_64.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 1d
On Mon, 2017-02-20 at 14:04 -0800, Thomas Gleixner wrote:
> > HOWEVER. Looking at current upstream code I don't understand the error,
> > the DEBUG_SHIRQ code is calling the driver's handler not the flow
> > handler so it shouldn't be called handle_fasteoi_irq or am I missing
> > something ?
>
> I
On Tue, 21 Feb 2017, Benjamin Herrenschmidt wrote:
> On Mon, 2017-02-20 at 21:55 +1100, Michael Ellerman wrote:
> > But when we're called for CONFIG_DEBUG_SHIRQ get_irq() is not called,
> > precisely because we're faking an interrupt.
> >
> > I'm not sure if there's a good way to fix it :/
>
> I
On Mon, 2017-02-20 at 21:55 +1100, Michael Ellerman wrote:
> But when we're called for CONFIG_DEBUG_SHIRQ get_irq() is not called,
> precisely because we're faking an interrupt.
>
> I'm not sure if there's a good way to fix it :/
In the irq_replay path we have code to adjust the CPPR stack. We co
On 02/15/2017 10:34 PM, Michael Ellerman wrote:
> Nathan Fontenot writes:
>
>> Revert the patch patch to auto-online hotplugged memory, commit
>> id ec999072442a. Using the auto-online acpability does online added
>> memory but does not update the associated device struct to
>> indicate that the
POWER8 uses bit 36 in SRR1 like POWER9 for i-side machine checks,
and contains several similar conditions for link timeouts that
are not currently handled.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce_power.c | 26 +++---
1 file changed, 19 insertions(+), 7 dele
Merge the evaluation and handling of machine checks into the
same table matching loop.
This changes P7 and P8 ERAT flushing from using SLB flush to
using ERAT flush.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce_power.c | 325 ++--
1 file changed
This makes a change in that it no longer passes undefined DAR as
the effective address for those errors that don't define it.
This was tested with a userspace harness to exercise valid SRR1
and DSISR combinations.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce_power.c | 569
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/mce.h | 91
arch/powerpc/kernel/mce_power.c | 92 +
2 files changed, 92 insertions(+), 91 deletions(-)
diff --git a/arch/powerpc/include/asm/mce.h b/arch/
Add POWER9 machine check handler. There are several new types of errors
and also asynchonous machine checks added.
This doesn't reuse the P7/8 defines and functions because it becomes too
complex. Instead, future changes will rework all to use a table driven
approach.
Signed-off-by: Nicholas Pigg
Asynchronous machine checks don't correspond to the instruction or
even task that is currently running. Therefore only synchronous
machine checks should attempt to kill the currently running task
to recover.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/platforms/powernv/opal.c | 20 +-
Put the ifdefs into a flush handler call, and have callers ask for
particular type of flushes. Also add an ERAT flush type (although
existing ERAT flushing goes to the SLB flush path).
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce_power.c | 124 +++---
Currently these just hardcoded.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/mce.h | 3 ++-
arch/powerpc/kernel/mce.c | 5 +++--
arch/powerpc/kernel/mce_power.c | 6 ++
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/mce.h b/arch
Print the faulting address of the machine check that may help
with debugging. The effective address reported can be a target
memory address rather than an instruction address.
Fix up a dangling bracket while here.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce.c | 3 ++-
1 file chan
Hi,
The first part of this series up to patch 5 includes MCE handler
definitions for POWER9. Probably the biggest concern is the new
MCE types and how they are recorded and reported, so comments on
that would be welcome.
Patches 6 onward change the MCE parsing into a table base approach.
Note, th
On Fri, Feb 17, 2017 at 04:20:47PM -0800, Joe Perches wrote:
> If or when you apply it, you should
> fix it up to suit.
To repeat, I don't have this patch so someone will need to send it to
me.
> $ git log -1000 --pretty=oneline --no-merges sound/soc | \
> cut -f2- -d" " | cut -f1 -d":" |sort
On 02/16/2017 11:11 PM, Joe Perches wrote:
> To enable eventual removal of pr_warning
> ---
> arch/powerpc/platforms/ps3/device-init.c| 14 +++---
> arch/powerpc/platforms/ps3/mm.c | 4 ++--
> arch/powerpc/platforms/ps3/os-area.c| 2 +-
PS3 parts look
Hi,
On 02/19/2017 09:07 AM, Sachin Sant wrote:
> While booting next-20170217 on a POWER8 LPAR following
> warning is displayed.
>
> Reverting the following commit helps boot cleanly.
> commit 3821fd35b5 : jump_label: Reduce the size of struct static_key
>
> [ 11.393008] [ cut here
MMCRA[SDAR_MODE] specifices how the SDAR should be updated in
continous sampling mode. On P9 it must be set to 0b00 when
MMCRA[63] is set.
Fixes: c7c3f568beff2 ('powerpc/perf: macros for power9 format encoding')
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/isa207-common.c | 43 ++
Power9 DD1 do not support PMU_HAS_SIER flag and sdsync
in perf_get_data_addr() defaults to MMCRA_SDSYNC which
is wrong. Since power9 MMCRA does not support SDSYNC bit,
patch includes PPMU_NO_SIAR flag to the check and set the
sdsync with MMCRA_SAMPLE_ENABLE;
Signed-off-by: Madhavan Srinivasan
---
Fixes: 8034f715f ("powernv/opal-dump: Convert to irq domain")
Converts all the return explicit number to a more proper IRQ_HANDLED,
which looks proper incase of interrupt handler returning case.
Here, It also removes error message like "nobody cared" which was
getting unveiled while returning -1
Moves the return value check of 'opal_dump_info' to a proper place which
was previously unnecessarily filling all the dump info even on failure.
Signed-off-by: Mukesh Ojha
Acked-by: Stewart Smith
Acked-by: Jeremy Kerr
---
arch/powerpc/platforms/powernv/opal-dump.c | 9 ++---
1 file changed
On Thursday 16 February 2017 08:10 AM, Jeremy Kerr wrote:
Hi Mukesh,
The return value of an interrupt handler is the special type
irqreturn_t. An interrupt handler can return two special values,
IRQ_NONE or IRQ_HANDLED.
Yep, you can assume that the reader knows that level of the interrupt
ha
On 2017/02/17 05:42PM, Arnaldo Carvalho de Melo wrote:
> Em Fri, Feb 17, 2017 at 07:44:33PM +0900, Masami Hiramatsu escreveu:
> > On Thu, 16 Feb 2017 13:47:37 +0530
> > "Naveen N. Rao" wrote:
> >
> > > I am posting the powerpc bits in the same thread so as to keep these
> > > changes together. I
Sachin Sant writes:
>>> While booting next-20170217 on a POWER6 box, I ran into following
>>> warning. This is a full system lpar. Previous next tree was good.
>>> I will try a bisect tomorrow.
>>
>> Do you have CONFIG_DEBUG_SHIRQ=y ?
>>
>
> Yes. CONFIG_DEBUG_SHIRQ is enabled.
>
> As suggested
On 2017/02/19 01:42PM, Masami Hiramatsu wrote:
> On Fri, 17 Feb 2017 17:42:54 -0300
> Arnaldo Carvalho de Melo wrote:
>
> > Em Fri, Feb 17, 2017 at 07:44:33PM +0900, Masami Hiramatsu escreveu:
> > > On Thu, 16 Feb 2017 13:47:37 +0530
> > > "Naveen N. Rao" wrote:
> > >
> > > > I am posting the p
On 2017/02/17 05:42PM, Arnaldo Carvalho de Melo wrote:
> Em Fri, Feb 17, 2017 at 07:44:33PM +0900, Masami Hiramatsu escreveu:
> > On Thu, 16 Feb 2017 13:47:37 +0530
> > "Naveen N. Rao" wrote:
> >
> > > I am posting the powerpc bits in the same thread so as to keep these
> > > changes together. I
Hello Kishon!
It's nice to see that you are improving the dwc framework+drivers.
pcie-artpec6.c has the same quirk as dra7xx,
see define ARTPEC6_CPU_TO_BUS_ADDR.
I could create a patch, but I guess it would make more sense
if it's part of this series.
Keep up the good work!
Regards,
Niklas
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