On Wed, 2017-04-05 at 10:49 +0530, Anshuman Khandual wrote:
> This just adds user space exported ABI definitions for 2MB, 16MB, 1GB,
> 16GB non default huge page sizes to be used with mmap() system call.
>
> Signed-off-by: Anshuman Khandual
> ---
> These defined values will be used along with MAP
On Tuesday 04 April 2017 07:18 AM, Daniel Axtens wrote:
Hi,
+ do {
+ pages = PAGE_SIZE * i;
+ pcni->vbase[i++] = (u64)phys_to_virt(pcni->pbase +
+pages);
+ } whi
On Tuesday 04 April 2017 06:28 AM, Daniel Axtens wrote:
Hi all,
I'm trying to get my head around these patches - at this point I'm just
doing a first pass, so I may have more substantive structural comments
later on. In the mean time - here are some minor C nits:
+ * Copyright (C) 2016 Mad
On Wednesday 05 April 2017 11:05 AM, Anshuman Khandual wrote:
On 04/04/2017 07:33 PM, Aneesh Kumar K.V wrote:
This patch adds support for gigantic pages in ppc64. We also updates
gigantic_page_supported helper such that arch can override it.
Seems like only radix based 1GB is considered as g
Fix a boundary condition where in some cases an eeh event that results
in card reset isn't passed on to a driver attached to the virtual PCI
device associated with a slice. This will happen in case when a slice
attached device driver returns a value other than
PCI_ERS_RESULT_NEED_RESET from the eeh
During an eeh event when the cxl card is fenced and card sysfs attr
perst_reloads_same_image is set following warning message is seen in the
kernel logs:
[ 60.622727] Adapter context unlocked with 0 active contexts
[ 60.622762] [ cut here ]
[ 60.622771] WARNING: CP
Make sparsemem the default on all 64-bit Book3S platforms. It already is
for pseries and ps3, and we need to enable it for powernv because on
POWER9 memory between chips is discontiguous.
For the other platforms sparsemem should work fine, though it might add
a small amount of overhead. We can alw
On 30 March 2017 at 12:46, Naveen N. Rao
wrote:
> Also, with a simple module to memset64() a 1GB vmalloc'ed buffer, here
> are the results:
> generic:0.245315533 seconds time elapsed( +- 1.83% )
> optimized: 0.169282701 seconds time elapsed( +- 1.96% )
Wondering wha
On 04/04/2017 07:33 PM, Aneesh Kumar K.V wrote:
> This patch adds support for gigantic pages in ppc64. We also updates
> gigantic_page_supported helper such that arch can override it.
Seems like only radix based 1GB is considered as gigantic page in this
implementation. What about the existing 16G
This just adds user space exported ABI definitions for 2MB, 16MB, 1GB,
16GB non default huge page sizes to be used with mmap() system call.
Signed-off-by: Anshuman Khandual
---
These defined values will be used along with MAP_HUGETLB while calling
mmap() system call if the desired HugeTLB page si
On Tue, Apr 04, 2017 at 12:05:03PM +0200, Thomas Huth wrote:
> According to the PowerISA 2.07, mtspr and mfspr should not always
> generate an illegal instruction exception when being used with an
> undefined SPR, but rather treat the instruction as a NOP or inject a
> privilege exception in some c
On Tuesday 04 April 2017 07:18 AM, Daniel Axtens wrote:
Hi,
+#define IMC_MAX_CHIPS 32
+#define IMC_MAX_PMUS 32
+#define IMC_MAX_PMU_NAME_LEN 256
I've noticed this is used as both the maximum length for event names and
event value strings. Would an
On Wednesday 05 April 2017 08:29 AM, Alexey Kardashevskiy wrote:
On 04/04/17 19:26, Aneesh Kumar K.V wrote:
Alexey Kardashevskiy writes:
The CMA pages migration code does not support compound pages at
the moment so it performs few tests before proceeding to actual page
migration.
One of th
On 04/04/2017 04:11 AM, Michael Ellerman wrote:
> Haren Myneni writes:
>
>> [PATCH 1/5] crypto/nx: Rename nx842_powernv_function as icswx function
>>
>> nx842_powernv_function is points to nx842_icswx_function and
>> will be point to VAS function which will be added later for
>> P9 NX support.
>
On 04/04/17 19:26, Aneesh Kumar K.V wrote:
> Alexey Kardashevskiy writes:
>
>> The CMA pages migration code does not support compound pages at
>> the moment so it performs few tests before proceeding to actual page
>> migration.
>>
>> One of the tests - PageTransHuge() - has VM_BUG_ON_PAGE(PageTa
The pseries platform supports Power4 and later CPUs, all of which are
multithreaded and/or multicore.
In practice no one ever builds a SMP=n kernel for these machines. So as
we did for powernv, have the pseries platform imply SMP=y.
Signed-off-by: Michael Ellerman
---
arch/powerpc/platforms/pse
The powernv platform supports Power7 and later CPUs, all of which are
multithreaded and multicore.
As such we never build a SMP=n kernel for those machines, other than
possibly for debugging or running in a simulator.
In the debugging case we can get a similar effect by booting with
nr_cpus=1, or
Of the 64-bit Book3S platforms, only powermac supports booting on an
actual non-SMP system. The other platforms can be built with SMP
disabled, but it doesn't make a lot of sense given the CPUs they support
are all multicore or multithreaded.
So give platforms the option of forcing SMP=y.
Signed-
Hi Michael,
PowerPc 970 as classified as Power4 too, because is it a pure derivate.
If need i have a 970MP
Ciao
Luigi
Da: Linuxppc-dev
per conto di
Michael Ellerman
Inviato: martedì 4 aprile 2017 15.20
A: linuxppc-dev@
Oggetto: POWER4 - who has one?
Hi fo
On Apr 04 2017, Michael Ellerman wrote:
> Quick quiz, who still has a POWER4?
Does a G5 qualify?
> And if so are you running mainline on it?
Always following latest -rc.
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED
Sukadev Bhattiprolu [sukadevatlinux.vnet.ibm.com] wrote:
> Implement vas_init() and vas_exit() functions for a new VAS module.
> This VAS module is essentially a library for other device drivers
> and kernel users of the NX coprocessors like NX-842 and NX-GZIP.
> In the future this will be extended
Sukadev Bhattiprolu [sukadevatlinux.vnet.ibm.com] wrote:
> Define macros for the VAS hardware registers and bit-fields as well
> as couple of data structures needed by the VAS driver.
>
> Signed-off-by: Sukadev Bhattiprolu
> +++ b/arch/powerpc/platforms/powernv/vas.h
> @@ -0,0 +1,387 @@
> +/*
On 4/4/17, Michael Ellerman wrote:
> Hi folks,
>
> Quick quiz, who still has a POWER4?
>
> And if so are you running mainline on it?
Not the same thing, but I have a box on two 970MP
>
> cheers
>
On Tue, 4 Apr 2017 20:12:45 +1000
Alexey Kardashevskiy wrote:
> On 25/03/17 23:25, Alexey Kardashevskiy wrote:
> > On 25/03/17 07:29, Alex Williamson wrote:
> >> On Fri, 24 Mar 2017 17:44:06 +1100
> >> Alexey Kardashevskiy wrote:
> >>
> >>> The existing SPAPR TCE driver advertises both VFIO_
On Tue, 2017-04-04 at 23:03 +1000, Michael Ellerman wrote:
>
> > 14 files changed, 2186 insertions(+), 12 deletions(-)
>
> I'm not going to review this in one go, given it's 10:30pm already.
Well, good, I was about to send (well tomorrow morning actually) v2
hoping it was going to be final sinc
The patch series is not yet send to linux-mm. Once I get feedback on the
approach used, I will resend this to linux-mm.
Also if there is sufficient interest we could also get nohash hugetlb
migration to work. But I avoided doing that in this series, because of
my inability to test the change
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/Kconfig.cputype | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/platforms/Kconfig.cputype
b/arch/powerpc/platforms/Kconfig.cputype
index 382c3dd86d6d..c0ca27521679 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
We will be using this later from the ppc64 code. Change the return type to bool.
Signed-off-by: Aneesh Kumar K.V
---
include/linux/hugetlb.h | 1 +
mm/hugetlb.c| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
inde
The defaul implementation prints warning and returns NULL. We will add ppc64
support in later patches
Signed-off-by: Aneesh Kumar K.V
---
include/linux/hugetlb.h | 3 +++
mm/gup.c| 33 +
mm/hugetlb.c| 8
3 files changed, 44 i
ppc64 supports pgd hugetlb entries. Add code to handle hugetlb pgd entries to
follow_page_mask so that ppc64 can switch to it to handle hugetlbe entries.
Signed-off-by: Aneesh Kumar K.V
---
include/linux/hugetlb.h | 3 +++
mm/gup.c| 7 +++
mm/hugetlb.c| 9
Add follow_huge_pd implementation for ppc64.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hugetlbpage.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 80f6d2ed551a..9d66d4f
Makes code reading easy. No functional changes in this patch.
Signed-off-by: Aneesh Kumar K.V
---
mm/gup.c | 148 +++
1 file changed, 91 insertions(+), 57 deletions(-)
diff --git a/mm/gup.c b/mm/gup.c
index 04aa405350dc..73d46f9f7b81 1
The right interface to use to set a hugetlb pte entry is set_huge_pte_at. Use
that instead of set_pte_at.
Signed-off-by: Aneesh Kumar K.V
---
mm/migrate.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/mm/migrate.c b/mm/migrate.c
index 9a0897a14d37..4
This patch adds support for gigantic pages in ppc64. We also updates
gigantic_page_supported helper such that arch can override it.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hugetlb.h | 9 +
arch/powerpc/mm/hugetlbpage.c| 7 +--
arch/power
On 04/04/2017 02:03 PM, Aneesh Kumar K.V wrote:
>
>
> On Tuesday 04 April 2017 11:33 AM, Anshuman Khandual wrote:
>> This just adds user space exported ABI definitions for both 16MB and
>> 16GB non default huge page sizes to be used with mmap() system call.
>>
>> Signed-off-by: Anshuman Khandual
On Tue, 2017-04-04 at 22:20 +1000, Michael Ellerman wrote:
> Benjamin Herrenschmidt writes:
>
> ...
>
> Give me some change log !
Well, the subject says it all :-) Sync the API with the latest OPAL :-)
> > Signed-off-by: Benjamin Herrenschmidt
> > ---
> > arch/powerpc/include/asm/opal-api.h
Hi Michael,
Just a couple of basic things to check:
- was the dtb updated to the newest?
- is the qman node present? This should be easily visible in
/proc/device-tree/soc@ffe00/qman@318000.
---
Best Regards, Laurentiu
On 04/04/2017 08:03 AM, Michael Ellerman wrote:
> Horia Geantă writ
Hi folks,
Quick quiz, who still has a POWER4?
And if so are you running mainline on it?
cheers
Benjamin Herrenschmidt writes:
> The XIVE interrupt controller is the new interrupt controller
> found in POWER9. It supports advanced virtualization capabilities
> among other things.
>
> Currently we use a set of firmware calls that simulate the old
> "XICS" interrupt controller but this is fai
On 4/4/17, Michael Ellerman wrote:
> Denis Kirjanov writes:
>
>> hvc_remove() takes a spin lock first then acquires the console
>> semaphore. This situation can easily lead to a deadlock scenario
>> where we call scheduler with spin lock held.
>
> Have you actually hit the deadlock? Because that
[ This patch changed the code from using multiple come-from label names
to using a single err label. Both are terrible ways to do error
handling.
Come-From Labels:
Come-from labels look like this:
foo = alloc();
if (!foo)
goto alloc_failed;
The "
Benjamin Herrenschmidt writes:
...
Give me some change log !
> Signed-off-by: Benjamin Herrenschmidt
> ---
> arch/powerpc/include/asm/opal-api.h| 302
> -
It looks like you've just copied it over in its entirety, including lots
of unused cruft.
Please jus
"Naveen N. Rao" writes:
> (generic) is with Matt's arch-independent patches applied. Profiling
> indicates that most of the overhead is actually with the lzo
> decompression...
>
> Also, with a simple module to memset64() a 1GB vmalloc'ed buffer, here
> are the results:
> generic: 0.245315
Denis Kirjanov writes:
> hvc_remove() takes a spin lock first then acquires the console
> semaphore. This situation can easily lead to a deadlock scenario
> where we call scheduler with spin lock held.
Have you actually hit the deadlock? Because that code's been like that
for years and I've neve
Haren Myneni writes:
> [PATCH 5/5] crypto/nx: Add P9 NX specific error codes for 842 engine
>
> This patch adds changes for checking P9 specific 842 engine
> error codes. These errros are reported in co-processor status
> block (CSB) for failures.
But you just enabled support on P9 in patch 4.
Haren Myneni writes:
> [PATCH 3/5] crypto/nx: Create nx842_delete_coproc function
>
> Move deleting coprocessor info upon exit or failure to
> nx842_delete_coproc().
Naming again, this deletes *all* the coprocs, so the name should be
plural.
cheers
Haren Myneni writes:
> [PATCH 2/5] crypto/nx: Create nx842_cfg_crb function
>
> Configure CRB is moved to nx842_cfg_crb() so that it can be
> used for icswx function and VAS function which will be added
> later.
Buy a vowel! :)
nx842_configure_crb() is fine.
cheers
Haren Myneni writes:
> [PATCH 1/5] crypto/nx: Rename nx842_powernv_function as icswx function
>
> nx842_powernv_function is points to nx842_icswx_function and
> will be point to VAS function which will be added later for
> P9 NX support.
I know it's nit-picking but can you give it a better name
Hi Haren,
A few comments ...
Haren Myneni writes:
> diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
> index 4e5a470..7315621 100644
> --- a/arch/powerpc/include/asm/vas.h
> +++ b/arch/powerpc/include/asm/vas.h
> @@ -19,6 +19,8 @@
> #define VAS_RX_FIFO_SIZE_MIN (1 <
On 25/03/17 23:25, Alexey Kardashevskiy wrote:
> On 25/03/17 07:29, Alex Williamson wrote:
>> On Fri, 24 Mar 2017 17:44:06 +1100
>> Alexey Kardashevskiy wrote:
>>
>>> The existing SPAPR TCE driver advertises both VFIO_SPAPR_TCE_IOMMU and
>>> VFIO_SPAPR_TCE_v2_IOMMU types to the userspace and the u
According to the PowerISA 2.07, mtspr and mfspr should not always
generate an illegal instruction exception when being used with an
undefined SPR, but rather treat the instruction as a NOP or inject a
privilege exception in some cases, too - depending on the SPR number.
Also turn the printk here in
Daniel Axtens writes:
>> In that function, the flow is:
>> pagefault_disable();
>> enable_kernel_altivec();
>>
>> pagefault_enable();
>>
>> There are a few things that it would be nice (but by no means essential)
>> to find out:
>> - what is the difference between pagefault and prempt enabl
Benjamin Herrenschmidt writes:
> On Mon, 2017-04-03 at 23:29 +1000, Michael Ellerman wrote:
>> The other option would be just to make a rule that anything EXPORT'ed
>> must use _GLOBAL_TOC().
>
> Can we enforce that somewhat at build time ?
Yeah I had a quick look at doing that last night but di
Alexey Kardashevskiy writes:
> The CMA pages migration code does not support compound pages at
> the moment so it performs few tests before proceeding to actual page
> migration.
>
> One of the tests - PageTransHuge() - has VM_BUG_ON_PAGE(PageTail()) as
> it should be called on head pages. Since
Frederic Barrat writes:
> Commit 4c6d9acce1f4 ("powerpc/mm: Add hooks for cxl") converted local
> TLBIs to global if the cxl driver is active. It is necessary because
> the CAPP snoops invalidations to forward them to the PSL on the cxl
> adapter.
> However one path was apparently forgotten. nati
On Tuesday 04 April 2017 11:33 AM, Anshuman Khandual wrote:
This just adds user space exported ABI definitions for both 16MB and
16GB non default huge page sizes to be used with mmap() system call.
Signed-off-by: Anshuman Khandual
---
These defined values will be used along with MAP_HUGETLB w
On 04.04.2017 08:25, Paul Mackerras wrote:
> On Mon, Apr 03, 2017 at 01:23:15PM +0200, Thomas Huth wrote:
>> According to the PowerISA 2.07, mtspr and mfspr should not generate
>> an illegal instruction exception when being used with an undefined SPR,
>> but rather treat the instruction as a NOP, i
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