On Thu, Apr 13, 2017 at 12:39 PM, Balbir Singh wrote:
>>>
>>> Yes. It was derived from TASK_SIZE :
>>>
>>> http://lxr.free-electrons.com/source/arch/powerpc/include/asm/processor.h#L105
>>>
>>
>> That is getting update to 128TB by default and conditionally to 512TB
>>
>
> Since this is compile tim
Anshuman Khandual writes:
> This verifies virtual address mapping below and above the
> 128TB range and makes sure that address returned are within
> the expected range depending upon the hint passed from the
> user space.
>
> Signed-off-by: Anshuman Khandual
> ---
> Tested this on latest ppc-ne
Nicholas Piggin writes:
> The TLB flush for radix first flushes TLB for radix configuration,
> then flushes for hash configuration. The second flush is unnecessary
> but does not affect correctness.
>
> Fixes: 1a472c9dba6b9 ("powerpc/mm/radix: Add tlbflush routines")
> Signed-off-by: Nicholas Pig
On Thursday 13 April 2017 06:53 PM, Michael Ellerman wrote:
Peter Zijlstra writes:
On Tue, Apr 11, 2017 at 07:21:05AM +0530, Madhavan Srinivasan wrote:
From: Sukadev Bhattiprolu
perf_mem_data_src is an union that is initialized via the ->val field
and accessed via the bitmap fields. For t
On Thursday 13 April 2017 06:08 PM, Peter Zijlstra wrote:
On Tue, Apr 11, 2017 at 07:21:05AM +0530, Madhavan Srinivasan wrote:
From: Sukadev Bhattiprolu
perf_mem_data_src is an union that is initialized via the ->val field
and accessed via the bitmap fields. For this to work on big endian
pl
On 04/15/2017 01:48 AM, Michal Suchanek wrote:
> Hello,
>
> On Wed, 12 Apr 2017 15:11:12 +0530
> Anshuman Khandual wrote:
>
>> This verifies virtual address mapping below and above the
>> 128TB range and makes sure that address returned are within
>> the expected range depending upon the hint pa
To support disabling and enabling of irq with PMI, set of
new powerpc_local_irq_pmu_save() and powerpc_local_irq_restore()
functions are added. And powerpc_local_irq_save() implemented,
by adding a new soft_disable_mask manipulation function
soft_disable_mask_or_return().
Local_irq_pmu_* macros ar
Two new bit mask field "IRQ_DISABLE_MASK_PMU" is introduced to support
the masking of PMI and "IRQ_DISABLE_MASK_ALL" to aid interrupt masking checking.
Couple of new irq #defs "PACA_IRQ_PMI" and "SOFTEN_VALUE_0xf0*" added to
use in the exception code to check for PMI interrupts.
In the masked_int
Local atomic operations are fast and highly reentrant per CPU counters.
Used for percpu variable updates. Local atomic operations only guarantee
variable modification atomicity wrt the CPU which owns the data and
these needs to be executed in a preemption safe way.
Here is the design of this patch
To support addition of "bitmask" to MASKABLE_* macros,
factor out the EXCPETION_PROLOG_1 macro.
Make it explicit the interrupt masking supported
by a gievn interrupt handler. Patch correspondingly
extends the MASKABLE_* macros with an addition's parameter.
"bitmask" parameter is passed to SOFTEN_T
New Kconfig is added "CONFIG_IRQ_DEBUG_SUPPORT" to add warn_on
to alert the invalid transitions. Also moved the code under
the CONFIG_TRACE_IRQFLAGS in arch_local_irq_restore() to new Kconfig.
Reviewed-by: Nicholas Piggin
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/Kconfig | 4
Currently we use both EXCEPTION_PROLOG_1 and __EXCEPTION_PROLOG_1
in the MASKABLE_* macros. As a cleanup, this patch makes MASKABLE_*
to use only __EXCEPTION_PROLOG_1. There is not logic change.
Reviewed-by: Nicholas Piggin
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/excepti
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabledMSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts
Rename the paca->soft_enabled to paca->soft_disable_mask as
it is no more used as a flag for interrupt state.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/hw_irq.h | 26 +-
arch/powerpc/include/asm/kvm_ppc.h | 2 +-
arch/powerpc/include/asm/paca.h
Force use of soft_enabled_set() wrapper to update paca-soft_enabled
wherever possisble. Also add a new wrapper function, soft_enabled_set_return(),
added to force the paca->soft_enabled updates.
Reviewed-by: Nicholas Piggin
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/hw_irq.
Add new soft_enabled_* manipulation function and implement
arch_local_* using the soft_enabled_* wrappers.
Reviewed-by: Nicholas Piggin
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/hw_irq.h | 32 ++--
1 file changed, 14 insertions(+), 18 deletions(
Move set_soft_enabled() from powerpc/kernel/irq.c to
asm/hw_irq.c, to force updates to paca-soft_enabled
done via these access function. Add "memory" clobber
to hint compiler since paca->soft_enabled memory is the target
here
Renaming it as soft_enabled_set() will make
namespaces works better as p
Two #defs IRQ_DISABLE_LEVEL_NONE and IRQ_DISABLE_LEVEL_LINUX
are added to be used when updating paca->soft_enabled.
Replace the hardcoded values used when updating
paca->soft_enabled with IRQ_DISABLE_MASK_* #def.
No logic change.
Reviewed-by: Nicholas Piggin
Signed-off-by: Madhavan Srinivasan
--
Local atomic operations are fast and highly reentrant per CPU counters.
Used for percpu variable updates. Local atomic operations only guarantee
variable modification atomicity wrt the CPU which owns the data and
these needs to be executed in a preemption safe way.
Here is the design of the patchs
On Friday 14 April 2017 04:24 AM, Michael Ellerman wrote:
Madhavan Srinivasan writes:
@@ -269,7 +263,7 @@ notrace void arch_local_irq_restore(unsigned long en)
replay = __check_irq_replay();
/* We can soft-enable now */
- set_soft_enabled(IRQ_DISABLE_MASK_NONE);
+ s
The TLB flush for radix first flushes TLB for radix configuration,
then flushes for hash configuration. The second flush is unnecessary
but does not affect correctness.
Fixes: 1a472c9dba6b9 ("powerpc/mm/radix: Add tlbflush routines")
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce_pow
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