powerpc/numa: Correct the currently broken capability to set the
topology for shared CPUs in LPARs. At boot time for shared CPU
lpars, the topology for each shared CPU is set to node zero, however,
this is now updated correctly using the Virtual Processor Home Node
(VPHN) capabilities information
Removing or adding memory via the PowerPC hotplug interface currently
dumps newly added processors or memory into default node 0, instead of
into the node that would be calculated based upon the VPHN affinity
tables. The code was updated to ensure that all nodes found at boot
are still available
On Thu, May 18, 2017 at 08:31:33PM +1200, Chris Packham wrote:
> Signed-off-by: Chris Packham
> ---
> drivers/edac/mv64x60_edac.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/edac/mv64x60_edac.c b/drivers/edac/mv64x60_edac.c
> index 14b7e7b71eaa..454e1e26ee7c 100644
> --- a/
Hi Michael,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.12-rc2 next-20170526]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Michael-Bringmann/powerpc-numa-Update-CPU
Hi Michal,
I have considered your proposals:
1. Making memset(0) unconditional inside __init_single_page() is not
going to work because it slows down SPARC, and ppc64. On SPARC even the
BSTI optimization that I have proposed earlier won't work, because after
consulting with other engineers I
From: Michael Ellerman
> Sent: 26 May 2017 08:24
> Nicholas Piggin writes:
> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > index f11f65634aab..438fdb0fb142 100644
> > --- a/arch/powerpc/xmon/xmon.c
> > +++ b/arch/powerpc/xmon/xmon.c
> > @@ -1242,14 +1242,16 @@ bpt_cmds(vo
On Fri, May 26, 2017 at 01:46:58PM +1000, Michael Ellerman wrote:
Reza Arbab writes:
On Thu, May 25, 2017 at 04:19:53PM +1000, Michael Ellerman wrote:
The commit message for 3af229f2071f says:
In practice, we never see a system with 256 NUMA nodes, and in fact, we
do not support node h
Removing or adding memory via the PowerPC hotplug interface currently
dumps newly added processors or memory into default node 0, instead of
into the node that would be calculated based upon the VPHN affinity
tables. The code was updated to ensure that all nodes found at boot
are still available
powerpc/numa: Correct the currently broken capability to set the
topology for shared CPUs in LPARs. At boot time for shared CPU
lpars, the topology for each shared CPU is set to node zero, however,
this is now updated correctly using the Virtual Processor Home Node
(VPHN) capabilities information
I am running into this problem on PowerPC systems where Balbir's patch set
was targeted. So, yes, I do need to be able to add/enable a new numa node
during system execution in cases where more resources (memory, virtual
processors) are added to the system dynamically.
On 05/25/2017 10:46 PM, Mich
>> arch/powerpc/mm/numa.c |7 ---
>> 1 file changed, 7 deletions(-)
>>
>> diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
>> index 15c2dd5..18f3038 100644
>> --- a/arch/powerpc/mm/numa.c
>> +++ b/arch/powerpc/mm/numa.c
>> @@ -907,13 +907,6 @@ void __init initmem_init(void)
>>
On 2017-05-26 13:38, Madhavan Srinivasan wrote:
Commit 8d911904f3ce4 ('powerpc/perf: Add restrictions to PMC5 in power9
DD1')
was added to restrict the use of PMC5 in Power9 DD1. Intend is to
diable
the use of PMC5 using raw event code. Commit instead of updating
"power9_isa207_pmu"
structure,
Michael Ellerman writes:
> Ivan Mikhaylov writes:
>>
>> From my point of view it's possible. I've checked docu and on idea
>> it should be possible cause WP is only affecting watchdog ping time.
>
> The question is, is there any chance that leaving those bits set on
> another platform will cause
Hi Arnd,
On Fri, 26 May 2017 11:59:23 +0200 Arnd Bergmann wrote:
>
> On Fri, May 26, 2017 at 10:32 AM, Stephen Rothwell
> wrote:
> > Hi all,
> >
> > The arch version is identical except for comments and white space.
> >
> > Signed-off-by: Stephen Rothwell
>
> Acked-by: Arnd Bergmann
Thank
Hi Arnd,
On Fri, 26 May 2017 11:58:26 +0200 Arnd Bergmann wrote:
>
> I think I had a patch series to do those some 10 years ago and never
> submitted it ;-)
Ah ha! :-)
> Acked-by: Arnd Bergmann
>
> asm/sockios.h is identical to the asm-generic version, so we can do
> the same there.
Yes, I s
Dear Sir,
I do run test libspe2. For For 4.4.69, 4.10.17 and 4.11.3, they all seem
PASS even having error almost the same, but for 4.12-rc1 and 4.12-rc2 , it
is hanged up on test_context_create_error.
please see my two files attached for 4.11.3 and 4.12-rc2.
4.11.3
[ 240.975893] WARNING: CPU:
On Fri, May 26, 2017 at 10:32 AM, Stephen Rothwell
wrote:
> Hi all,
>
> The arch version is identical except for comments and white space.
>
> Signed-off-by: Stephen Rothwell
Acked-by: Arnd Bergmann
On Fri, May 26, 2017 at 8:19 AM, Stephen Rothwell wrote:
> These are completely obvious as all they do is include the asm-generic
> versions.
>
> Signed-off-by: Stephen Rothwell
I think I had a patch series to do those some 10 years ago and never
submitted it ;-)
Acked-by: Arnd Bergmann
asm/s
Hi all,
The arch version is identical except for comments and white space.
Signed-off-by: Stephen Rothwell
---
arch/powerpc/include/uapi/asm/Kbuild| 1 +
arch/powerpc/include/uapi/asm/sockios.h | 20
2 files changed, 1 insertion(+), 20 deletions(-)
delete mode 100644
Commit 8d911904f3ce4 ('powerpc/perf: Add restrictions to PMC5 in power9 DD1')
was added to restrict the use of PMC5 in Power9 DD1. Intend is to diable
the use of PMC5 using raw event code. Commit instead of updating
"power9_isa207_pmu"
structure, updated "power9_pmu" structure. Patch to fix the sa
Nicholas Piggin writes:
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index f11f65634aab..438fdb0fb142 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -1242,14 +1242,16 @@ bpt_cmds(void)
> {
> int cmd;
> unsigned long a;
> - int
On 2017-05-25, Nicolae Rosia wrote:
> I'm working on a real-time application using POSIX timers running on a
> QorIQ PowerPC platform with a 4.1 PREEMPT RT kernel and I'm trying to
> understand whether the following can happen:
>
> 1. A thread with a core affinity #0 creates a timer which will inv
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