This patch adds P9 NX support for 842 compression engine. Virtual
Accelerator Switchboard (VAS) is used to access 842 engine on P9.
For each NX engine per chip, setup receive window using
vas_rx_win_open() which configures RxFIFo with FIFO address, lpid,
pid and tid values. This unique (lpid, pid
This patch adds changes for checking P9 specific 842 engine
error codes. These errros are reported in coprocessor status
block (CSB) for failures.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/icswx.h | 3 +++
drivers/crypto/nx/nx-842-powernv.c | 18 ++
drivers/cry
Updating coprocessor list is moved to nx842_add_coprocs_list().
This function will be used for both icswx and VAS functions.
Signed-off-by: Haren Myneni
---
drivers/crypto/nx/nx-842-powernv.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/nx/nx-8
Move deleting coprocessors info upon exit or failure to
nx842_delete_coprocs().
Signed-off-by: Haren Myneni
---
drivers/crypto/nx/nx-842-powernv.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/crypto/nx/nx-842-powernv.c
b/drivers/crypto
Configure CRB is moved to nx842_configure_crb() so that it can
be used for icswx and VAS exec functions. VAS function will be
added later with P9 support.
Signed-off-by: Haren Myneni
---
drivers/crypto/nx/nx-842-powernv.c | 57 +-
1 file changed, 38 insertion
Rename nx842_powernv_function to nx842_powernv_exec.
nx842_powernv_exec points to nx842_exec_icswx and
will be point to VAS exec function which will be added later
for P9 NX support.
Signed-off-by: Haren Myneni
---
drivers/crypto/nx/nx-842-powernv.c | 20 +---
1 file changed, 13
P9 introduces Virtual Accelerator Switchboard (VAS) to communicate
with NX 842 engine. icswx function is used to access NX before.
On powerNV systems, NX-842 driver invokes VAS functions for
configuring RxFIFO (receive window) per each NX engine. VAS uses
this FIFO to communicate the request to NX
On 07/17/2017 11:53 PM, Ram Pai wrote:
> On Mon, Jul 17, 2017 at 04:50:38PM -0700, Haren Myneni wrote:
>>
>> This patch adds P9 NX support for 842 compression engine. Virtual
>> Accelerator Switchboard (VAS) is used to access 842 engine on P9.
>>
>> For each NX engine per chip, setup receive window
Try to allocate kernel page tables according to the node of
the memory they will map.
---
arch/powerpc/include/asm/book3s/64/hash.h | 2 +-
arch/powerpc/include/asm/book3s/64/radix.h | 2 +-
arch/powerpc/include/asm/sparsemem.h | 2 +-
arch/powerpc/kernel/setup_64.c | 3
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/setup_64.c | 51 ++
1 file changed, 32 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index d3c506a93b0b..5c89b771ac81 100644
--- a/arch/pow
Similary to the previous patch, allocate LPPACAs on a per-CPU basis,
attempting to get node-local memory.
---
arch/powerpc/include/asm/lppaca.h | 13 ++-
arch/powerpc/kernel/machine_kexec_64.c | 15 ++--
arch/powerpc/kernel/paca.c | 65 +++---
a
Change the paca array into an array of pointers to pacas. Allocate
pacas individually per CPU. Try to allocate node-local if possible.
Book3E not yet compiled.
Hash mode won't be able to get per-node allocations, but in theory
on node > 0 CPUs we could bolt an SLB at the bottom of their node
memo
Signed-off-by: Nicholas Piggin
---
include/linux/memblock.h | 5 -
mm/memblock.c| 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/include/linux/memblock.h b/include/linux/memblock.h
index 77d427974f57..03731a1ffa76 100644
--- a/include/linux/memblock.h
+++ b/i
The "lppaca" is a structure registered with the hypervisor. This
is unnecessary when running on non-virtualised platforms. One field
from the lppaca is also used by the host, so move that out into the
paca.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/paca.h | 8 ++--
These are unused in radix mode.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/paca.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index fd7deb79110a..032b073c2c30 100644
--- a/arch/powerpc/kernel/
Book3S radix-mode has no SLB interrupt limitation, and hash-mode has
a 1T limitation on modern CPUs.
Update the paca alloation limits to match the stack allocation. Book3E
still needs a look.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/paca.c | 37 +++-
Radix MMU does not take SLB or TLB interrupts when accessing kernel
linear address. Remove this restriction for radix mode.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/setup_64.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kerne
This removes the RMA limit on powernv platform, which constrains
early allocations such as PACAs and stacks. There are still other
restrictions that must be followed, such as bolted SLB limits, but
real mode addressing has no constraints.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/hash_u
Remove incorrect comment about real mode address restrictions on
powernv (bare metal), and unnecessary clamping to ppc64_rma_size.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/platforms/powernv/opal.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/plat
Hi,
This series isn't greatly polished or well tested yet, but it's
conceptually simple so I'll just get some comments. Powernv does not
have any real mode access limitation, and ISA3 radix does not have
any SLB/TLB limitation on the kernel linear address. We also can
avoid some allocations when n
On Fri, 21 Jul 2017 21:28:34 +0200,
Rob Herring wrote:
>
> Now that we have a custom printf format specifier, convert users of
> full_name to use %pOF instead. This is preparation to remove storing
> of the full path string for each node.
>
> Signed-off-by: Rob Herring
> Cc: Johannes Berg
> Cc:
dma_object.path is unused, so rather than fix it to work with DT
full_name changes, just remove it.
Signed-off-by: Rob Herring
Cc: Timur Tabi
Cc: Nicolin Chen
Cc: Xiubo Li
Cc: Fabio Estevam
Cc: Liam Girdwood
Cc: Mark Brown
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Cc: alsa-de...@alsa-project.o
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring
Cc: Johannes Berg
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Cc: Timur Tabi
Cc: Nicolin Chen
Cc
replace redundant code in __hash_page_64K(), __hash_page_huge(),
__hash_page_4K(), __hash_page_4K() and flush_hash_page() with
helper functions pte_get_hash_gslot() and pte_set_hash_slot()
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Ram Pai
---
arch/powerpc/mm/hash64_4k.c | 14 +
Introduce pte_get_hash_gslot()() which returns the slot number of the
HPTE in the global hash table.
This function will come in handy as we work towards re-arranging the
PTE bits in the later patches.
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Ram Pai
---
arch/powerpc/include/asm/book3s/64/h
Introduce pte_set_hash_slot().It sets the (H_PAGE_F_SECOND|H_PAGE_F_GIX)
bits at the appropriate location in the PTE of 4K PTE. For
64K PTE, it sets the bits in the second part of the PTE. Though
the implementation for the former just needs the slot parameter, it does
tak
The H_PAGE_F_SECOND,H_PAGE_F_GIX are not in the 64K main-PTE.
capture these changes in the dump pte report.
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Ram Pai
---
arch/powerpc/mm/dump_linuxpagetables.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/mm/
Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6
in the 64K backed HPTE pages. This along with the earlier
patch will entirely free up the four bits from 64K PTE.
The bit numbers are big-endian as defined in the ISA3.0
This patch does the following change to 64K PTE backed
by 64K H
Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6,
in the 4K backed HPTE pages.These bits continue to be used
for 64K backed HPTE pages in this patch, but will be freed
up in the next patch. The bit numbers are big-endian as
defined in the ISA3.0
The patch does the following change to t
RPAGE_RSV0..4 pte bits are currently used for hpte slot
tracking. We need these bits for memory-protection
keys. Luckily these four bits are relatively easier
to move among all the other candidate bits.
For 64K linux-ptes backed by 4k hptes, these bits
are used for tracking the
On Fri, Jul 21, 2017 at 03:24:05PM +1000, Balbir Singh wrote:
> It would be nice to be able to dump page tables in a
> particular context
>
> Example use cases
>
> Dumping PTE contents to see the keys (useful for debugging)
>
> c000ba48c880 c000bab438b0 2677 2675 T 2 protection_keys
Benjamin Herrenschmidt a écrit :
When hitting below a VM_GROWSDOWN vma (typically growing the stack),
we check whether it's a valid stack-growing instruction and we
check the distance to GPR1. This is largely open coded with lots
of comments, so move it out to a helper.
Did you have a look at
On Fri, Jul 21, 2017 at 12:21:50PM +0530, Aneesh Kumar K.V wrote:
> Ram Pai writes:
>
> > On Thu, Jul 20, 2017 at 12:12:47PM +0530, Aneesh Kumar K.V wrote:
> >> Ram Pai writes:
> >>
> >> > helper function that checks if the read/write/execute is allowed
> >> > on the pte.
> >> >
> >> > Signed-o
On Fri, Jun 30, 2017 at 02:53:31PM +0300, Ivan Mikhaylov wrote:
> Add mmc0 changes for enabling arasan emmc and change
> defconfig appropriately.
>
> Signed-off-by: Ivan Mikhaylov
> ---
> arch/powerpc/boot/dts/fsp2.dts | 33 +-
> arch/powerpc/configs/44x/fs
As for commit 68baf692c435 ("powerpc/pseries: Fix of_node_put()
underflow during DLPAR remove"), the call to of_node_put()
must be removed from pSeries_reconfig_remove_node().
dlpar_detach_node() and pSeries_reconfig_remove_node() call
of_detach_node(), and thus the node should not be released
in
On Fri, 2017-07-21 at 15:54 +0300, Ivan Mikhaylov wrote:
> Hi Ian,
> > Building the split device-tree tree[0] highlighted that upstream commit
> > 9eec6cb142bd ("powerpc/44x/fsp2: Add device tree for FSP2 board") introduced
> > this warning when building the device tree:
> >
> > $ make CROSS_COMPI
Hi Ian,
>Building the split device-tree tree[0] highlighted that upstream commit
>9eec6cb142bd ("powerpc/44x/fsp2: Add device tree for FSP2 board") introduced
>this warning when building the device tree:
>
>$ make CROSS_COMPILE=powerpc-linux-gnu- ARCH=powerpc fsp2.dtb
> CHK scripts/mod/devicet
Hi Linus,
Please pull some more powerpc fixes for 4.13:
The following changes since commit 01e6a61aceb82e13bec29502a8eb70d9574f97ad:
powerpc/64: Fix atomic64_inc_not_zero() to return an int (2017-07-12 21:49:55
+1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/li
On Tue, 2017-07-18 at 05:32:44 UTC, Nicholas Piggin wrote:
> A previous optimisation incorrectly assumed the PAPR hcall does
> not use r12, and clobbers it upon entry. In fact it is used as
> an input. This can result in KVM guests crashing (observed with
> PR KVM).
>
> Instead of using r12 to sav
On Fri, 2017-07-14 at 06:51:21 UTC, Michael Ellerman wrote:
> Move the core logic into a helper, so we can use it for changing permissions
> other than _PAGE_WRITE.
>
> Signed-off-by: Michael Ellerman
> Reviewed-by: Balbir Singh
Series applied to powerpc fixes.
https://git.kernel.org/powerpc/c
On Mon, 2017-07-10 at 06:19:38 UTC, Nicholas Piggin wrote:
> POWER9 DD2 can see spurious PMU interrupts after state-loss idle in
> some conditions.
>
> A solution is to save and reload MMCR0 over state-loss idle.
>
> Signed-off-by: Nicholas Piggin
> Acked-by: Madhavan Srinivasan
Applied to pow
From: "Gautham R. Shenoy"
Currently we use the stop-api provided by the firmware to program the
SLW engine to restore the values of hypervisor resources that get lost
on deeper idle states (such as winkle). Since the deep states were
only used for CPU-Hotplug on POWER8 systems, we would program t
From: "Gautham R. Shenoy"
The stop4 idle state on POWER9 is a deep idle state which loses
hypervisor resources, but whose latency is low enough that it can be
exposed via cpuidle.
Until now, the deep idle states which lose hypervisor resources (eg:
winkle) were only exposed via CPU-Hotplug. Hen
From: "Gautham R. Shenoy"
Hi,
This is the third iteration of the patchset to enable exploitation of
stop4 idle state on POWER9 via cpuidle.
The earlier version can be found here :
[v2]: https://lkml.org/lkml/2017/7/19/152
[v1]: https://lkml.org/lkml/2017/7/18/691
The changes across the version
Current vDSO64 implementation does not have support for coarse
clocks (CLOCK_MONOTONIC_COARSE, CLOCK_REALTIME_COARSE), for which it falls
back to system call. Below is a benchmark of the difference in execution
time with and without vDSO support.
(Non-coarse clocks are also included just for compl
(+ Hans)
On 21 July 2017 at 00:52, Daniel Axtens wrote:
> Hi Ard,
>
>> (+ Laszlo)
>>
>> On 19 July 2017 at 02:28, Daniel Axtens wrote:
>>> Hi all,
>>>
>>> Previously I posted a patch that provided a quirk for a hibmc card
>>> behind a particular Huawei bridge that allowed it to be marked as the
On Fri, 2017-07-21 at 16:59 +1000, Michael Ellerman wrote:
> Nice !
>
> Balbir Singh writes:
>
> > It would be nice to be able to dump page tables in a
> > particular context
> >
> > Example use cases
> >
> > Dumping PTE contents to see the keys (useful for debugging)
> >
> > c000ba48c880
* Michael Ellerman [2017-07-21 16:33:07]:
> Vaidyanathan Srinivasan writes:
> > * Nicholas Piggin [2017-07-21 11:16:44]:
> >> diff --git a/arch/powerpc/platforms/pseries/pseries_energy.c
> >> b/arch/powerpc/platforms/pseries/pseries_energy.c
> >> index 164a13d3998a..35c891aabef0 100644
> >> --
Victor Aoqui writes:
> Implemented default hugepage size verification (default_hugepagesz=)
> in order to allow allocation of defined number of pages (hugepages=)
> only for supported hugepage sizes.
>
> Signed-off-by: Victor Aoqui
> ---
> v2:
>
> - Renamed default_hugepage_setup_sz function to
Nice !
Balbir Singh writes:
> It would be nice to be able to dump page tables in a
> particular context
>
> Example use cases
>
> Dumping PTE contents to see the keys (useful for debugging)
>
> c000ba48c880 c000bab438b0 2677 2675 T 2 protection_keys
What is that ^ ?
> 0:mon> ds c0
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