Le 09/08/2017 à 04:29, Michael Ellerman a écrit :
Christophe LEROY writes:
Le 14/07/2017 à 08:51, Michael Ellerman a écrit :
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h
b/arch/powerpc/include/asm/book3s/64/pgtable.h
index c0737c86a362..3d562b210c65 100644
--- a/arch/powerpc/in
Jens Axboe writes:
> On 08/08/2017 04:16 AM, Michael Ellerman wrote:
>> Geoff Levand writes:
>>
>>> Hi Michael,
>>>
>>> A few very minor updates for PS3. Please apply.
>>
>> Jens do you want to take the block ones, or should I just take the lot?
>
> Up to you, I'm fine either way.
OK I'll gr
Sukadev Bhattiprolu writes:
> Michael Ellerman [m...@ellerman.id.au] wrote:
>> Sukadev Bhattiprolu writes:
>> > From fd0abf5c61b6041fdb75296e8580b86dc91d08d6 Mon Sep 17 00:00:00 2001
>> > From: Benjamin Herrenschmidt
>> > Date: Tue, 1 Aug 2017 20:54:41 -0500
>> > Subject: [PATCH] powerpc: xive:
On 07/25/2017 10:55 PM, Shilpasri G Bhat wrote:
In P9, OCC allows for clearing the sensor min-max history. This patch
exports attribute to reset history when set will clear the history of
all the sensors owned by CSM and belonging to the chip.
Signed-off-by: Shilpasri G Bhat
---
This patch is o
On Tue, Aug 08, 2017 at 10:56:13AM +0200, Cédric Le Goater wrote:
> xive_poke_esb() is performing a load/read so it is better named as
> xive_esb_read().
Uh, patch seems to mismatch the comment here, calling it
xive_peek_esb() instead.
Does reading the ESB had a side effect on the hardware? If s
On Tue, Aug 08, 2017 at 10:56:12AM +0200, Cédric Le Goater wrote:
> This is the framework for using XIVE in a PowerVM guest. The support
> is very similar to the native one in a much simpler form.
>
> Instead of OPAL calls, a set of Hypervisors call are used to configure
> the interrupt sources an
On Tue, Aug 08, 2017 at 10:56:18AM +0200, Cédric Le Goater wrote:
> '/ibm,plat-res-int-priorities' contains a list of priorities that the
> hypervisor has reserved for its own use. Scan these ranges to choose
> the lowest unused priority for the xive spapr backend.
>
> Signed-off-by: Cédric Le Goa
On Tue 8/8/2017 6:05 PM, Michael Ellerman wrote:
> -Original Message-
> From: Michael Ellerman [mailto:m...@ellerman.id.au]
> Sent: Tuesday, August 08, 2017 6:05 PM
> To: Qiang Zhao ; t...@linutronix.de
> Cc: o...@buserror.net; linuxppc-dev@lists.ozlabs.org; Xiaobo Xie
> ; linux-ker...@vg
Christophe LEROY writes:
> Le 14/07/2017 à 08:51, Michael Ellerman a écrit :
>> diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h
>> b/arch/powerpc/include/asm/book3s/64/pgtable.h
>> index c0737c86a362..3d562b210c65 100644
>> --- a/arch/powerpc/include/asm/book3s/64/pgtable.h
>> +++ b/arc
On 20/07/17 16:25, Matt Brown wrote:
The flush_dcache_phys_range function is no longer used in the kernel.
This patch removes and cleans up the function.
Signed-off-by: Matt Brown
That does indeed look unused.
Reviewed-by: Andrew Donnellan
--
Andrew Donnellan OzLabs, ADL Canbe
On 08/08/2017 08:05 PM, Laurent Dufour wrote:
> Add support for the new speculative faults events.
>
> Signed-off-by: Laurent Dufour
> ---
> tools/include/uapi/linux/perf_event.h | 2 ++
> tools/perf/util/evsel.c | 2 ++
> tools/perf/util/parse-events.c| 8
> tools
Michael Ellerman [m...@ellerman.id.au] wrote:
> Sukadev Bhattiprolu writes:
>
> > From fd0abf5c61b6041fdb75296e8580b86dc91d08d6 Mon Sep 17 00:00:00 2001
> > From: Benjamin Herrenschmidt
> > Date: Tue, 1 Aug 2017 20:54:41 -0500
> > Subject: [PATCH] powerpc: xive: ensure active irqd when setting a
Document the usage of the VAS Fast thread-wakeup API.
Thanks for input/comments from Benjamin Herrenschmidt, Michael Neuling,
Michael Ellerman, Robert Blackmore, Ian Munsie, Haren Myneni, Paul Mackerras.
Cc:Ian Munsie
Cc:Paul Mackerras
Signed-off-by: Sukadev Bhattiprolu
---
Documentation/powe
The Fast Thread Wake-up (FTW) driver provides user space applications an
interface to the Core-to-Core functionality in POWER9. The driver provides
the device node/ioctl API to applications and uses the external interfaces
to the VAS driver to interact with the VAS hardware.
A follow-on patch prov
Define the VAS_TX_WIN_OPEN and VAS_RX_WIN_OPEN ioctl interface. Each user
of VAS, like the NX-FTW driver in a follow-on patch, should implement
these ioctls.
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/include/uapi/asm/vas.h | 30 ++
1 file changed, 30 inserti
We need the SPRN_TIDR to bet set for use with fast thread-wakeup
(core-to-core wakeup). Each thread in a process needs to have a
unique id within the process but as explained below, for now, we
assign globally unique thread ids to all threads in the system.
Signed-off-by: Sukadev Bhattiprolu
---
Define interfaces (wrappers) to the 'copy' and 'paste' instructions
(which are new in PowerISA 3.0). These are intended to be used to
by NX driver(s) to submit Coprocessor Request Blocks (CRBs) to the
NX hardware engines.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v4]
- Export symb
Define an interface to open a VAS send window. This interface is
intended to be used the Nest Accelerator (NX) driver(s) to open
a send window and use it to submit compression/encryption requests
to a VAS receive window.
The receive window, identified by the [vasid, cop] parameters, must
already b
Define the vas_win_close() interface which should be used to close a
send or receive windows.
While the hardware configurations required to open send and receive windows
differ, the configuration to close a window is the same for both. So we use
a single interface to close the window.
Signed-off-
Define the vas_rx_win_open() interface. This interface is intended to be
used by the Nest Accelerator (NX) driver(s) to setup receive windows for
one or more NX engines (which implement compression/encryption algorithms
in the hardware).
Follow-on patches will provide an interface to close the win
Define the vas_rx_win_open() interface. This interface is intended to be
used by the Nest Accelerator (NX) driver(s) to setup receive windows for
one or more NX engines (which implement compression/encryption algorithms
in the hardware).
Follow-on patches will provide an interface to close the win
Define an interface to return a system-wide unique id for a given VAS
window.
The vas_win_id() will be used in a follow-on patch to generate an unique
handle for a user space receive window. Applications can use this handle
to pair send and receive windows for fast thread-wakeup.
The hardware ref
Define an interface that the NX drivers can use to find the physical
paste address of a send window. This interface is expected to be used
with the mmap() operation of the NX driver's device. i.e the user space
process can use driver's mmap() operation to map the send window's paste
address into th
Define helpers to allocate/free VAS window objects. These will
be used in follow-on patches when opening/closing windows.
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/platforms/powernv/vas-window.c | 70 +
1 file changed, 70 insertions(+)
diff --git a/arch/pow
Define helpers to initialize window context registers of the VAS
hardware. These will be used in follow-on patches when opening/closing
VAS windows.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v6]
- Add support for FTW windows and drop the fault window id
code since it is n
Define some helper functions to access the MMIO regions. We use these
in follow-on patches to read/write VAS hardware registers. They are
also used to later issue 'paste' instructions to submit requests to
the NX hardware engines.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog [v6]:
- M
Implement vas_init() and vas_exit() functions for a new VAS module.
This VAS module is essentially a library for other device drivers
and kernel users of the NX coprocessors like NX-842 and NX-GZIP.
In the future this will be extended to add support for user space
to access the NX coprocessors.
VA
Move the GET_FIELD and SET_FIELD macros to vas.h as VAS and other
users of VAS, including NX-842 can use those macros.
There is a lot of related code between the VAS/NX kernel drivers
and skiboot. For consistency switch the order of parameters in
SET_FIELD to match the order in skiboot.
Signed-of
Define macros for the VAS hardware registers and bit-fields as well
as couple of data structures needed by the VAS driver.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v6]
- Add some fields for FTW windows
Changelog[v4]
- [Michael Neuling] Move VAS code to arch/powerpc; Reorg
POWER9 introduces a hardware subsystem referred to as the Virtual
Accelerator Switchboard (VAS). VAS allows kernel subsystems and user
space processes to directly access the Nest Accelerator (NX) engines
which implement compression and encryption algorithms in the hardware.
NX has been in Power pr
On Mon, Aug 7, 2017 at 9:21 PM, Michael Ellerman wrote:
> Rob Herring writes:
>
>> On Tue, Jul 25, 2017 at 4:44 PM, Rob Herring wrote:
>>> This series is the last steps to remove storing the full path for every
>>> DT node. Instead, we can create full path strings dynamically as needed
>>> with
Add support for the new speculative faults events.
Signed-off-by: Laurent Dufour
---
tools/include/uapi/linux/perf_event.h | 2 ++
tools/perf/util/evsel.c | 2 ++
tools/perf/util/parse-events.c| 8
tools/perf/util/parse-events.l| 2 ++
tools/perf/util/pytho
Add support for the new speculative page faults software events.
Signed-off-by: Laurent Dufour
---
arch/powerpc/mm/fault.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index c6cd40901dd0..112c4bc9da70 100644
--- a/arc
Add support for the new speculative page faults software events.
Signed-off-by: Laurent Dufour
---
arch/x86/mm/fault.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 46fb9c2a832d..17985f11b9da 100644
--- a/arch/x86/mm/faul
Add new software events to count succeeded and failed speculative page
faults.
Signed-off-by: Laurent Dufour
---
include/uapi/linux/perf_event.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index b1c0b187acfe..fbfb03dff33
There is a deadlock when a CPU is doing a speculative page fault and
another one is calling do_unmap().
The deadlock occurred because the speculative path try to spinlock the
pte while the interrupt are disabled. When the other CPU in the
unmap's path has locked the pte then is waiting for all the
When dealing with speculative page fault handler, we may race with VMA
being split or merged. In this case the vma->vm_start and vm->vm_end
fields may not match the address the page fault is occurring.
This can only happens when the VMA is split but in that case, the
anon_vma pointer of the new VM
The speculative page fault handler must be protected against anon_vma
changes. This is because page_add_new_anon_rmap() is called during the
speculative path.
In addition, don't try speculative page fault if the VMA don't have an
anon_vma structure allocated because its allocation should be
protec
This patch enable the speculative page fault on the PowerPC
architecture.
This will try a speculative page fault without holding the mmap_sem,
if it returns with WM_FAULT_RETRY, the mmap_sem is acquired and the
traditional page fault processing is done.
Signed-off-by: Laurent Dufour
---
arch/po
From: Peter Zijlstra
Try a speculative fault before acquiring mmap_sem, if it returns with
VM_FAULT_RETRY continue with the mmap_sem acquisition and do the
traditional fault.
Signed-off-by: Peter Zijlstra (Intel)
[Clearing of FAULT_FLAG_ALLOW_RETRY is now done in
handle_speculative_fault()]
[
From: Peter Zijlstra
Provide infrastructure to do a speculative fault (not holding
mmap_sem).
The not holding of mmap_sem means we can race against VMA
change/removal and page-table destruction. We use the SRCU VMA freeing
to keep the VMA around. We use the VMA seqcount to detect change
(includi
The VMA sequence count has been introduced to allow fast detection of
VMA modification when running a page fault handler without holding
the mmap_sem.
This patch provides protection agains the VMA modification done in :
- madvise()
- mremap()
- mpol_rebind_policy()
From: Peter Zijlstra
Manage the VMAs with SRCU such that we can do a lockless VMA lookup.
We put the fput(vma->vm_file) in the SRCU callback, this keeps files
valid during speculative faults, this is possible due to the delayed
fput work by Al Viro -- do we need srcu_barrier() in unmount
somepla
From: Peter Zijlstra
Wrap the VMA modifications (vma_adjust/unmap_page_range) with sequence
counts such that we can easily test if a VMA is changed.
The unmap_page_range() one allows us to make assumptions about
page-tables; when we find the seqcount hasn't changed we can assume
page-tables are
When handling page fault without holding the mmap_sem the fetch of the
pte lock pointer and the locking will have to be done while ensuring
that the VMA is not touched in our back.
So move the fetch and locking operations in a dedicated function.
Signed-off-by: Laurent Dufour
---
mm/memory.c |
From: Peter Zijlstra
When speculating faults (without holding mmap_sem) we need to validate
that the vma against which we loaded pages is still valid when we're
ready to install the new PTE.
Therefore, replace the pte_offset_map_lock() calls that (re)take the
PTL with pte_map_lock() which can fa
This is a port on kernel 4.13 of the work done by Peter Zijlstra to
handle page fault without holding the mm semaphore [1].
The idea is to try to handle user space page faults without holding the
mmap_sem. This should allow better concurrency for massively threaded
process since the page fault han
From: Peter Zijlstra
One of the side effects of speculating on faults (without holding
mmap_sem) is that we can race with free_pgtables() and therefore we
cannot assume the page-tables will stick around.
Remove the reliance on the pte pointer.
Signed-off-by: Peter Zijlstra (Intel)
---
mm/memo
On 08/08/2017 04:16 AM, Michael Ellerman wrote:
> Geoff Levand writes:
>
>> Hi Michael,
>>
>> A few very minor updates for PS3. Please apply.
>
> Jens do you want to take the block ones, or should I just take the lot?
Up to you, I'm fine either way.
--
Jens Axboe
On 2017-08-08 09:15, David Laight wrote:
From: Pasha Tatashin
Sent: 08 August 2017 12:49
Thank you for looking at this change. What you described was in my
previous iterations of this project.
See for example here: https://lkml.org/lkml/2017/5/5/369
I was asked to remove that flag, and only ze
From: Pasha Tatashin
> Sent: 08 August 2017 12:49
> Thank you for looking at this change. What you described was in my
> previous iterations of this project.
>
> See for example here: https://lkml.org/lkml/2017/5/5/369
>
> I was asked to remove that flag, and only zero memory in place when
> need
> @@ -741,7 +741,11 @@ static int ps3vram_probe(struct ps3_system_bus_device
> *dev)
> goto out_unmap_reports;
> }
>
> - ps3vram_cache_init(dev);
> + error = ps3vram_cache_init(dev);
> + if (error < 0) {
> + goto out_unmap_reports;
> + }
> +
>
Hi Will,
> Damn, I actually prefer the flag :)
>
> But actually, if you look at our implementation of vmemmap_populate,
then we
> have our own version of vmemmap_populate_basepages that terminates at the
> pmd level anyway if ARM64_SWAPPER_USES_SECTION_MAPS. If there's
resistance
> to do this
On Tue, 8 Aug 2017 16:06:43 +0530
Gautham R Shenoy wrote:
> Hi Nicholas,
>
> On Sun, Aug 06, 2017 at 03:02:38AM +1000, Nicholas Piggin wrote:
> > POWER9 CPUs have independent MMU contexts per thread so KVM
> > does not have to bring sibling threads into real-mode when
> > switching MMU mode to g
On Tue, Aug 08, 2017 at 07:49:22AM -0400, Pasha Tatashin wrote:
> Hi Will,
>
> Thank you for looking at this change. What you described was in my previous
> iterations of this project.
>
> See for example here: https://lkml.org/lkml/2017/5/5/369
>
> I was asked to remove that flag, and only zero
head_8xx is dedicated to 8xx so no need to use macros that
depends on the CPU
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index a1c2a2cfe
Use symbolic names for DSISR bits in DSI
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 2 +-
arch/powerpc/mm/fault.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 778a0e11
For the 8xx, PVR values defined in arch/powerpc/include/asm/reg.h
are nowhere used.
Remove all defines and add PVR_8xx
Use it in arch/powerpc/kernel/cputable.c
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h | 6 ++
arch/powerpc/kernel/cputable.c | 2 +-
2 files changed,
Two config options exist to define powerpc MPC8xx:
* CONFIG_PPC_8xx
* CONFIG_8xx
arch/powerpc/platforms/Kconfig.cputype has contained the following
comment about CONFIG_8xx item for some years:
"# this is temp to handle compat with arch=ppc"
There is no more users of CONFIG_8xx, so remove it.
Si
4xx, CPM2 and 8xx cannot be selected at the same time, so
no need to test 8xx && !4xx && !CPM2. Testing 8xx is enough.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
inde
Two config options exist to define powerpc MPC8xx:
* CONFIG_PPC_8xx
* CONFIG_8xx
arch/powerpc/platforms/Kconfig.cputype has contained the following
comment about CONFIG_8xx item for some years:
"# this is temp to handle compat with arch=ppc"
arch/powerpc is now the only place with remaining use o
The 8xx cannot access the TBL and TBU registers using mfspr/mtspr
It must be accessed using mftb/mftbu
Due to this, there is a number of places with #ifdef CONFIG_8xx
This patch defines new macros MFTBL(x) and MFTBU(x) on the same model
as MFTB(x) and tries to make use of them as much as possible
mpc8xx_pic.c is dedicated to the 8xx, so move it to platform/8xx
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/Makefile | 2 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 2 +-
arch/powerpc/{sysdev/mpc8xx_pic.c => platforms/8xx/pic.c} | 2 +
To remain consistent with what is done with CPM2, let's link
CPM1 related parts to CONFIG_CPM1 instead of CONFIG_8xx
When something depends on both CPM1 and CPM2 we associate it
with CONFIG_CPM
Signed-off-by: Christophe Leroy
---
arch/powerpc/sysdev/Makefile | 3 ++-
arch/powerpc/sysdev/fsl_so
Since commit aa42c69c67f82 ("[POWERPC] Add support for FP emulation
for the e300c2 core"), program_check_exception() can be called for
math emulation. In that case, 'reason' is 0.
On the 8xx, there is a Software Emulation interrupt which is
called for all unimplemented and illegal instructions. Th
In the same spirit as what was done for 4xx and 44x, move
the 8xx machine check into platforms/8xx
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/traps.c| 25
arch/powerpc/platforms/8xx/Makefile| 2 +-
arch/powerpc/platforms/8xx/machine_chec
The entire 8xx directory is omitted if CONFIG_8xx is not enabled, so
within the 8xx/Makefile CONFIG_8xx is always y. So convert
obj-$(CONFIG_8xx) to the more obvious obj-y.
Signed-off-by: Christophe Leroy
---
This serie applies on top of Michael's serie begining with '[1/9] powerpc/47x:
Guard
This serie does some cleanup in the area of the 8xx.
In the same spirit as what Michael did for 4xx, move 8xx
specific stuff into platforms/8xx
Then try to reduce the amount of #ifdefs specific to 8xx
Remove the CONFIG_8xx which is redundant with CONFIG_PPC_8xx
Plus some misc cleanups
Christop
Hi Will,
Thank you for looking at this change. What you described was in my
previous iterations of this project.
See for example here: https://lkml.org/lkml/2017/5/5/369
I was asked to remove that flag, and only zero memory in place when
needed. Overall the current approach is better everywh
Both xive_core_init() and xive_native_init() are called from and call
__init routines, so they should also be __init.
Signed-off-by: Michael Ellerman
---
arch/powerpc/sysdev/xive/common.c | 4 ++--
arch/powerpc/sysdev/xive/native.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff -
early_check_vec5() is called from and calls __init routines, so should
also be __init.
Signed-off-by: Michael Ellerman
---
arch/powerpc/mm/init_64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index b1c83a6bfd54..588a5
Andreas Schwab writes:
> binutils >= 2.26 now warns about misuse of register expressions in
> assembler operands that are actually literals, for example:
>
> arch/powerpc/kernel/entry_64.S:535: Warning: invalid register expression
>
> Signed-off-by: Andreas Schwab
> ---
> arch/powerpc/include/a
On Tue, 2017-08-08 at 10:55:57 UTC, Michael Ellerman wrote:
> This reverts commit bc4f65e4cf9d6cc43e0e9ba0b8648cf9201cd55f.
>
> As reported by Andreas, this commit is causing unrecoverable SLB misses in the
> system call exit path:
>
> Unrecoverable exception 4100 at c000a1ec
> Oops:
The patch
ASoC: fsl: Convert to using %pOF instead of full_name
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and s
Hi all,
Apologies for the large Cc list, but wasn't really sure who to send this to.
I've seen this once on a Power8 box, with next-20170807.
I think it happened while I was running the memory hoptlug selftests.
cheers
[ 3532.474435] ==
[
This reverts commit bc4f65e4cf9d6cc43e0e9ba0b8648cf9201cd55f.
As reported by Andreas, this commit is causing unrecoverable SLB misses in the
system call exit path:
Unrecoverable exception 4100 at c000a1ec
Oops: Unrecoverable exception, sig: 6 [#1]
SMP NR_CPUS=2 PowerMac
...
CPU:
On Tue, 2017-08-08 at 06:37:24 UTC, Christophe Leroy wrote:
> commit d300627c6a536 ("powerpc/6xx: Handle DABR match before
> calling do_page_fault") breaks non 6xx platforms.
>
> [6.029556] Failed to execute /init (error -14)
> [6.034623] Starting init: /bin/sh exists but couldn't execute
On Fri, 2017-08-04 at 09:55:14 UTC, Frederic Barrat wrote:
> P9 has support for PCI peer-to-peer, enabling a device to write in the
> mmio space of another device directly, without interrupting the CPU.
>
> This patch adds support for it on powernv, by adding a new API to be
> called by drivers. T
On Fri, 2017-08-04 at 01:12:18 UTC, Matt Brown wrote:
> This adds the powernv_get_random_darn function which utilises the darn
> instruction, introduced in POWER9. The powernv_get_random_darn function
> is used as the ppc_md.get_random_seed on P9.
>
> The DARN instruction can potentially throw an
On Tue, 2017-08-01 at 10:29:22 UTC, Michael Ellerman wrote:
> Currently KERN_IO_START is defined as:
>
> #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
>
> Although it looks like a constant, both the components are actually
> variables, to allow us to have a different value bet
On Sun, Aug 06, 2017 at 03:02:41AM +1000, Nicholas Piggin wrote:
> When stop is executed with EC=ESL=0, it appears to execute like a
> normal instruction (resuming from NIP when woken by interrupt).
> So all the save/restore handling can be avoided completely. In
> particular NV GPRs do not have to
"Naveen N. Rao" writes:
> diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile
> index 0b2f771593eb..5f95af64cb8f 100644
> --- a/arch/powerpc/xmon/Makefile
> +++ b/arch/powerpc/xmon/Makefile
> @@ -7,6 +7,19 @@ UBSAN_SANITIZE := n
>
> ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
On Sun, Aug 06, 2017 at 03:02:40AM +1000, Nicholas Piggin wrote:
> The hardware can execute stop in any context, and KVM does not
> require real mode. This saves a switch to real-mode when going
> idle.
>
> Signed-off-by: Nicholas Piggin
Acked-by: Gautham R. Shenoy
> ---
> arch/powerpc/kernel
Sukadev Bhattiprolu writes:
> From fd0abf5c61b6041fdb75296e8580b86dc91d08d6 Mon Sep 17 00:00:00 2001
> From: Benjamin Herrenschmidt
> Date: Tue, 1 Aug 2017 20:54:41 -0500
> Subject: [PATCH] powerpc: xive: ensure active irqd when setting affinity
>
> Ensure irqd is active before attempting to set
On Sun, Aug 06, 2017 at 03:02:39AM +1000, Nicholas Piggin wrote:
> Signed-off-by: Nicholas Piggin
Reviewed-by: Gautham R. Shenoy
--
Thanks and Regards
gautham.
Hi Nicholas,
On Sun, Aug 06, 2017 at 03:02:38AM +1000, Nicholas Piggin wrote:
> POWER9 CPUs have independent MMU contexts per thread so KVM
> does not have to bring sibling threads into real-mode when
> switching MMU mode to guest. This can simplify POWER9 sleep/wake
> paths and avoids hwsyncs.
>
Geoff Levand writes:
> Hi Michael,
>
> A few very minor updates for PS3. Please apply.
Jens do you want to take the block ones, or should I just take the lot?
cheers
Daniel Axtens writes:
> Michael Ellerman writes:
>
>> Daniel Axtens writes:
>>
>>> Currently, we do a PCI fixup to mark a default card so that Xorg
>>> autoconfiguration works.
>>>
>>> There is a new generic method to do this sort of vga fixup, and
>>> it occurs by default.
>>>
>>> Drop our old
Qiang Zhao writes:
> On Mon 8/7/2017 3:02 PM, Michael Ellerman wrote:
>
>> -Original Message-
>> From: Michael Ellerman [mailto:m...@ellerman.id.au]
>> Sent: Monday, August 07, 2017 3:02 PM
>> To: Qiang Zhao ; t...@linutronix.de
>> Cc: o...@buserror.net; Qiang Zhao ; linuxppc-
>> d...@li
Christophe LEROY writes:
> Le 08/08/2017 à 04:16, Michael Ellerman a écrit :
>> Christophe LEROY writes:
>>
>>> Le 07/08/2017 à 12:41, Michael Ellerman a écrit :
On Wed, 2017-07-19 at 04:49:23 UTC, Benjamin Herrenschmidt wrote:
> This will allow simplifying the returns from do_page_fau
It will be required later by the H_INT_ESB hcall.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/asm/xive.h | 1 +
arch/powerpc/sysdev/xive/native.c | 2 ++
arch/powerpc/sysdev/xive/spapr.c | 2 ++
3 files changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/xive.h b/arch
xive_poke_esb() is performing a load/read so it is better named as
xive_esb_read(). Also introduce a XIVE_ESB_LOAD_EOI read when EOI'ing
LSI interrupts.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/common.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions
This is the framework for using XIVE in a PowerVM guest. The support
is very similar to the native one in a much simpler form.
Instead of OPAL calls, a set of Hypervisors call are used to configure
the interrupt sources and the event/notification queues of the guest:
- H_INT_GET_SOURCE_INFO
On Mon, Aug 07, 2017 at 04:38:45PM -0400, Pavel Tatashin wrote:
> To optimize the performance of struct page initialization,
> vmemmap_populate() will no longer zero memory.
>
> We must explicitly zero the memory that is allocated by vmemmap_populate()
> for kasan, as this memory does not go throu
On POWER9, the Client Architecture Support (CAS) negotiation process
determines whether the guest operates in XIVE Legacy compatibility or
in XIVE exploitation mode.
Now that we have initial guest support for the XIVE interrupt
controller, let's inform the hypervisor what we can do.
Signed-off-by
Platform Exploitation Mode support is indicated by the property
"ibm,arch-vec-5-platform-support-vec-5" : byte 23 bits 0-1 set to 0b01
or 0b10
OS Selection for Exploitation Mode is indicated by the property
"ibm,architecture-vec-5" : byte 23 bits 0-1 set to 0b01. A value of
0b00 indicates use of l
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/common.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/xive/common.c
b/arch/powerpc/sysdev/xive/common.c
index e6b245bb9602..22b6f8954083 100644
--- a/arch/powerpc/sysdev/xive/commo
Having the CPU identifier in the debug logs is helpful when tracking
issues. Also add some more logging and fix a compile issue in
xive_do_source_eoi().
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/common.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
'/ibm,plat-res-int-priorities' contains a list of priorities that the
hypervisor has reserved for its own use. Scan these ranges to choose
the lowest unused priority for the xive spapr backend.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/spapr.c | 62
Hello,
On a POWER9 sPAPR machine, the Client Architecture Support (CAS)
negotiation process determines whether the guest operates with an
interrupt controller using the legacy model, as found on POWER8, or in
XIVE exploitation mode, the newer POWER9 interrupt model. This
patchset is a first propos
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