Re: [PATCH 0/3] cxlflash: Miscellaneous fixes

Uma, > This patch series contains miscellaneous fixes. The first two address > issues that were identified by smatch and the last patch fixes a > regression introduced by Commit 565180723294 ("scsi: cxlflash: SISlite > updates to support 4 ports"). Applied to 4.14/scsi-queue. Thanks! --

[PATCH 3/3] cxlflash: Fix vlun resize failure in the shrink path

The ioctl DK_CAPI_VLUN_RESIZE can fail if the allocated vlun size is reduced from almost maximum capacity and then increased again. The shrink_lxt() routine is currently using the SISL_ASTATUS_MASK to mask the higher 48 bits of the lxt entry. This is unnecessary and incorrect as it uses a mask

[PATCH 2/3] cxlflash: Avoid double mutex unlock

From: "Matthew R. Ochs" The AFU recovery routine uses an interruptible mutex to control the flow of in-flight recoveries. Upon receiving an interruptible signal the code branches to a common exit path which wrongly assumes the mutex is held. Add a local variable to

[PATCH 1/3] cxlflash: Remove unnecessary existence check

From: "Matthew R. Ochs" The AFU termination sequence has been refactored over time such that the main tear down routine, term_afu(), can no longer can be invoked with a NULL AFU pointer. Remove the unnecessary existence check from term_afu(). Signed-off-by: Matthew R.

[PATCH 0/3] cxlflash: Miscellaneous fixes

This patch series contains miscellaneous fixes. The first two address issues that were identified by smatch and the last patch fixes a regression introduced by Commit 565180723294 ("scsi: cxlflash: SISlite updates to support 4 ports"). This series is intended for 4.14 and is bisectable. Matthew

Re: [PATCH v2 1/1] futex: remove duplicated code and fix UB

On Thu, 24 Aug 2017, Will Deacon wrote: > On Thu, Aug 24, 2017 at 09:31:05AM +0200, Jiri Slaby wrote: > > +static int futex_atomic_op_inuser(unsigned int encoded_op, u32 __user > > *uaddr) > > +{ > > + unsigned int op = (encoded_op & 0x7000) >> 28; > > + unsigned int cmp =

Re: [PATCH 2/2] of: Restrict DMA configuration

On Tue, Aug 15, 2017 at 09:19:50AM -0500, Rob Herring wrote: > > For the immediate issue at hand, I guess the alternative plan of attack > > would be to stick a flag in struct bus_type for the bus drivers > > themselves to opt into generic DMA configuration. That at least keeps > > everything

Re: [RFC Part1 PATCH v3 14/17] x86/boot: Add early boot support when running with SEV active

Btw, I don't see our SEV-specific chicken bit which disables SEV only. Do we need it? If so, maybe something like mem_encrypt=sme_only or so. Or is the mem_encrypt=off chicken bit enough? What about the use case where you want SME but no encrypted guests? A bunch of hmmm. --

[bug report] powerpc/mm/cxl: Add the fault handling cpu to mm cpumask

Hello Aneesh Kumar K.V, This is a semi-automatic email about new static checker warnings. The patch 0f4bc0932e51: "powerpc/mm/cxl: Add the fault handling cpu to mm cpumask" from Jul 27, 2017, leads to the following Smatch complaint: drivers/misc/cxl/fault.c:161 cxl_handle_mm_fault()

[GIT PULL] Please pull powerpc/linux.git powerpc-4.13-8 tag

Hi Linus, Please pull one more powerpc fix for 4.13: The following changes since commit 5a69aec945d27e78abac9fd032533d3aaebf7c1e: powerpc: Fix VSX enabling/flushing to also test MSR_FP and MSR_VEC (2017-08-16 19:35:54 +1000) are available in the git repository at:

Re: [PATCH v7 12/12] powerpc/vas: Define copy/paste interfaces

Hi Suka, A few more things ... Sukadev Bhattiprolu writes: > diff --git a/arch/powerpc/platforms/powernv/copy-paste.h > b/arch/powerpc/platforms/powernv/copy-paste.h > new file mode 100644 > index 000..7783bb8 > --- /dev/null > +++

[PATCH] powerpc/44x: mask and shift to zero bug

My static checker complains that 0x1800 >> 13 is zero. Looking at the context, it seems like a copy and paste bug from the line below and probably 0x3 << 13 or 0x6000 was intended. Fixes: 2af59f7d5c3e ("[POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper") Signed-off-by: Dan

Re: [PATCH v7 10/12] powerpc/vas: Define vas_win_close() interface

Hi Suka, More comments :) Sukadev Bhattiprolu writes: > diff --git a/arch/powerpc/platforms/powernv/vas-window.c > b/arch/powerpc/platforms/powernv/vas-window.c > index 2dd4b63..24288dd 100644 > --- a/arch/powerpc/platforms/powernv/vas-window.c > +++

Re: [PATCH v7 01/12] powerpc/vas: Define macros, register fields and structures

Sukadev Bhattiprolu writes: > diff --git a/arch/powerpc/platforms/powernv/vas.h > b/arch/powerpc/platforms/powernv/vas.h > new file mode 100644 > index 000..c66aaf0 > --- /dev/null > +++ b/arch/powerpc/platforms/powernv/vas.h > @@ -0,0 +1,385 @@ ... > + > +/* > +

Re: [PATCH v2 00/20] Speculative page faults

On 21/08/2017 08:28, Anshuman Khandual wrote: > On 08/18/2017 03:34 AM, Laurent Dufour wrote: >> This is a port on kernel 4.13 of the work done by Peter Zijlstra to >> handle page fault without holding the mm semaphore [1]. >> >> The idea is to try to handle user space page faults without holding

Re: [PATCH v7 08/12] powerpc/vas: Define vas_win_id()

Sukadev Bhattiprolu writes: > Define an interface to return a system-wide unique id for a given VAS > window. > > The vas_win_id() will be used in a follow-on patch to generate an unique > handle for a user space receive window. Applications can use this handle > to

Re: [PATCH v7 07/12] powerpc/vas: Define vas_win_paste_addr()

Sukadev Bhattiprolu writes: > Define an interface that the NX drivers can use to find the physical > paste address of a send window. This interface is expected to be used > with the mmap() operation of the NX driver's device. i.e the user space > process can use

Re: [PATCH v7 06/12] powerpc/vas: Define helpers to alloc/free windows

Sukadev Bhattiprolu writes: > diff --git a/arch/powerpc/platforms/powernv/vas-window.c > b/arch/powerpc/platforms/powernv/vas-window.c > index 3a50d6a..9c12919 100644 > --- a/arch/powerpc/platforms/powernv/vas-window.c > +++

Re: [PATCH v7 05/12] powerpc/vas: Define helpers to init window context

Sukadev Bhattiprolu writes: > diff --git a/arch/powerpc/platforms/powernv/vas-window.c > b/arch/powerpc/platforms/powernv/vas-window.c > index a3a705a..3a50d6a 100644 > --- a/arch/powerpc/platforms/powernv/vas-window.c > +++

Re: [PATCH v2 18/20] perf tools: Add support for the SPF perf event

On 21/08/2017 10:48, Anshuman Khandual wrote: > On 08/18/2017 03:35 AM, Laurent Dufour wrote: >> Add support for the new speculative faults event. >> >> Signed-off-by: Laurent Dufour >> --- >> tools/include/uapi/linux/perf_event.h | 1 + >> tools/perf/util/evsel.c

Re: [PATCH v2 14/20] mm: Provide speculative fault infrastructure

On 20/08/2017 14:11, Sergey Senozhatsky wrote: > On (08/18/17 00:05), Laurent Dufour wrote: > [..] >> +/* >> + * MPOL_INTERLEAVE implies additional check in mpol_misplaced() which >> + * are not compatible with the speculative page fault processing. >> + */ >> +pol =

Re: [PATCH 5/6] powerpc/mm: Optimize detection of thread local mm's

Le 25/08/2017 à 09:44, Benjamin Herrenschmidt a écrit : On Fri, 2017-08-25 at 06:53 +0200, Frederic Barrat wrote: Le 24/08/2017 à 20:47, Benjamin Herrenschmidt a écrit : On Thu, 2017-08-24 at 18:40 +0200, Frederic Barrat wrote: The decrementing part is giving me troubles, and I think it

Re: [PATCH 5/6] powerpc/mm: Optimize detection of thread local mm's

On Fri, 2017-08-25 at 06:53 +0200, Frederic Barrat wrote: > > Le 24/08/2017 à 20:47, Benjamin Herrenschmidt a écrit : > > On Thu, 2017-08-24 at 18:40 +0200, Frederic Barrat wrote: > > > > > > The decrementing part is giving me troubles, and I think it makes sense: > > > if I decrement the

[PATCH v2 09/10] powerpc: Handle opposite-endian processes in emulation code

This adds code to the load and store emulation code to byte-swap the data appropriately when the process being emulated is set to the opposite endianness to that of the kernel. This also enables the emulation for the multiple-register loads and stores (lmw, stmw, lswi, stswi, lswx, stswx) to work

[PATCH v2 10/10] powerpc/64: Fix update forms of loads and stores to write 64-bit EA

When a 64-bit processor is executing in 32-bit mode, the update forms of load and store instructions are required by the architecture to write the full 64-bit effective address into the RA register, though only the bottom 32 bits are used to address memory. Currently, the instruction emulation

[PATCH v2 08/10] powerpc: Emulate load/store floating double pair instructions

This adds lfdp[x] and stfdp[x] to the set of instructions that analyse_instr() and emulate_step() understand. Signed-off-by: Paul Mackerras --- arch/powerpc/lib/sstep.c | 76 ++-- 1 file changed, 60 insertions(+), 16 deletions(-)

[PATCH v2 07/10] powerpc: Handle vector element load/stores in emulation code

This adds code to analyse_instr() and emulate_step() to handle the vector element loads and stores: lvebx, lvehx, lvewx, stvebx, stvehx, stvewx. Signed-off-by: Paul Mackerras --- arch/powerpc/lib/sstep.c | 50 ++-- 1 file changed,

[PATCH v2 06/10] powerpc: Emulate FP/vector/VSX loads/stores correctly when regs not live

At present, the analyse_instr/emulate_step code checks for the relevant MSR_FP/VEC/VSX bit being set when a FP/VMX/VSX load or store is decoded, but doesn't recheck the bit before reading or writing the relevant FP/VMX/VSX register in emulate_step(). Since we don't have preemption disabled, it is

[PATCH v2 05/10] powerpc: Make load/store emulation use larger memory accesses

At the moment, emulation of loads and stores of up to 8 bytes to unaligned addresses on a little-endian system uses a sequence of single-byte loads or stores to memory. This is rather inefficient, and the code is hard to follow because it has many ifdefs. In addition, the Power ISA has

[PATCH v2 04/10] powerpc: Add emulation for the addpcis instruction

The addpcis instruction puts the sum of the next instruction address plus a constant into a register. Since the result depends on the address of the instruction, it will give an incorrect result if it is single-stepped out of line, which is what the *probes subsystem will currently do if a probe

[PATCH v2 03/10] powerpc: Fix emulation of the isel instruction

The case added for the isel instruction was added inside a switch statement which uses the 10-bit minor opcode field in the 0x7fe bits of the instruction word. However, for the isel instruction, the minor opcode field is only the 0x3e bits, and the 0x7c0 bits are used for the "BC" field, which

[PATCH v2 02/10] powerpc: Change analyse_instr so it doesn't modify *regs

The analyse_instr function currently doesn't just work out what an instruction does, it also executes those instructions whose effect is only to update CPU registers that are stored in struct pt_regs. This is undesirable because optprobes uses analyse_instr to work out if an instruction could be

[PATCH v2 01/10] powerpc: Handle most loads and stores in instruction emulation code

This extends the instruction emulation infrastructure in sstep.c to handle all the load and store instructions defined in the Power ISA v3.0, except for the atomic memory operations, ldmx (which was never implemented), lfdp/stfdp, and the vector element load/stores. The instructions added are:

[PATCH v2 0/10] powerpc: Beef up single-stepping/instruction emulation infrastructure

This patch series extends the code in arch/powerpc/lib/sstep.c so that it handles almost all load and store instructions -- all except the atomic memory operations (lwat, stwat, etc.). It also makes sure that we use the largest possible aligned accesses to access memory and that we don't access