Hi All,
Thanks a lot for your replies.
@NXP developers: Could you please tell us some information?
Thanks,
Christian
On 08 January 2018 at 02:14AM, Michal Suchanek wrote:
On 7 January 2018 at 19:54, Olof Johansson wrote:
On Sun, Jan 7, 2018 at 5:04 AM, Christian Zigotzky
wrote:
Hello Mic
On Sat, Jan 06, 2018 at 10:28:00AM +1100, Michael Ellerman wrote:
> Bharata B Rao writes:
>
> > Currently device tree nodes for memory are scanned before the
> > radix feature is discovered in mmu_early_init_devtree(). Move this
> > routine ahead of scanning memory nodes so that we know if the
>
Any chance to get this fully reviewed and picked up before the
end of the merge window?
The patch
ASoC: fsl_ssi: Fix build error
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
t
On Fri, Jan 5, 2018 at 2:35 AM, Christophe Leroy
wrote:
> This patch restores the alphabetic order which was broken by
> commit 1e0fc9d1eb2b0 ("powerpc/Kconfig: Enable STRICT_KERNEL_RWX
> for some configs")
>
> Fixes: 1e0fc9d1eb2b0 ("powerpc/Kconfig: Enable STRICT_KERNEL_RWX for some
> configs")
An application running with libhugetlbfs fails to allocate
additional pages to HEAP due to the hugemap being done
inconditionally as topdown mapping:
mmap(0x1008, 1572864, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_ANONYMOUS|0x4, -1, 0) = 0x73e8
[...]
mmap(0x7400, 1048576, PROT_READ|PR
Le 22/12/2017 à 13:36, Philippe Bergheaud a écrit :
P9 supports PCI tunneled operations (atomics and as_notify). This
patch adds support for tunneled operations on powernv, with a new
API, to be called by device drivers:
pnv_pci_get_tunnel_ind()
Tell driver the 16-bit ASN indication used b
Le 22/12/2017 à 13:36, Philippe Bergheaud a écrit :
+#ifdef CONFIG_PPC64/* for thread.tidr */
+int pnv_pci_get_as_notify_info(struct task_struct *task, u32 *lpid, u32 *pid,
+ u32 *tid)
+{
+ struct mm_struct *mm = NULL;
+
+ if (task == NULL)
+
Le 22/12/2017 à 13:36, Philippe Bergheaud a écrit :
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications"
From: Michael Neuling
A new hypervisor call has been defined to communicate various
characteristics of the CPU to guests. Add definitions for the hcall
number, flags and a wrapper function.
Signed-off-by: Michael Neuling
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/hvcall.h
From: Nicholas Piggin
The rfid/hrfid ((Hypervisor) Return From Interrupt) instruction is
used for switching from the kernel to userspace, and from the
hypervisor to the guest kernel. However it can and is also used for
other transitions, eg. from real mode kernel code to virtual mode
kernel code,
From: Nicholas Piggin
This commit does simple conversions of rfi/rfid to the new macros that
include the expected destination context. By simple we mean cases
where there is a single well known destination context, and it's
simply a matter of substituting the instruction for the appropriate
macro
From: Nicholas Piggin
In the syscall exit path we may be returning to user or kernel
context. We already have a test for that, because we conditionally
restore r13. So use that existing test and branch, and bifurcate the
return based on that.
Signed-off-by: Nicholas Piggin
Signed-off-by: Michae
From: Nicholas Piggin
Similar to the syscall return path, in fast_exception_return we may be
returning to user or kernel context. We already have a test for that,
because we conditionally restore r13. So use that existing test and
branch, and bifurcate the return based on that.
Signed-off-by: Ni
On some CPUs we can prevent the Meltdown vulnerability by flushing the
L1-D cache on exit from kernel to user mode, and from hypervisor to
guest.
This is known to be the case on at least Power7, Power8 and Power9. At
this time we do not know the status of the vulnerability on other CPUs
such as th
From: Nicholas Piggin
Expose the state of the RFI flush (enabled/disabled) via sysfs, and
allow it to be enabled/dissabled at runtime.
Signed-off-by: Nicholas Piggin
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/setup.h | 2 ++
arch/powerpc/kernel/sysfs.c | 41 +
From: Nicholas Piggin
In the SLB miss handler we may be returning to user or kernel. We need
to add a check early on and save the result in the cr4 register, and
then we bifurcate the return path based on that.
Signed-off-by: Nicholas Piggin
Signed-off-by: Michael Ellerman
---
arch/powerpc/ke
Because there may be some performance overhead of the RFI flush, add
kernel command line options to disable it.
We add a sensibly named 'no_rfi_flush' option, but we also hijack the
x86 option 'nopti'. The RFI flush is not the same as KPTI, but if we
see 'nopti' we can guess that the user is tryin
From: Michael Neuling
A new hypervisor call is available which tells the guest settings
related to the RFI flush. Use it to query the appropriate flush
instruction(s), and whether the flush is required.
Signed-off-by: Michael Neuling
Signed-off-by: Michael Ellerman
---
arch/powerpc/platforms/
From: Oliver O'Halloran
New device-tree properties are available which tell the hypervisor
settings related to the RFI flush. Use them to determine the
appropriate flush instruction to use, and whether the flush is
required.
Signed-off-by: Oliver O'Halloran
Signed-off-by: Michael Ellerman
---
> On Jan 7, 2018, at 1:36 PM, Matthew R. Ochs wrote:
>
> On Thu, Jan 04, 2018 at 05:33:48PM +1100, Andrew Donnellan wrote:
>> On 04/01/18 09:54, Uma Krishnan wrote:
>>> In the event of a command failure, cxlflash returns the failure to the
>>> upper layers to process. After processing the error,
On Tue, Jan 09, 2018 at 03:54:45AM +1100, Michael Ellerman wrote:
> diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S
> b/arch/powerpc/kvm/book3s_rmhandlers.S
> index 42a4b237df5f..34a5adeff084 100644
> --- a/arch/powerpc/kvm/book3s_rmhandlers.S
> +++ b/arch/powerpc/kvm/book3s_rmhandlers.S
> @@ -4
Add code to parse the new property 'ibm,thread-groups" when it is
present. The content of this property explicitly defines the number
of threads per core as well as the PowerPC 'threads_core_mask'.
The design provides a common device-tree for both P9 normal core and
P9 fused core systems. The new
On Tue, 9 Jan 2018, Michael Ellerman wrote:
Sorry, I wasn't aware about your efforts and did not cc you. I've just
queued a more generic sysfs interface for this whole mess:
https://lkml.kernel.org/r/20180107214913.096657...@linutronix.de
It should be simple to extend for write and it would be g
The migration of LPARs across Power systems affects many attributes
including that of the associativity of memory blocks and CPUs. The
patches in this set execute when a system is coming up fresh upon a
migration target. They are intended to,
* Recognize changes to the associativity of memory an
hotplug/mobility: Recognize more changes to the associativity of
memory blocks described by the 'ibm,dynamic-memory' and 'cpu'
properties when processing the topology of LPARS in Post Migration
events. Previous efforts only recognized whether a memory block's
assignment had changed in the property
postmigration/memory: In an LPAR migration scenario, the property
"ibm,associativity-lookup-arrays" may change. In the event that a
row of the array differs, locate all assigned memory blocks with that
'aa_index' and 're-add' them to the system memory block data structures.
In the process of the '
postmigration/memory: Now apply changes to the associativity of memory
blocks described by the 'ibm,dynamic-memory-v2' property regarding
the topology of LPARS in Post Migration events.
* Extend the previous work done for the 'ibm,associativity-lookup-array'
to apply to either property 'ibm,dyna
From: Michael Ellerman
Date: Mon, 08 Jan 2018 14:26:12 +1100
> I don't see it in rc7, will it get to Linus sometime before the
> release?
I will do what I can to make sure it does, it is in my GIT tree.
Hi Michael,
I hadn't seen any update on this patch, just wanted to make sure you saw it.
-Nathan
On 12/05/2017 09:33 PM, Nathan Fontenot wrote:
> When DLPAR removing a CPU we need to invalidate its entry in the
> numa_cpu_lookup_table. There is no guarantee that on a subsequent
> DLPAR add of
This patch implements MMIO emulation for two instructions: lvx and stvx.
NOTE: I'm resending copying now kvm-...@vger.kernel.org.
Thanks.
Jose Ricardo Ziviani (1):
KVM: PPC: Book3S: Add MMIO emulation for VMX instructions
arch/powerpc/include/asm/kvm_host.h | 2 +
arch/powerpc/include/as
This patch provides the MMIO load/store vector indexed
X-Form emulation.
Instructions implemented: lvx, stvx
Signed-off-by: Jose Ricardo Ziviani
---
arch/powerpc/include/asm/kvm_host.h | 2 +
arch/powerpc/include/asm/kvm_ppc.h| 4 +
arch/powerpc/include/asm/ppc-opcode.h | 6 ++
arch
On 11/28/2017 04:58 PM, Michael Bringmann wrote:
> On powerpc systems which allow 'hot-add' of CPU or memory resources,
> it may occur that the new resources are to be inserted into nodes
> that were not used for these resources at bootup. In the kernel,
> any node that is used must be defined and
On 11/28/2017 04:58 PM, Michael Bringmann wrote:
> On powerpc systems which allow 'hot-add' of CPU, it may occur that
> the new resources are to be inserted into nodes that were not used
> for memory resources at bootup. Many different configurations of
> PowerPC resources may need to be supported
On 11/28/2017 04:58 PM, Michael Bringmann wrote:
> On powerpc systems with shared configurations of CPUs and memory and
> memoryless nodes at boot, an event ordering problem was observed on
> a SLES12 build platforms with the hot-add of CPUs to the memoryless
> nodes.
>
> * The most common error o
On Mon, Jan 8, 2018 at 3:26 AM, Christoph Hellwig wrote:
> Any chance to get this fully reviewed and picked up before the
> end of the merge window?
I'm fine carrying these through the nvdimm tree, but I'd need an ack
from the mm folks for all the code touches related to arch_add_memory.
On Mon 08-01-18 11:44:02, Dan Williams wrote:
> On Mon, Jan 8, 2018 at 3:26 AM, Christoph Hellwig wrote:
> > Any chance to get this fully reviewed and picked up before the
> > end of the merge window?
>
> I'm fine carrying these through the nvdimm tree, but I'd need an ack
> from the mm folks for
On Jan 7, 2018, at 1:36 PM, Matthew R. Ochs wrote:On Thu, Jan 04, 2018 at 05:33:48PM +1100, Andrew Donnellan wrote:On 04/01/18 09:54, Uma Krishnan wrote:In the event of a command failure, cxlflash returns the failure to theupper layers to process. After processing the error, when the command isque
The migration of LPARs across Power systems affects many attributes
including that of the associativity of memory blocks and CPUs. The
patches in this set execute when a system is coming up fresh upon a
migration target. They are intended to,
* Recognize changes to the associativity of memory an
hotplug/mobility: Recognize more changes to the associativity of
memory blocks described by the 'ibm,dynamic-memory' and 'cpu'
properties when processing the topology of LPARS in Post Migration
events. Previous efforts only recognized whether a memory block's
assignment had changed in the property
postmigration/memory: In an LPAR migration scenario, the property
"ibm,associativity-lookup-arrays" may change. In the event that a
row of the array differs, locate all assigned memory blocks with that
'aa_index' and 're-add' them to the system memory block data structures.
In the process of the '
postmigration/memory: Now apply changes to the associativity of memory
blocks described by the 'ibm,dynamic-memory-v2' property regarding
the topology of LPARS in Post Migration events.
* Extend the previous work done for the 'ibm,associativity-lookup-array'
to apply to either property 'ibm,dyna
On Mon, Jan 08, 2018 at 06:09:51PM +0100, Peter Zijlstra wrote:
> On Tue, Jan 09, 2018 at 03:54:45AM +1100, Michael Ellerman wrote:
> > diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S
> > b/arch/powerpc/kvm/book3s_rmhandlers.S
> > index 42a4b237df5f..34a5adeff084 100644
> > --- a/arch/powerpc/kv
On Mon, Jan 8, 2018 at 12:25 PM, Michal Hocko wrote:
> On Mon 08-01-18 11:44:02, Dan Williams wrote:
>> On Mon, Jan 8, 2018 at 3:26 AM, Christoph Hellwig wrote:
>> > Any chance to get this fully reviewed and picked up before the
>> > end of the merge window?
>>
>> I'm fine carrying these through
On Mon 08-01-18 13:27:13, Dan Williams wrote:
> On Mon, Jan 8, 2018 at 12:25 PM, Michal Hocko wrote:
> > On Mon 08-01-18 11:44:02, Dan Williams wrote:
> >> On Mon, Jan 8, 2018 at 3:26 AM, Christoph Hellwig wrote:
> >> > Any chance to get this fully reviewed and picked up before the
> >> > end of
On 01/08/2018 08:54 AM, Michael Ellerman wrote:
> From: Oliver O'Halloran
>
> New device-tree properties are available which tell the hypervisor
> settings related to the RFI flush. Use them to determine the
> appropriate flush instruction to use, and whether the flush is
> required.
>
> Signed-
Paul Mackerras writes:
> On Mon, Jan 08, 2018 at 06:09:51PM +0100, Peter Zijlstra wrote:
>> On Tue, Jan 09, 2018 at 03:54:45AM +1100, Michael Ellerman wrote:
>> > diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S
>> > b/arch/powerpc/kvm/book3s_rmhandlers.S
>> > index 42a4b237df5f..34a5adeff084 1
Thomas Gleixner writes:
> On Tue, 9 Jan 2018, Michael Ellerman wrote:
>
> Sorry, I wasn't aware about your efforts and did not cc you. I've just
> queued a more generic sysfs interface for this whole mess:
No worries.
> https://lkml.kernel.org/r/20180107214913.096657...@linutronix.de
>
> It sho
This fixes migration on POWER9 machines, especially when migration
starts within first 10 seconds after the guest start.
Signed-off-by: Alexey Kardashevskiy
---
This is a reminder that the problem exists, a proper patch and
commit log are still needed. The "(old & PATB_HR)" was tested but
not th
On Fri, Dec 29, 2017 at 09:18:10AM +0100, Christoph Hellwig wrote:
> Signed-off-by: Christoph Hellwig
> ---
> arch/hexagon/include/asm/io.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/arch/hexagon/include/asm/io.h b/arch/hexagon/include/asm/io.h
> index 66f5e9a61efc..9e8621d94ee9 1
Uma,
> This patch series contains miscellaneous fixes. The first patch fixes
> a bug while the rest improve the code structure and prepare the code
> for future enhancements.
Added stable tag to first patch and applied series to
4.16/scsi-queue. Thank you!
--
Martin K. Petersen Oracle Lin
This adds three new capabilities that give userspace information about
the underlying machine's level of vulnerability to the Meltdown and
Spectre attacks, and what instructions the hardware implements to
assist software to work around the vulnerabilities.
Each capability is a tri-state, where 0 i
Currently the pseries kernel advertises radix MMU support even if
the actual support is disabled via the CONFIG_PPC_RADIX_MMU option.
This adds a check for CONFIG_PPC_RADIX_MMU to avoid advertising radix
to the hypervisor.
Suggested-by: Paul Mackerras
Signed-off-by: Alexey Kardashevskiy
---
ar
With enabled DEBUG, there is a compile error:
"error: ‘flags’ is used uninitialized in this function".
This moves pr_devel() little further where @flags are initialized.
Signed-off-by: Alexey Kardashevskiy
---
/home/aik/p/guest-kernel/arch/powerpc/platforms/pseries/lpar.c: In function
‘pSeries
The pnv_get_proc_freq() function was recently changed to call
cpufreq_get(), instead of cpufreq_quick_get(), in order to fetch
a more up-to-date value for the CPU frequency:
cd77b5ce208c153260ed7882d8910f2395bfaabd
powerpc/powernv/cpufreq: Fix the frequency read by /proc/cpuinfo
Unfortunate
On 01/08/2018 11:54 AM, Michael Ellerman wrote:
> On some CPUs we can prevent the Meltdown vulnerability by flushing the
> L1-D cache on exit from kernel to user mode, and from hypervisor to
> guest.
I've tested multiple iterations of these patches over the past few
weeks, on both real hardware, a
On 01/08/2018 05:09 PM, Michael Ellerman wrote:
> Thomas Gleixner writes:
>
>> On Tue, 9 Jan 2018, Michael Ellerman wrote:
>>
>> Sorry, I wasn't aware about your efforts and did not cc you. I've just
>> queued a more generic sysfs interface for this whole mess:
>
> No worries.
>
>> https://lkml
Instead of just telling GCC that dcbz(), dcbi(), dcbf() and dcbst()
clobber memory, tell it what it clobbers:
* dcbz(), dcbi() and dcbf() clobbers one cacheline as output
* dcbf() and dcbst() clobbers one cacheline as input
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/cache.h | 1
On Mon, Jan 8, 2018 at 8:54 AM, Michael Ellerman wrote:
> On some CPUs we can prevent the Meltdown vulnerability by flushing the
> L1-D cache on exit from kernel to user mode, and from hypervisor to
> guest.
Super minor nitpicks below. Don't let this hold up your work.
> --- a/arch/powerpc/kerne
On Mon, 2018-01-08 at 21:30 -0800, John Sperbeck wrote:
> The pnv_get_proc_freq() function was recently changed to call
> cpufreq_get(), instead of cpufreq_quick_get(), in order to fetch
> a more up-to-date value for the CPU frequency:
>
>cd77b5ce208c153260ed7882d8910f2395bfaabd
>powerpc/p
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