Greetings,
Todays mainline kernel has Oops messages for memory hot-unplug
operation.
Machine: Power 8 bare-metal
Kernel: 4.15.0
Config: attached
gcc: 4.8.5
Test: Memory hot-unplug
echo offline > /sys/devices/system/memory/memory/state
the above command triggered 2 kernel Oops messages and the
Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper")
replaced of_irq_parse_pci() + irq_create_of_mapping() with
of_irq_parse_and_map_pci() but this change lost virq returned by
irq_create_of_mapping() so virq remained zero causing INTx
misconfiguration.
This fixes
Alexey Kardashevskiy writes:
> Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper")
> replaced of_irq_parse_pci() + irq_create_of_mapping() with
> of_irq_parse_and_map_pci() but this change lost virq returned by
> irq_create_of_mapping() so virq remained
Alexey Kardashevskiy writes:
> On 09/02/18 15:00, Michael Ellerman wrote:
>> On Thu, 2018-02-08 at 05:33:54 UTC, Alexey Kardashevskiy wrote:
>>> Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper")
>>> correctly states that of_irq_parse_and_map_pci() does
We introduce a new function named cxl_start_trace_psl9() that starts
the various trace-arrays available on PSL9. The implementation
configures trace-array-units(TAU) via multiple writes to the
PSL_TRACECFG register and uses the defaults (data-bus, trigger-bus &
trigger-masks) provided by the h/w
We introduce a new module parameter named 'enable_psltrace' which asks cxl
to start(by default) psl-traces on an adapter as soon as its probe is
finished. In case this default behavior is not needed then this
module parameter can be set to '0'.
Signed-off-by: Vaibhav Jain
We introduce a new enum named cxl_psl9_traceid that represents
individual trace-arrays available on PSL9. In addition a set of new
defines named s CXL_PSL9_TRACESTATE_XXX are introduced that represent
various states a trace-array can be in. Value of each define is the
value reported by PSL_CTCCFG
This patch-set updates the cxl adapter probe procedure to selectively enable
PSL-traces at the end of a successful probe for a PSL9 based adapter. This would
let implementors of AFUs that use in-kernel apis to interact with the CXL
adapter get early debug data.
This feature is controlled via a
On 09/02/18 15:00, Michael Ellerman wrote:
> On Thu, 2018-02-08 at 05:33:54 UTC, Alexey Kardashevskiy wrote:
>> Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper")
>> correctly states that of_irq_parse_and_map_pci() does the same thing as
>> of_irq_parse_pci() does as it
For PSL9 the time-base enable bit has moved from PSL_TB_CTLSTAT
register to PSL_CONTROL register. Hence we don't need an sl_ops
implementation for 'write_timebase_ctrl' for PSL9.
Hence this patch removes function write_timebase_ctrl_psl9() and its
references from the code.
Signed-off-by: Vaibhav
We enable the NORST bit by default for debug afu images to prevent
reset of AFU trace-data on a PCI link drop. For production AFU images
this bit is always ignored and PSL gets reconfigured anyways thereby
resetting the trace data. So setting this bit for non-debug images
doesn't have any impact.
On Thu, 2018-02-08 at 05:33:54 UTC, Alexey Kardashevskiy wrote:
> Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper")
> correctly states that of_irq_parse_and_map_pci() does the same thing as
> of_irq_parse_pci() does as it simply calls
> of_irq_parse_pci() and
On Wed, 2018-02-07 at 06:35:51 UTC, Balbir Singh wrote:
> This patch splits the a linear mapping if the hot-unplug range
> is smaller than the mapping size. The code detects if the mapping
> needs to be split into a smaller size and if so, uses the stop
> machine infrastructure to map the current
On Wed, 2018-02-07 at 01:20:02 UTC, Nicholas Piggin wrote:
> This change restores and formalises the behaviour that access to NULL or
> other user addresses by the kernel during boot should fault rather than
> succeed and modify memory. This was inadvertently broken when fixing
> another bug,
On Tue, 2018-02-06 at 12:36:37 UTC, Madhavan Srinivasan wrote:
> Commit f14e953b191f ("powerpc/64s: Add support to take additional parameter
> in MASKABLE_* macro")
> messed up MASKABLE_RELON_EXCEPTION_HV_OOL macro by adding the wrong
> __SOFTEN__ test which caused guest kernel trash at boot.
On Sat, 2018-02-03 at 07:17:50 UTC, Nicholas Piggin wrote:
> The soft IRQ masking code has to hard-disable interrupts in cases
> where the exception is not cleared by the masked handler. External
> interrupts used this approach for soft masking. Now recently PMU
> interrupts do the same thing.
>
On Tue, 2018-01-30 at 15:11:44 UTC, Colin King wrote:
> From: Colin Ian King
>
> Currently the comparison of used < 0 is always false because
> uses is a size_t. Fix this by making used a ssize_t type.
>
> Detected by Coccinelle:
> drivers/misc/ocxl/file.c:320:6-10:
On Fri, 2018-01-26 at 19:41:59 UTC, Nathan Fontenot wrote:
> When DLPAR removing a CPU, the unmapping of the cpu from a node in
> unmap_cpu_from_node() should also invalidate the CPUs entry in the
> numa_cpu_lookup_table. There is not a guarantee that on a subsequent
> DLPAR add of the CPU the
Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper")
replaced of_irq_parse_pci() + irq_create_of_mapping() with
of_irq_parse_and_map_pci() but this change lost virq returned by
irq_create_of_mapping() so virq remained zero causing INTx
misconfiguration.
This fixes
On Thu, 2018-02-08 at 16:42 -0600, Bjorn Helgaas wrote:
> On Fri, Feb 09, 2018 at 09:21:43AM +1100, Benjamin Herrenschmidt wrote:
> > On Thu, 2018-02-08 at 15:39 -0600, Bjorn Helgaas wrote:
> > > I don't understand how this fix works. We used to check the result of
> > >
On Fri, Feb 09, 2018 at 09:21:43AM +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2018-02-08 at 15:39 -0600, Bjorn Helgaas wrote:
> > I don't understand how this fix works. We used to check the result of
> > of_irq_parse_and_map_pci() and entered the block if it was zero.
> >
> > Now you enter
On Thu, 2018-02-08 at 15:39 -0600, Bjorn Helgaas wrote:
> I don't understand how this fix works. We used to check the result of
> of_irq_parse_and_map_pci() and entered the block if it was zero.
>
> Now you enter the block if it is zero or less than zero, but:
>
> static int
On Thu, Feb 08, 2018 at 01:20:04PM -0600, Bjorn Helgaas wrote:
> [+cc linux-pci]
>
> The original commit was merged via PCI, and I think it's a good idea
> to merge fixes to it the same way. I'll try to merge this in time for
> v4.16-rc1.
>
> On Wed, Feb 7, 2018 at 11:33 PM, Alexey
On Tue, 6 Feb 2018 17:49:46 +0100 Laurent Dufour
wrote:
> This is a port on kernel 4.15 of the work done by Peter Zijlstra to
> handle page fault without holding the mm semaphore [1].
>
> The idea is to try to handle user space page faults without holding the
>
On Wed, Feb 7, 2018 at 11:33 PM, Alexey Kardashevskiy wrote:
> Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper")
> correctly states that of_irq_parse_and_map_pci() does the same thing as
> of_irq_parse_pci() does as it simply calls
> of_irq_parse_pci() and
On Thu, Feb 08, 2018 at 08:46:27PM +0530, Aneesh Kumar K.V wrote:
> "Aneesh Kumar K.V" writes:
>
> > To support memory keys, we moved the hash pte slot information to the second
> > half of the page table. This was ok with PTE entries at level 4 and level 3.
> >
On Thu, Feb 08, 2018 at 04:04:41PM +0530, Aneesh Kumar K.V wrote:
> To support memory keys, we moved the hash pte slot information to the second
> half of the page table. This was ok with PTE entries at level 4 and level 3.
> We already allocate larger page table pages at those level to accomodate
[+cc linux-pci]
The original commit was merged via PCI, and I think it's a good idea
to merge fixes to it the same way. I'll try to merge this in time for
v4.16-rc1.
On Wed, Feb 7, 2018 at 11:33 PM, Alexey Kardashevskiy wrote:
> Commit 59f47eff03a0 ("powerpc/pci: Use
Alexei Starovoitov wrote:
On 2/8/18 4:03 AM, Sandipan Das wrote:
The imm field of a bpf_insn is a signed 32-bit integer. For
JIT-ed bpf-to-bpf function calls, it stores the offset from
__bpf_call_base to the start of the callee function.
For some architectures, such as powerpc64, it was found
We ended up with code that did a conditional branch inside a feature
section to code outside of the feature section. Depending on how the
object file gets organized, that might mean we exceed the 14bit
relocation limit for conditional branches:
On 2/8/18 4:03 AM, Sandipan Das wrote:
The imm field of a bpf_insn is a signed 32-bit integer. For
JIT-ed bpf-to-bpf function calls, it stores the offset from
__bpf_call_base to the start of the callee function.
For some architectures, such as powerpc64, it was found that
this offset may be as
On 08/02/2018 16:00, Matthew Wilcox wrote:
> On Thu, Feb 08, 2018 at 03:35:58PM +0100, Laurent Dufour wrote:
>> I reviewed that part of code, and I think I could now change the way
>> pte_unmap_safe() is checking for the pte's value. Since we now have all the
>> needed details in the vm_fault
"Aneesh Kumar K.V" writes:
> To support memory keys, we moved the hash pte slot information to the second
> half of the page table. This was ok with PTE entries at level 4 and level 3.
> We already allocate larger page table pages at those level to accomodate
On 2/8/18 6:20 AM, Michael Ellerman wrote:
> There's no reason pci_uevent_ers() needs to be inline in pci.h, so
> move it out to a C file.
>
> Given it's used by AER the obvious location would be somewhere in
> drivers/pci/pcie/aer, but because it's also used by powerpc EEH code
> unfortunately
On Thu, Feb 08, 2018 at 03:35:58PM +0100, Laurent Dufour wrote:
> I reviewed that part of code, and I think I could now change the way
> pte_unmap_safe() is checking for the pte's value. Since we now have all the
> needed details in the vm_fault structure, I will pass it to
> pte_unamp_same() and
On 06/02/2018 21:28, Matthew Wilcox wrote:
> On Tue, Feb 06, 2018 at 05:49:50PM +0100, Laurent Dufour wrote:
>> From: Peter Zijlstra
>>
>> One of the side effects of speculating on faults (without holding
>> mmap_sem) is that we can race with free_pgtables() and therefore we
There's no reason pci_uevent_ers() needs to be inline in pci.h, so
move it out to a C file.
Given it's used by AER the obvious location would be somewhere in
drivers/pci/pcie/aer, but because it's also used by powerpc EEH code
unfortunately that doesn't work in the case where EEH is enabled but
This adds support for bpf-to-bpf function calls for the powerpc64
JIT compiler. After a round of the usual JIT passes, the offsets
to callee functions from __bpf_call_base are known. To update the
target addresses for the branch instructions associated with each
BPF_CALL, an extra pass is
The imm field of a bpf_insn is a signed 32-bit integer. For
JIT-ed bpf-to-bpf function calls, it stores the offset from
__bpf_call_base to the start of the callee function.
For some architectures, such as powerpc64, it was found that
this offset may be as large as 64 bits because of which this
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
arch/powerpc/include/asm/book3s/64/hash.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h
To support memory keys, we moved the hash pte slot information to the second
half of the page table. This was ok with PTE entries at level 4 and level 3.
We already allocate larger page table pages at those level to accomodate extra
details. For level 4 we already have the extra space which was
[Adding some people whom seem relevant but did not get fingered by
get_maintainer.pl]
On 2017-08-03 14:59, Peter Rosin wrote:
> The sanctioned compatible is "nxp,pca9547".
Ping.
Cheers,
Peter
> Signed-off-by: Peter Rosin
> ---
> arch/powerpc/boot/dts/fsl/t104xqds.dtsi | 2 +-
cp_abort is only required or user windows, because kernel context
must not be preempted between a copy/paste pair.
Without this patch, the init task gets used_vas set when it runs
the nx842_powernv_init initcall, which opens windows for kernel
usage.
used_vas is then never cleared anywhere, so
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