On Fri, 2018-03-23 at 16:44 +1100, Michael Neuling wrote:
.../...
> This fixes the problem in the same way the generic PCIe AER code (in
> drivers/pci/pcie/aer/aerdrv_core.c) does. It makes the EEH code hold
> the device_lock() before performing the driver EEH callbacks. This
> ensures either th
On Fri, 2018-03-23 at 10:26 +0530, Aneesh Kumar K.V wrote:
> +#define CPU_FTR_TLBIE_BUG LONG_ASM_CONST(0x2000)
I did ask you to make this CPU_FTR_POWER9_TLBIE_BUG...
Cheers,
Ben
"Aneesh Kumar K.V" writes:
> diff --git a/arch/powerpc/include/asm/cputable.h
> b/arch/powerpc/include/asm/cputable.h
> index a2c5c95882cf..6c151d2e9bd9 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -465,7 +466,7 @@ static inline void cpu_feat
The SLB bad address handler's trap number fixup does not preserve the
low bit that indicates nonvolatile GPRs have not been saved. This
leads save_nvgprs to skip saving them, and subsequent functions and
return from interrupt will think they are saved.
This causes kernel branch-to-garbage debuggin
The current EEH callbacks can race with a driver unbind. This
can result in a backtraces like this:
[7.573055] EEH: Frozen PHB#0-PE#1fc detected
[7.573063] EEH: PE location: S09, PHB location: N/A
[7.573069] CPU: 2 PID: 2312 Comm: kworker/u258:3 Not tainted
4.15.6-openpower1 #2
[
Hi Christophe,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.16-rc6 next-20180322]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
Maintainers, ping? Any comment?
Thanks
On Thu, Mar 15, 2018 at 12:41 PM, Pingfan Liu wrote:
> This topic has a very long history. It comes from Mahesh Salgaonkar
>
> For v3: https://patchwork.ozlabs.org/patch/834860/
> I hope we can acquire it for "kexec -p" soon.
>
> V4->V5:
> improve the [
On POWER9, under some circumstances, a broadcast TLB invalidation might complete
before all previous stores have drained, potentially allowing stale stores from
becoming visible after the invalidation. This works around it by doubling up
those TLB invalidations which was verified by HW to be suffic
No functionality change. Just code movement to ease code changes later
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/tlb-radix.c | 64 ++---
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm
These function are not used in the code. Remove them.
Signed-off-by: Aneesh Kumar K.V
---
.../powerpc/include/asm/book3s/64/tlbflush-radix.h | 3 --
arch/powerpc/mm/tlb-radix.c| 40 --
2 files changed, 43 deletions(-)
diff --git a/arch/powerpc/includ
On Thu, 2018-03-22 at 17:37 +0100, Christophe Lombard wrote:
> The cxl driver cannot disable the interrupt at the device level and has
> to use disable_irq[_nosync] instead.
> To avoid the implementation of the lazy optimisation (the interrupt is
> marked disabled, but the hardware is left unmasked
Due to recent refactoring in EEH in:
commit b9fde58db7e5 ("powerpc/powernv: Rework EEH initialization on
powernv")
a misleading message was seen in the kernel message buffer:
[0.108431] EEH: PowerNV platform initialized
[0.589979] EEH: No capable adapters found
This happened due to the re
On Fri, Mar 23, 2018 at 1:37 AM, Jared Bents
wrote:
> Thank you for the response but unfortunately, it looks like I already
> have that and it is being used. To verify, I commented that out and
> got the failure "dma_direct_alloc_coherent: No suitable zone for pfn
> 0xe". Below is the code f
On Thu, 2018-03-22 at 12:51 -0500, Sinan Kaya wrote:
> On 3/22/2018 8:52 AM, Benjamin Herrenschmidt wrote:
> > > > No, it's not sufficient.
> >
> > Just to clarify ... barrier() is just a compiler barrier, it means the
> > compiler will generate things in the order they are written. This isn't
> >
On Fri, 2018-03-16 at 17:38 -0300, Thiago Jung Bauermann wrote:
> IMA will need to access the digest of the PKCS7 message (as calculated by
> the kernel) before the signature is verified, so introduce
> pkcs7_get_digest() for that purpose.
>
> Also, modify pkcs7_digest() to detect when the digest
> On Mar 22, 2018, at 11:40 AM, Frederic Barrat
> wrote:
>
>
>
> Le 26/02/2018 à 23:21, Uma Krishnan a écrit :
>> A range of PASIDs are used as identifiers for the adapter contexts. These
>> contexts may be destroyed and created randomly. Use an IDR to keep track
>> of contexts that are in u
From: Benjamin Herrenschmidt
On POWER9 the Nest MMU may fail to invalidate some
translations when doing a tlbie "by PID" or "by LPID"
that is targeted at the TLB only and not the page walk
cache.
This works around it by forcing such invalidations to
escalate to RIC=2 (full invalidation of TLB *a
From: Benjamin Herrenschmidt
Currently, when using coprocessors (which use the Nest MMU), we
simply increment the active_cpu count to force all TLB invalidations
to be come broadcast.
Unfortunately, due to an errata in POWER9, we will need to know
more specifically that coprocessors are in use.
Hi Thiago,
On Fri, 2018-03-16 at 17:38 -0300, Thiago Jung Bauermann wrote:
> IMA will need to know the key that signed a given PKCS#7 message, so add
> pkcs7_get_message_sig().
>
> It will also need to verify an already parsed PKCS#7 message. For this
> purpose, add verify_pkcs7_message_sig() whi
On Thu, 22 Mar 2018 19:36:36 +0300 Ilya Smith wrote:
> Current implementation doesn't randomize address returned by mmap.
> All the entropy ends with choosing mmap_base_addr at the process
> creation. After that mmap build very predictable layout of address
> space. It allows to bypass ASLR in ma
Please add changelogs. An explanation of what a "limit on memory
region random shift" is would be nice ;) Why does it exist, why are we
doing this, etc. Surely there's something to be said - at present this
is just a lump of random code?
On Thu, 22 Mar 2018 19:36:37 +0300 Ilya Smith wrote:
> include/linux/mm.h | 16 --
> mm/mmap.c | 164
> +
You'll be wanting to update the documentation.
Documentation/sysctl/kernel.txt and
Documentation/admin-guide/kernel-parame
In commit 14baf4d9c739 ("cxl: Add guest-specific code") the following code
was added:
if (afu->crs_len < 0) {
dev_err(&afu->dev, "Unexpected configuration record size
value\n");
return -EINVAL;
}
However the variable `crs_len` is of type u64 and ca
In commit 9690c1574268 ("powerpc/mm/radix: Fix always false comparison
against MMU_NO_CONTEXT") an issue was discovered where `mm->context.id` was
being truncated to an `unsigned int`, while the PID is actually an
`unsigned long`. Update the earlier patch by fixing one remaining
occurrence. Discove
Some prototypes for weak functions were missing for powerpc specific
functions. Add the missing prototypes to the CONFIG_PCI_IOV block. This
fixes the following three warnings treated as error when using W=1:
arch/powerpc/kernel/pci-common.c:236:17: error: no previous prototype for
‘pcibios_def
Some function prototypes and body for Thermal Assist Units were not in
sync. Update the function definition to match the existing function
declaration found in `setup-common.c`, changing an `int` return type to a
`u32` return type. Move the prototypes to a header file. Fix the following
warnings, t
The header file was missing from the includes. Fix the
following warning, treated as error with W=1:
arch/powerpc/kernel/vecemu.c:260:5: error: no previous prototype for
‘emulate_altivec’ [-Werror=missing-prototypes]
Signed-off-by: Mathieu Malaterre
---
arch/powerpc/kernel/vecemu.c | 1 +
1
The header file was missing from the includes. Fix the
following warning, treated as error with W=1:
arch/powerpc/kernel/pci_32.c:286:6: error: no previous prototype for
‘sys_pciconfig_iobase’ [-Werror=missing-prototypes]
Signed-off-by: Mathieu Malaterre
---
arch/powerpc/kernel/pci_32.c | 1
The header `pmac.h` was not included, leading to the following warnings,
treated as error with W=1:
arch/powerpc/platforms/powermac/time.c:69:13: error: no previous prototype
for ‘pmac_time_init’ [-Werror=missing-prototypes]
arch/powerpc/platforms/powermac/time.c:207:15: error: no previous pr
Add one missing prototype for function rh_dump_blk. Fix warning treated as
error in W=1:
arch/powerpc/lib/rheap.c:740:6: error: no previous prototype for
‘rh_dump_blk’ [-Werror=missing-prototypes]
Signed-off-by: Mathieu Malaterre
---
arch/powerpc/include/asm/rheap.h | 3 +++
1 file changed,
Some functions prototypes were missing for the non-altivec code. Add the
missing prototypes directly in xor_vmx, fix warnings treated as errors with
W=1:
arch/powerpc/lib/xor_vmx_glue.c:18:6: error: no previous prototype for
‘xor_altivec_2’ [-Werror=missing-prototypes]
arch/powerpc/lib/xor_vm
The function prototypes were declared within a `#ifdef CONFIG_PPC_LITE5200`
block which would prevent them from being visible when compiling
`mpc52xx_pm.c`. Move the prototypes outside of the `#ifdef` block to fix
the following warnings treated as errors with W=1:
arch/powerpc/platforms/52xx/mpc
Add a missing prototype for function `note_bootable_part` to silence a
warning treated as error with W=1:
arch/powerpc/platforms/powermac/setup.c:361:12: error: no previous prototype
for ‘note_bootable_part’ [-Werror=missing-prototypes]
Signed-off-by: Mathieu Malaterre
---
arch/powerpc/platf
The pmac_pfunc_base_install prototype was declared in powermac/smp.c since
function was used there, move it to pmac_pfunc.h header to be visible in
pfunc_base.c. Fix a warning treated as error with W=1:
arch/powerpc/platforms/powermac/pfunc_base.c:330:12: error: no previous
prototype for ‘pmac_
Add a missing include .
These functions can all be static, make it so. Fix warnings treated as
errors with W=1:
arch/powerpc/platforms/chrp/time.c:41:13: error: no previous prototype for
‘chrp_time_init’ [-Werror=missing-prototypes]
arch/powerpc/platforms/chrp/time.c:66:5: error: no previous
These functions can all be static, make it so. Fix warnings treated as
errors with W=1:
arch/powerpc/platforms/chrp/pci.c:34:5: error: no previous prototype for
‘gg2_read_config’ [-Werror=missing-prototypes]
arch/powerpc/platforms/chrp/pci.c:61:5: error: no previous prototype for
‘gg2_write_
These functions can all be static, make it so. Fix warnings treated as
errors with W=1:
arch/powerpc/kernel/tau_6xx.c:53:6: error: no previous prototype for
‘set_thresholds’ [-Werror=missing-prototypes]
arch/powerpc/kernel/tau_6xx.c:73:6: error: no previous prototype for
‘TAUupdate’ [-Werror
These functions can all be static, make it so. Fix warnings treated as
errors with W=1:
arch/powerpc/platforms/powermac/pci.c:1022:6: error: no previous prototype
for ‘pmac_pci_fixup_ohci’ [-Werror=missing-prototypes]
arch/powerpc/platforms/powermac/pci.c:1057:6: error: no previous prototype
This function can be static, make it so, this fix a warning treated as
error with W=1:
arch/powerpc/kernel/btext.c:173:5: error: no previous prototype for
‘btext_initialize’ [-Werror=missing-prototypes]
Signed-off-by: Mathieu Malaterre
---
arch/powerpc/kernel/btext.c | 2 +-
1 file changed,
Add gcc attribute unused to silence a warning.
These functions can all be static, make it so. Fix warnings treated as
errors with W=1:
arch/powerpc/platforms/chrp/setup.c:97:6: error: no previous prototype for
‘chrp_show_cpuinfo’ [-Werror=missing-prototypes]
arch/powerpc/platforms/chrp/setup
Add gcc attribute unused to variable tmp. Fix warning treated as error with
W=1:
arch/powerpc/kernel/kvm.c:675:6: error: variable ‘tmp’ set but not used
[-Werror=unused-but-set-variable]
Signed-off-by: Mathieu Malaterre
---
arch/powerpc/kernel/kvm.c | 2 +-
1 file changed, 1 insertion(+), 1
Add gcc attribute unused for two variables. Fix warnings treated as errors
with W=1:
arch/powerpc/kernel/prom_init.c:1388:8: error: variable ‘path’ set but not
used [-Werror=unused-but-set-variable]
Signed-off-by: Mathieu Malaterre
---
arch/powerpc/kernel/prom_init.c | 4 ++--
1 file changed
Since the value of x is never intended to be read, declare it with gcc
attribute as unused. Fix warning treated as error with W=1:
arch/powerpc/platforms/powermac/udbg_scc.c:76:9: error: variable ‘x’ set but
not used [-Werror=unused-but-set-variable]
Signed-off-by: Mathieu Malaterre
---
arch
Since the value of x is never intended to be read, declare it with gcc
attribute as unused. Fix warning treated as error with W=1:
arch/powerpc/platforms/powermac/bootx_init.c:471:21: error: variable ‘x’ set
but not used [-Werror=unused-but-set-variable]
Signed-off-by: Mathieu Malaterre
---
Here is another batch for warnings treated as error on ppc32. Tested with:
$ make ARCH=powerpc ppc32_defconfig
$ make -j8 ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- W=1
Using:
$ powerpc-linux-gnu-gcc --version
powerpc-linux-gnu-gcc (Debian 6.3.0-18) 6.3.0 20170516
Mathieu Malaterre (19):
p
Signed-off-by: Ilya Smith
---
include/linux/mm.h | 16 --
mm/mmap.c | 164 +
2 files changed, 175 insertions(+), 5 deletions(-)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index ad06d42..c716257 100644
--- a/include/linux
Current implementation doesn't randomize address returned by mmap.
All the entropy ends with choosing mmap_base_addr at the process
creation. After that mmap build very predictable layout of address
space. It allows to bypass ASLR in many cases. This patch make
randomization of address on any mmap
Signed-off-by: Ilya Smith
---
arch/alpha/kernel/osf_sys.c | 1 +
arch/arc/mm/mmap.c | 1 +
arch/arm/mm/mmap.c | 2 ++
arch/frv/mm/elf-fdpic.c | 1 +
arch/ia64/kernel/sys_ia64.c | 1 +
arch/ia64/mm/hugetlbpage.c | 1 +
arch/met
On Wed, 21 Mar 2018 15:09:32 -0700
Joe Perches wrote:
> diff --git a/kernel/trace/trace_printk.c b/kernel/trace/trace_printk.c
> index ad1d6164e946..50f44b7b2b32 100644
> --- a/kernel/trace/trace_printk.c
> +++ b/kernel/trace/trace_printk.c
> @@ -196,7 +196,7 @@ struct notifier_block module_trace
On 3/22/2018 8:52 AM, Benjamin Herrenschmidt wrote:
>>> No, it's not sufficient.
> Just to clarify ... barrier() is just a compiler barrier, it means the
> compiler will generate things in the order they are written. This isn't
> sufficient on archs with an OO memory model, where an actual memory
>
Le 26/02/2018 à 23:22, Uma Krishnan a écrit :
After reading and modifying the function configuration, setup the OCXL
link using the OCXL provider services. The link is released when the
adapter is unconfigured.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
Reviewed-by: Frederi
Le 26/02/2018 à 23:22, Uma Krishnan a écrit :
The AFU should be enabled following a successful configuration and
disabled near the end of the cleanup path.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
Reviewed-by: Frederic Barrat
drivers/scsi/cxlflash/ocxl_hw.c | 9 +
Le 26/02/2018 à 23:22, Uma Krishnan a écrit :
When the AFU is configured, the global and per process MMIO regions
are presented by the configuration space. Save these regions and
map the global MMIO region that is used to access all of the control
and provisioning data in the AFU.
Signed-off-b
Le 26/02/2018 à 23:21, Uma Krishnan a écrit :
Allocate a file descriptor for an adapter context when requested. In order
to allocate inodes for the file descriptors, a pseudo filesystem is created
and used.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
We've touched the subjec
Le 26/02/2018 à 23:21, Uma Krishnan a écrit :
A range of PASIDs are used as identifiers for the adapter contexts. These
contexts may be destroyed and created randomly. Use an IDR to keep track
of contexts that are in use and assign a unique identifier to new ones.
Signed-off-by: Uma Krishnan
The cxl driver cannot disable the interrupt at the device level and has
to use disable_irq[_nosync] instead.
To avoid the implementation of the lazy optimisation (the interrupt is
marked disabled, but the hardware is left unmasked), we can disable it,
for a particular irq line, by calling
'irq_set_
Le 26/02/2018 à 23:21, Uma Krishnan a écrit :
Add support to create and release the adapter contexts for OCXL and
provide means to specify certain contexts as a master.
The existing cxlflash core has a design requirement that each host will
have a single host context available by default. To s
Le 26/02/2018 à 23:21, Uma Krishnan a écrit :
Per the OCXL specification, the maximum PASID supported by the AFU is
indicated by a field within the configuration space. Similar to acTags,
implementations can choose to use any sub-range of PASID within their
assigned range. For cxlflash, the ent
Le 26/02/2018 à 23:21, Uma Krishnan a écrit :
The OCXL specification supports distributing acTags amongst different
AFUs and functions on the link. As cxlflash devices are expected to only
support a single AFU and function, the entire range that was assigned to
the function is also assigned to
Le 26/02/2018 à 23:21, Uma Krishnan a écrit :
The host AFU configuration is read on the initialization path to identify
the features and configuration of the AFU. This data is cached for use in
later configuration steps.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scs
Le 26/02/2018 à 23:21, Uma Krishnan a écrit :
The host AFU configuration is read on the initialization path to identify
the features and configuration of the AFU. This data is cached for use in
later configuration steps.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
Reviewed-by
Le 26/02/2018 à 23:20, Uma Krishnan a écrit :
The OCXL specification supports distributing acTags amongst different
AFUs and functions on the link. The platform-specific acTag range for the
link is obtained using the OCXL provider services and then assigned to the
host function based on impleme
Le 26/02/2018 à 23:20, Uma Krishnan a écrit :
Per the OCXL specification, the underlying host can have multiple AFUs
per function with each function supporting its own configuration. The host
function configuration is read on the initialization path to evaluate the
number of functions present a
Thank you for the response but unfortunately, it looks like I already
have that and it is being used. To verify, I commented that out and
got the failure "dma_direct_alloc_coherent: No suitable zone for pfn
0xe". Below is the code flow for function
ath10k_pci_hif_exchange_bmi_msg which is sho
On Thu, 2018-03-22 at 21:15 +1100, Oliver wrote:
> On Thu, Mar 22, 2018 at 3:24 PM, Benjamin Herrenschmidt
> wrote:
> > On Wed, 2018-03-21 at 08:53 -0500, Sinan Kaya wrote:
> > > writel_relaxed() needs to have ordering guarantees with respect to the
> > > order
> > > device observes writes.
> >
Long long post ahead...
I've been playing with rewriting interrupt entry code, this is really
rough patch so far, but it boots mambo. I'll just post it now to get
opinions on the approach.
This implements a new set of exception macros, converts the decrementer
to use them (it's maskable so it cov
"Aneesh Kumar K.V" writes:
> diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
> index fdb424a29f03..63470b06c502 100644
> --- a/arch/powerpc/mm/init_64.c
> +++ b/arch/powerpc/mm/init_64.c
> @@ -68,12 +68,6 @@
>
> #include "mmu_decl.h"
>
> -#ifdef CONFIG_PPC_BOOK3S_64
> -#if
"Aneesh Kumar K.V" writes:
> We need to zero-out pgd table only if we share the slab cache with pud/pmd
> level caches. With the support of 4PB, we don't share the slab cache anymore.
> Instead of removing the code completely hide it within an #ifdef. We don't
> need
> to do this with any other
On Thu, Mar 22, 2018 at 08:25:43PM +1100, Oliver wrote:
> On Thu, Mar 22, 2018 at 7:20 PM, Gabriel Paubert wrote:
> > On Thu, Mar 22, 2018 at 04:24:24PM +1100, Oliver wrote:
> >> On Thu, Mar 22, 2018 at 1:35 AM, David Laight
> >> wrote:
> >> >> x86 has compiler barrier inside the relaxed() API s
On-Chip-Controller(OCC) is an embedded micro-processor in POWER9 chip
which measures various system and chip level sensors. These sensors
comprises of environmental sensors (like power, temperature, current
and voltage) and performance sensors (like utilization, frequency).
All these sensors are co
This patch provides support to disable and enable plaform specific
sensor groups like performance, utilization and frequency.
Signed-off-by: Shilpasri G Bhat
---
.../ABI/testing/sysfs-firmware-opal-sensor-groups | 34 +
.../powerpc/platforms/powernv/opal-sensor-groups.c | 80 +++
Adds support to enable/disable a sensor group at runtime. This
can be used to select the sensor groups that needs to be copied to
main memory by OCC. Sensor groups like power, temperature, current,
voltage, frequency, utilization can be enabled/disabled at runtime.
Signed-off-by: Shilpasri G Bhat
This patch series adds support to enable/disable OCC based
inband-sensor groups at runtime. The environmental sensor groups are
managed in HWMON and the remaining platform specific sensor groups are
managed in /sys/firmware/opal.
The firmware changes required for this patch is posted below:
https:
asm/barrier.h is not always included after asm/synch.h, which meant
it was missing __SUBARCH_HAS_LWSYNC, so in some files smp_wmb() would
be eieio when it should be lwsync. kernel/time/hrtimer.c is one case.
__SUBARCH_HAS_LWSYNC is only used in one place, so just fold it in
to where it's used. Pre
From: Oliver
> Sent: 22 March 2018 05:24
...
> > No less painful was doing a byteswapping write to normal memory.
>
> What was the problem? The reverse indexed load/store instructions are
> a little awkward to use, but they work...
Finding something that would generate the right instruction witho
Our implementation matches that of the generic version, which also
handles FTRACE_UPDATE_MODIFY_CALL. So, remove our implementation in
favor of the generic version.
Signed-off-by: Naveen N. Rao
---
arch/powerpc/kernel/trace/ftrace.c | 36
1 file changed, 36 d
With -mprofile-kernel, we always save the full register state in
ftrace_caller(). While this works, this is inefficient if we're not
interested in the register state, such as when we're using the function
tracer.
Rename the existing ftrace_caller() as ftrace_regs_caller() and provide
a simpler imp
For R_PPC64_REL24 relocations, we suppress emitting instructions for TOC
load/restore in the relocation stub if the relocation is for _mcount()
call when using -mprofile-kernel ABI.
To detect this, we check if the preceding instructions are per the
standard set of instructions emitted by gcc: eith
If function_graph tracer is enabled during kexec, we see the below
exception in the simulator:
root@(none):/# kexec -e
kvm: exiting hardware virtualization
kexec_core: Starting new kernel
[ 19.262020070,5] OPAL: Switch to big-endian OS
kexec: Starting switc
During guest entry/exit, we switch over to/from the guest MMU context.
While doing so, we set our state to KVM_GUEST_MODE_HOST_HV to note down
the fact that we cannot take any exceptions in the hypervisor code.
Since ftrace may be enabled and since it can result in us taking a trap,
disable ftrace
We have some C code that we call into from real mode where we cannot
take any exceptions. Though the C functions themselves are mostly safe,
if these functions are traced, there is a possibility that we may take
an exception. For instance, in certain conditions, the ftrace code uses
WARN(), which u
This is v3 of the patches posted at:
https://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg130652.html
This series has been tested using mambo for p8 (hash) and p9 (radix).
The first two patches fix a kernel oops when function tracing is enabled
while using KVM.
Patch 3 is new and chan
On Thu, Mar 22, 2018 at 3:24 PM, Benjamin Herrenschmidt
wrote:
> On Wed, 2018-03-21 at 08:53 -0500, Sinan Kaya wrote:
>> writel_relaxed() needs to have ordering guarantees with respect to the order
>> device observes writes.
>
> Correct.
>
>> x86 has compiler barrier inside the relaxed() API so th
For SEC 2.x+, cipher in length must contain only the ciphertext length.
In case of using hardware ICV checking, the ICV length is provided via
the "extent" field of the descriptor pointer.
Cc: # 4.8+
Fixes: 549bd8bc5987 ("crypto: talitos - Implement AEAD for SEC1 using
HMAC_SNOOP_NO_AFEU")
Repor
On Thu, Mar 22, 2018 at 7:20 PM, Gabriel Paubert wrote:
> On Thu, Mar 22, 2018 at 04:24:24PM +1100, Oliver wrote:
>> On Thu, Mar 22, 2018 at 1:35 AM, David Laight
>> wrote:
>> >> x86 has compiler barrier inside the relaxed() API so that code does not
>> >> get reordered. ARM64 architecturally gu
Right now we use only 4K out of the 64k page allocated for the level 4 page
table. W.r.t the performance impact due to lock contention, with ebizzy
256 threads:
without patch (10 runs of ./ebizzy -m -n 1000 -s 131072 -S 100)
median = 15678.5
stdev = 42.1209
with patch:
median = 15354
stdev = 194
On Thu, Mar 22, 2018 at 04:24:24PM +1100, Oliver wrote:
> On Thu, Mar 22, 2018 at 1:35 AM, David Laight wrote:
> >> x86 has compiler barrier inside the relaxed() API so that code does not
> >> get reordered. ARM64 architecturally guarantees device writes to be
> >> observed
> >> in order.
> >
> >
Naveen N. Rao wrote:
We have some C code that we call into from real mode where we cannot
take any exceptions. Though the C functions themselves are mostly safe,
if these functions are traced, there is a possibility that we may take
an exception. For instance, in certain conditions, the ftrace co
On Wed, Mar 21, 2018 at 02:53:00PM +0800, Li Wang wrote:
>On Wed, Mar 21, 2018 at 5:58 AM, Ram Pai <[1]linux...@us.ibm.com> wrote:
>
> On Fri, Mar 09, 2018 at 11:43:00AM +0800, Li Wang wrote:
> > On Fri, Mar 9, 2018 at 12:45 AM, Ram Pai
> <[1][2]linux...@us.ibm.com> wrote:
>
89 matches
Mail list logo
