[PATCH] selftests/powerpc: fix exec benchmark

The exec_target binary could segfault calling _exit(2) because r13 is not set up properly (and libc looks at that when performing a syscall). Call SYS_exit using syscall(2) which doesn't seem to have this problem. Signed-off-by: Nicholas Piggin ---

Re: [PATCH] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

On Fri, May 11, 2018 at 11:43 PM, Anju T Sudhakar wrote: > Currently memory is allocated for core-imc based on cpu_present_mask, which > has > bit 'cpu' set iff cpu is populated. We use (cpu number / threads per core) > as as array index to access the memory. > So in a

Re: [PATCH] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

On Fri, 2018-05-11 at 19:13 +0530, Anju T Sudhakar wrote: > Currently memory is allocated for core-imc based on cpu_present_mask, which > has > bit 'cpu' set iff cpu is populated. We use (cpu number / threads per core) > as as array index to access the memory. > So in a system with guarded cores,

Re: make a few block drivers highmem safe

On 5/9/18 7:59 AM, Christoph Hellwig wrote: > Hi all, > > this series converts a few random block drivers to be highmem safe, > in preparation of eventually getting rid of the block layer bounce > buffering support. Applied, thanks. -- Jens Axboe

[PATCH 7/7] cxlflash: Isolate external module dependencies

Depending on the underlying transport, cxlflash has a dependency on either the CXL or OCXL drivers, which are enabled via their Kconfig option. Instead of having a module wide dependency on these config options, it is better to isolate the object modules that are dependent on the CXL and OCXL

[PATCH 6/7] cxlflash: Abstract hardware dependent assignments

As a staging cleanup to support transport specific builds of the cxlflash module, relocate device dependent assignments to header files. This will avoid littering the core driver with conditional compilation logic. Signed-off-by: Uma Krishnan ---

[PATCH 5/7] cxlflash: Add include guards to backend.h

The new header file, backend.h, that was recently added is missing the include guards. This commit adds the guards. Signed-off-by: Uma Krishnan --- drivers/scsi/cxlflash/backend.h | 5 + 1 file changed, 5 insertions(+) diff --git

[PATCH 4/7] cxlflash: Use local mutex for AFU serialization

From: "Matthew R. Ochs" AFUs can only process a single AFU command at a time. This is enforced with a global mutex situated within the AFU send routine. As this mutex has a global scope, it has the potential to unnecessarily block commands destined for other AFUs.

[PATCH 3/7] cxlflash: Acquire semaphore before invoking ioctl services

When a superpipe process that makes use of virtual LUNs is terminated or killed abruptly, there is a possibility that the cxlflash driver could hang and deprive other operations on the adapter. The release fop registered to be invoked on a context close, detaches every LUN associated with the

[PATCH 2/7] cxlflash: Limit the debug logs in the IO path

The kernel log can get filled with debug messages from send_cmd_ioarrin() when dynamic debug is enabled for the cxlflash module and there is a lot of legacy I/O traffic. While these messages are necessary to debug issues that involve command tracking, the abundance of data can overwrite other

[PATCH 1/7] cxlflash: Yield to active send threads

The following Oops may be encountered if the device is reset, i.e. EEH recovery, while there is heavy I/O traffic: 59:mon> t [c000200db64bb680] c00809264c40 cxlflash_queuecommand+0x3b8/0x500 [cxlflash] [c000200db64bb770] c090d3b0

[PATCH 0/7] Miscellaneous patches and bug fixes

This patch series adds few improvements to the cxlflash driver and it also contains couple of bug fixes. This patch series is intended for 4.18 and is bisectable. Matthew R. Ochs (1): cxlflash: Use local mutex for AFU serialization Uma Krishnan (6): cxlflash: Yield to active send threads

RE: [PATCH 3/9] soc: fsl: set rcpm bit for FTM

> -Original Message- > From: Yinbo Zhu [mailto:yinbo@nxp.com] > Sent: Thursday, May 10, 2018 10:35 PM > To: Yinbo Zhu ; Rob Herring ; > Mark Rutland ; Catalin Marinas ) > ; Will Deacon )

Re: [PATCH 2/2] crypto: vmx - Remove overly verbose printk from AES XTS init

On Thu, May 03, 2018 at 10:29:30PM +1000, Michael Ellerman wrote: > In p8_aes_xts_init() we do a printk(KERN_INFO ...) to report the > fallback implementation we're using. However with a slow console this > can significantly affect the speed of crypto operations. So remove it. > > Fixes:

Re: [PATCH 1/2] crypto: vmx - Remove overly verbose printk from AES init routines

On Thu, May 03, 2018 at 10:29:29PM +1000, Michael Ellerman wrote: > In the vmx AES init routines we do a printk(KERN_INFO ...) to report > the fallback implementation we're using. > > However with a slow console this can significantly affect the speed of > crypto operations. Using 'cryptsetup

[PATCH] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

Currently memory is allocated for core-imc based on cpu_present_mask, which has bit 'cpu' set iff cpu is populated. We use (cpu number / threads per core) as as array index to access the memory. So in a system with guarded cores, since allocation happens based on cpu_present_mask, (cpu number /

[GIT PULL] Please pull powerpc/linux.git powerpc-4.17-5 tag

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hi Linus, Please pull some more powerpc fixes for 4.17: The following changes since commit b2d7ecbe355698010a6b7a15eb179e09eb3d6a34: powerpc/kvm/booke: Fix altivec related build break (2018-04-27 16:36:03 +1000) are available in the git

RE: [PATCH v5 5/7] ocxl: Expose the thread_id needed for wait on POWER9

> -Original Message- > From: Frederic Barrat > Sent: Friday, 11 May 2018 7:25 PM > To: Alastair D'Silva ; linuxppc-dev@lists.ozlabs.org > Cc: linux-ker...@vger.kernel.org; linux-...@vger.kernel.org; > mi...@neuling.org;

Re: [PATCH v3 2/2] cxl: Report the tunneled operations status

Le 25/04/2018 à 13:08, Philippe Bergheaud a écrit : Failure to synchronize the tunneled operations does not prevent the initialization of the cxl card. This patch reports the tunneled operations status via /sys. Signed-off-by: Philippe Bergheaud --- Good idea, but

Re: [PATCH v3 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

Le 25/04/2018 à 13:08, Philippe Bergheaud a écrit : Skiboot used to set the default Tunnel BAR register value when capi mode was enabled. This approach was ok for the cxl driver, but prevented other drivers from choosing different values. Skiboot versions > 5.11 will not set the default value

[PATCH 1/2] powerpc: Detect the presence of big-core with interleaved threads

From: "Gautham R. Shenoy" A pair of IBM POWER9 SMT4 cores can be fused together to form a big-core with 8 SMT threads. This can be discovered via the "ibm,thread-groups" CPU property in the device tree which will indicate which group of threads that share the L1 cache,

[PATCH 0/2] powerpc: Scheduler optimization for POWER9 bigcores

From: "Gautham R. Shenoy" Hi, A pair of IBM POWER9 SMT4 cores can be fused together to form a big-core with 8 SMT threads. This can be discovered via the "ibm,thread-groups" CPU property in the device tree which will indicate which group of threads that share the L1

[PATCH 2/2] powerpc: Enable ASYM_SMT on interleaved big-core systems

From: "Gautham R. Shenoy" Each of the SMT4 cores forming a fused-core are more or less independent units. Thus when multiple tasks are scheduled to run on the fused core, we get the best performance when the tasks are spread across the pair of SMT4 cores. Since the

Re: [PATCH v5 5/7] ocxl: Expose the thread_id needed for wait on POWER9

Le 11/05/2018 à 12:06, Alastair D'Silva a écrit : -Original Message- From: Frederic Barrat Sent: Friday, 11 May 2018 7:25 PM To: Alastair D'Silva ; linuxppc-dev@lists.ozlabs.org Cc: linux-ker...@vger.kernel.org; linux-...@vger.kernel.org;

Re: [PATCH] misc: cxl: Change return type to vm_fault_t

Le 17/04/2018 à 16:53, Souptick Joarder a écrit : Use new return type vm_fault_t for fault handler. For now, this is just documenting that the function returns a VM_FAULT value rather than an errno. Once all instances are converted, vm_fault_t will become a distinct type. Reference id ->

Re: [PATCH v5 7/7] ocxl: Document new OCXL IOCTLs

Le 11/05/2018 à 08:13, Alastair D'Silva a écrit : From: Alastair D'Silva Signed-off-by: Alastair D'Silva --- Acked-by: Frederic Barrat Documentation/accelerators/ocxl.rst | 11 +++ 1 file changed, 11

Re: [PATCH v5 6/7] ocxl: Add an IOCTL so userspace knows what OCXL features are available

Le 11/05/2018 à 08:13, Alastair D'Silva a écrit : From: Alastair D'Silva In order for a userspace AFU driver to call the POWER9 specific OCXL_IOCTL_ENABLE_P9_WAIT, it needs to verify that it can actually make that call. Signed-off-by: Alastair D'Silva

Re: [PATCH v5 5/7] ocxl: Expose the thread_id needed for wait on POWER9

Le 11/05/2018 à 08:13, Alastair D'Silva a écrit : From: Alastair D'Silva In order to successfully issue as_notify, an AFU needs to know the TID to notify, which in turn means that this information should be available in userspace so it can be communicated to the AFU.

Re: [PATCH v5 4/7] ocxl: Rename pnv_ocxl_spa_remove_pe to clarify it's action

Le 11/05/2018 à 08:13, Alastair D'Silva a écrit : From: Alastair D'Silva The function removes the process element from NPU cache. Signed-off-by: Alastair D'Silva --- Acked-by: Frederic Barrat

Re: [PATCH v5 3/7] powerpc: use task_pid_nr() for TID allocation

Le 11/05/2018 à 08:12, Alastair D'Silva a écrit : From: Alastair D'Silva The current implementation of TID allocation, using a global IDR, may result in an errant process starving the system of available TIDs. Instead, use task_pid_nr(), as mentioned by the original

Re: [PATCH v5 2/7] powerpc: Use TIDR CPU feature to control TIDR allocation

Le 11/05/2018 à 08:12, Alastair D'Silva a écrit : From: Alastair D'Silva Switch the use of TIDR on it's CPU feature, rather than assuming it is available based on architecture. Signed-off-by: Alastair D'Silva --- Reviewed-by: Frederic Barrat

Re: [PATCH v5 1/7] powerpc: Add TIDR CPU feature for POWER9

Le 11/05/2018 à 08:12, Alastair D'Silva a écrit : From: Alastair D'Silva This patch adds a CPU feature bit to show whether the CPU has the TIDR register available, enabling as_notify/wait in userspace. Signed-off-by: Alastair D'Silva ---

[PATCH] crypto: reorder paes test lexicographically

Due to a snafu "paes" testmgr tests were not ordered lexicographically, which led to boot time warnings. Reorder the tests as needed. Fixes: a794d8d ("crypto: ccree - enable support for hardware keys") Reported-by: Abdul Haleem Signed-off-by: Gilad Ben-Yossef

[PATCH] powerpc/xive: Remove (almost) unused macros

The GETFIELD and SETFIELD macros in xive-regs.h aren't used except for a single instance of GETFIELD, so replace that and remove them. These macros are also defined in vas.h, so either those should be eventually replaced or the macros moved into bitops.h. Signed-off-by: Russell Currey

Re: [next-20180509][bisected a794d8d] ppc boot warnings at crypto/testmgr.c:3720

On Fri, May 11, 2018 at 9:59 AM, Abdul Haleem wrote: > Greeting's > > Today's next kernel on powerpc machine has boot warnings with commit > > a794d8d : crypto: ccree - enable support for hardware keys Adding the crypto list and maintainer as it came in via the

Re: [PATCH 00/17] Implement use of HW assistance on TLB table walk on 8xx

Christophe Leroy writes: > The purpose of this serie is to implement hardware assistance for TLB table > walk > on the 8xx. > > First part is to make L1 entries and L2 entries independant. > For that, we need to alter ioremap functions in order to handle GUARD >

Re: [PATCH 11/17] powerpc/nohash32: set GUARDED attribute in the PMD directly

Christophe Leroy writes: > diff --git a/arch/powerpc/mm/ioremap.c b/arch/powerpc/mm/ioremap.c > index 59be5dfcb3e9..b8c347077e02 100644 > --- a/arch/powerpc/mm/ioremap.c > +++ b/arch/powerpc/mm/ioremap.c > @@ -132,9 +132,14 @@ void __iomem * __ioremap_caller(phys_addr_t

[PATCH v5 5/7] ocxl: Expose the thread_id needed for wait on POWER9

From: Alastair D'Silva In order to successfully issue as_notify, an AFU needs to know the TID to notify, which in turn means that this information should be available in userspace so it can be communicated to the AFU. Signed-off-by: Alastair D'Silva

[PATCH v5 4/7] ocxl: Rename pnv_ocxl_spa_remove_pe to clarify it's action

From: Alastair D'Silva The function removes the process element from NPU cache. Signed-off-by: Alastair D'Silva --- arch/powerpc/include/asm/pnv-ocxl.h | 2 +- arch/powerpc/platforms/powernv/ocxl.c | 4 ++-- drivers/misc/ocxl/link.c |

[PATCH v5 7/7] ocxl: Document new OCXL IOCTLs

From: Alastair D'Silva Signed-off-by: Alastair D'Silva --- Documentation/accelerators/ocxl.rst | 11 +++ 1 file changed, 11 insertions(+) diff --git a/Documentation/accelerators/ocxl.rst b/Documentation/accelerators/ocxl.rst index

[PATCH v5 6/7] ocxl: Add an IOCTL so userspace knows what OCXL features are available

From: Alastair D'Silva In order for a userspace AFU driver to call the POWER9 specific OCXL_IOCTL_ENABLE_P9_WAIT, it needs to verify that it can actually make that call. Signed-off-by: Alastair D'Silva --- drivers/misc/ocxl/file.c | 25

[PATCH v5 0/7] ocxl: Implement Power9 as_notify/wait for OpenCAPI

From: Alastair D'Silva The Power 9 as_notify/wait feature provides a lower latency way to signal a thread that work is complete. This series enables the use of this feature from OpenCAPI adapters, as well as addressing a potential starvation issue when allocating thread

[PATCH v5 1/7] powerpc: Add TIDR CPU feature for POWER9

From: Alastair D'Silva This patch adds a CPU feature bit to show whether the CPU has the TIDR register available, enabling as_notify/wait in userspace. Signed-off-by: Alastair D'Silva --- arch/powerpc/include/asm/cputable.h | 3 ++-

[PATCH v5 3/7] powerpc: use task_pid_nr() for TID allocation

From: Alastair D'Silva The current implementation of TID allocation, using a global IDR, may result in an errant process starving the system of available TIDs. Instead, use task_pid_nr(), as mentioned by the original author. The scenario described which prevented it's use

[PATCH v5 2/7] powerpc: Use TIDR CPU feature to control TIDR allocation

From: Alastair D'Silva Switch the use of TIDR on it's CPU feature, rather than assuming it is available based on architecture. Signed-off-by: Alastair D'Silva --- arch/powerpc/kernel/process.c | 6 +++--- 1 file changed, 3 insertions(+), 3

Re: [PATCH 05/17] powerpc: move io mapping functions into ioremap.c

Christophe Leroy writes: > diff --git a/arch/powerpc/mm/ioremap.c b/arch/powerpc/mm/ioremap.c > new file mode 100644 > index ..5d2645193568 > --- /dev/null > +++ b/arch/powerpc/mm/ioremap.c > @@ -0,0 +1,350 @@ > +/* > + * This file contains the routines for