Highlights include elimination of legacy clock bindings use from dts
files, an 83xx watchdog handler, fixes to old dts interrupt errors, and
some minor cleanup.
The following changes since commit 8c6c942d33f2a79439e86f8f406afae40a5bc767:
powerpc/eeh: Fix debugfs_simple_attr.cocci warnings
On Wed, 2018-12-12 at 01:57 +, Andy Tang wrote:
> > -Original Message-
> > From: Scott Wood
> > Sent: 2018年11月26日 9:19
> > To: Andy Tang
> > Cc: mturque...@baylibre.com; sb...@kernel.org; robh...@kernel.org;
> > mark.rutl...@arm.com; b...@kernel.crashing.org; pau...@samba.org;
> >
Otherwise 64-bit PPC builds fail with undefined references
to these accessors.
Cc: Peng Ma
Cc: Wen He
Fixes: 68997fff94afa (" dmaengine: fsldma: Adding macro FSL_DMA_IN/OUT
implement for ARM platform")
Signed-off-by: Scott Wood
---
Is there any reason why ioreadXXbe() etc can't be used on PPC
This is required for CONFIG_DEBUG_INFO to work.
Signed-off-by: Scott Wood
---
arch/powerpc/configs/fsl-emb-nonhw.config | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs/fsl-emb-nonhw.config
b/arch/powerpc/configs/fsl-emb-nonhw.config
index e0567dc41968..d592ba27b122
On Wed, 2018-07-18 at 14:46 +0300, Camelia Groza wrote:
> The Cortina PHY requires the use of the dedicated Cortina PHY driver
> instead of the generic one.
>
> Signed-off-by: Camelia Groza
> ---
> arch/powerpc/boot/dts/fsl/t4240rdb.dts | 8
> 1 file changed, 4 insertions(+), 4
mpc8641_hpcn was updated to 4-cell interrupt specifiers, but
PCI interrupt-map was not updated. It was also missing #interrupt-cells
on the outer PCI buses.
p1020rdb-pc was updated to 4-cell interrupt specifiers, but
the ethernet-phy nodes weren't updated.
mpc832x_rdb had an invalid "interrupts
On Fri, 2018-12-07 at 09:22 +0100, Nicholas Mc Guire wrote:
> devm_kstrdup() may return NULL if internal allocation failed, but
> as machine is from the device tree, and thus RO, devm_kstrdup_const()
> can be used here, which will only copy the reference.
Is it really going to only copy the
On Thu, 2018-11-15 at 23:26 +0530, Sabyasachi Gupta wrote:
> On Mon, Nov 5, 2018 at 7:52 AM Sabyasachi Gupta
> wrote:
> >
> > Replaced dma_alloc_coherent + memset with dma_zalloc_coherent
> >
> > Signed-off-by: Sabyasachi Gupta
>
> Any comment on this patch?
Just that FSL patches should be
On Thu, 2018-12-20 at 21:02 -0500, Steven Rostedt wrote:
> On Fri, 21 Dec 2018 12:11:35 +1100
> Benjamin Herrenschmidt wrote:
>
> > Hi Steven !
> >
> > I'm trying to untangle something, and I need your help :-)
> >
> > In commit 3cb5f1a3e58c0bd70d47d9907cc5c65192281dee, you added a summy
> >
From: "Steven Rostedt (VMware)"
The structure of the ret_stack array on the task struct is going to
change, and accessing it directly via the curr_ret_stack index will no
longer give the ret_stack entry that holds the return address. To access
that, architectures must now use
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
Documentation/admin-guide/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt
b/Documentation/admin-guide/kernel-parameters.txt
index aefd358..cf6b4c5
If the user choses not to use the mitigations, replace
the code sequence with nops.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/kernel/setup-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/setup-common.c
In order to protect against speculation attacks on
indirect branches, the branch predictor is flushed at
kernel entry to protect for the following situations:
- userspace process attacking another userspace process
- userspace process attacking the kernel
Basically when the privillege level change
Report branch predictor state flush as a mitigation for
Spectre variant 2.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/kernel/security.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c
In order to protect against speculation attacks on
indirect branches, the branch predictor is flushed at
kernel entry to protect for the following situations:
- userspace process attacking another userspace process
- userspace process attacking the kernel
Basically when the privillege level change
In order to protect against speculation attacks (Spectre
variant 2) on NXP PowerPC platforms, the branch predictor
should be flushed when the privillege level is changed.
This patch is adding the infrastructure to fixup at runtime
the code sections that are performing the branch predictor flush
Implement Spectre variant 2 workarounds for NXP PowerPC Book3E
processors.
Diana Craciun (11):
Add infrastructure to fixup branch predictor flush
Add macro to flush the branch predictor
Fix spectre_v2 mitigations reporting
Emulate SPRN_BUCSR register
Add nospectre_v2 command line
The BUCSR register can be used to invalidate the entries in the
branch prediction mechanisms.
Signed-off-by: Diana Craciun
---
v1-->v2
- no change
arch/powerpc/include/asm/ppc_asm.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc_asm.h
Switching from the guest to host is another place
where the speculative accesses can be exploited.
Flush the branch predictor when entering KVM.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/kvm/bookehv_interrupts.S | 4
1 file changed, 4 insertions(+)
diff --git
In order to flush the branch predictor the guest kernel
performs writes to the BUCSR register which is hypervisor
privilleged. However, the branch predictor is flushed at
each KVM entry, so the branch predictor has been already
flushed, so just return as soon as possible to guest.
Signed-off-by:
Currently for CONFIG_PPC_FSL_BOOK3E
cat /sys/devices/system/cpu/vulnerabilities/spectre_v2 reports:
"Mitigation: Software count cache flush" which is wrong. Fix it
to report vulnerable for now.
Signed-off-by: Diana Craciun
---
v1->v2
- no change
arch/powerpc/kernel/security.c | 2 +-
1 file
When the command line argument is present, the Spectre variant 2
mitigations are disabled.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/include/asm/setup.h | 5 +
arch/powerpc/kernel/security.c | 21 +
2 files changed, 26 insertions(+)
diff
The OPAL call wrapper gets interrupt disabling wrong. It disables
interrupts just by clearing MSR[EE], which has two problems:
- It doesn't call into the IRQ tracing subsystem, which means tracing
across OPAL calls does not always notice IRQs have been disabled.
- It doesn't go through the IRQ
By clearing all interrupt sources, not only those that
already occurred, the existing code may acknowledge by
mistake interrupts that occurred after the code checks
for them.
Signed-off-by: Madalin Bucur
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/qman.c | 9 +
1 file changed,
Hello Bjorn,
On Thu, 20 Dec 2018, Bjorn Helgaas wrote:
> I think the strategy is fine, but can you restructure the patches
> like this:
>
> 1) Factor out sriov_add_vfs() and sriov_dev_vfs(). This makes no
> functional change at all.
>
> 2) Add dev->no_vf_scan, set it in the s390
Set the flag to skip scanning for VFs after SRIOV enablement.
VF creation will be triggered by the hotplug code.
Signed-off-by: Sebastian Ott
Reviewed-by: Christoph Hellwig
---
arch/s390/pci/pci.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
Provide a flag to skip scanning for new VFs after SRIOV enablement.
This can be set by implementations for which the VFs are already
reported by other means.
Signed-off-by: Sebastian Ott
Reviewed-by: Christoph Hellwig
---
drivers/pci/iov.c | 6 ++
include/linux/pci.h | 1 +
2 files
Provide sriov_add_vfs as a wrapper to scan for VFs that cleans up
after itself. This is just a code simplification. No functional change.
Signed-off-by: Sebastian Ott
Reviewed-by: Christoph Hellwig
---
drivers/pci/iov.c | 44 +++-
1 file changed, 31
On Tue, 2018-10-09 at 15:24 +0200, Christoph Hellwig wrote:
> * Find the least restrictive zone that is entirely below the
> @@ -324,11 +305,14 @@ void __init paging_init(void)
> printk(KERN_DEBUG "Memory hole size: %ldMB\n",
>(long int)((top_of_ram - total_ram) >> 20));
On 06/12/18 14:21, lantianyu1...@gmail.com wrote:
> static inline int hyperv_flush_guest_mapping(u64 as) { return -1; }
> +static inline int hyperv_flush_guest_mapping_range(u64 as,
> + hyperv_fill_flush_list_func fill_func, void *data);
> +{
> + return -1;
This part for
On 06/12/18 14:21, lantianyu1...@gmail.com wrote:
> From: Lan Tianyu
>
> For nested memory virtualization, Hyper-v doesn't set write-protect
> L1 hypervisor EPT page directory and page table node to track changes
> while it relies on guest to tell it changes via HvFlushGuestAddressLlist
>
[2.364486] WARNING: CPU: 0 PID: 60 at ./arch/powerpc/include/asm/io.h:837
dma_nommu_map_page+0x44/0xd4
[2.373579] CPU: 0 PID: 60 Comm: cryptomgr_test Tainted: GW
4.20.0-rc5-00560-g6bfb52e23a00-dirty #531
[2.384740] NIP: c000c540 LR: c000c584 CTR:
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