[PATCH v10 13/14] powerpc/vas: Free send window in VAS instance after credits returned

2020-04-02 Thread Haren Myneni
NX may be processing requests while trying to close window. Wait until all credits are returned and then free send window from VAS instance. Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas-window.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH v10 12/14] powerpc/vas: Display process stuck message

2020-04-02 Thread Haren Myneni
Process can not close send window until all requests are processed. Means wait until window state is not busy and send credits are returned. Display debug messages in case taking longer to close the window. Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas-window.c | 28

[PATCH v10 11/14] powerpc/vas: Do not use default credits for receive window

2020-04-02 Thread Haren Myneni
System checkstops if RxFIFO overruns with more requests than the maximum possible number of CRBs allowed in FIFO at any time. So max credits value (rxattr.wcreds_max) is set and is passed to vas_rx_win_open() by the the driver. Signed-off-by: Haren Myneni ---

[PATCH v10 10/14] powerpc/vas: Print CRB and FIFO values

2020-04-02 Thread Haren Myneni
Dump FIFO entries if could not find send window and print CRB for debugging. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas-fault.c | 41 ++ 1 file changed, 41 insertions(+) diff --git

[PATCH v10 09/14] powerpc/vas: Return credits after handling fault

2020-04-02 Thread Haren Myneni
NX uses credit mechanism to control the number of requests issued on a specific window at any point of time. Only send windows and fault window are used credits. When the request is issued on a given window, a credit is taken. This credit will be returned after that request is processed. If

[PATCH v10 08/14] powerpc/vas: Update CSB and notify process for fault CRBs

2020-04-02 Thread Haren Myneni
Applications polls on CSB for the status update after requests are issued. NX process these requests and update the CSB with the status. If it encounters translation error, pastes CRB in fault FIFO and raises an interrupt. The kernel handles fault by reading CRB from fault FIFO and process the

[PATCH v10 07/14] powerpc/vas: Setup thread IRQ handler per VAS instance

2020-04-02 Thread Haren Myneni
When NX encounters translation error on CRB and any request buffer, raises an interrupt on the CPU to handle the fault. It can raise one interrupt for multiple faults. Expects OS to handle these faults and return credits for fault window after processing faults. Setup thread IRQ handler and IRQ

[PATCH v10 06/14] powerpc/vas: Take reference to PID and mm for user space windows

2020-04-02 Thread Haren Myneni
When process opens a window, its pid and tgid will be saved in the vas_window struct. This window will be closed when the process exits. The kernel handles NX faults by updating CSB or send SEGV signal to pid of the process if the user space csb addr is invalid. In multi-thread applications, a

[PATCH v10 05/14] powerpc/vas: Register NX with fault window ID and IRQ port value

2020-04-02 Thread Haren Myneni
For each user space send window, register NX with fault window ID and port value so that NX paste CRBs in this fault FIFO when it sees fault on the request buffer. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas-window.c | 15

[PATCH v10 04/14] powerpc/vas: Setup fault window per VAS instance

2020-04-02 Thread Haren Myneni
Setup fault window for each VAS instance. When NX gets a fault on request buffer, pastes fault CRB in the corresponding fault FIFO and then raises an interrupt to the OS. The kernel handles this fault and process faults CRB from this FIFO. Signed-off-by: Sukadev Bhattiprolu Signed-off-by:

[PATCH v10 03/14] powerpc/vas: Alloc and setup IRQ and trigger port address

2020-04-02 Thread Haren Myneni
Allocate a xive irq on each chip with a vas instance. The NX coprocessor raises a host CPU interrupt via vas if it encounters page fault on user space request buffer. Subsequent patches register the trigger port with the NX coprocessor, and create a vas fault handler for this interrupt mapping.

[PATCH v10 02/14] powerpc/vas: Define nx_fault_stamp in coprocessor_request_block

2020-04-02 Thread Haren Myneni
Kernel sets fault address and status in CRB for NX page fault on user space address after processing page fault. User space gets the signal and handles the fault mentioned in CRB by bringing the page in to memory and send NX request again. Signed-off-by: Sukadev Bhattiprolu Signed-off-by:

[PATCH v10 01/14] powerpc/xive: Define xive_native_alloc_irq_on_chip()

2020-04-02 Thread Haren Myneni
This function allocates IRQ on a specific chip. VAS needs per chip IRQ allocation and will have IRQ handler per VAS instance. Signed-off-by: Haren Myneni Reviewed-by: Cédric Le Goater --- arch/powerpc/include/asm/xive.h | 9 - arch/powerpc/sysdev/xive/native.c | 6 +++--- 2 files

Re: [RFC PATCH 3/4] powerpc ppc-opcode: move ppc instuction encoding from test_emulate_step

2020-04-02 Thread Naveen N. Rao
Michael Ellerman wrote: "Naveen N. Rao" writes: Balamuruhan S wrote: Few ppc instructions are encoded in test_emulate_step.c, consolidate them to ppc-opcode.h, fix redefintion errors in bpf_jit caused due to this consolidation. Reuse the macros from ppc-opcode.h ... diff --git

[PATCH v10 00/14] powerpc/vas: Page fault handling for user space NX requests

2020-04-02 Thread Haren Myneni
On power9, Virtual Accelerator Switchboard (VAS) allows user space or kernel to communicate with Nest Accelerator (NX) directly using COPY/PASTE instructions. NX provides various functionalities such as compression, encryption and etc. But only compression (842 and GZIP formats) is supported in

Re: [PATCH v4 14/25] nvdimm/ocxl: Add support for Admin commands

2020-04-02 Thread Dan Williams
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote: > > Admin commands for these devices are the primary means of interacting > with the device controller to provide functionality beyond the load/store > capabilities offered via the NPU. > > For example, SMART data, firmware update, and

Re: [PATCH v4 06/25] ocxl: Tally up the LPC memory on a link & allow it to be mapped

2020-04-02 Thread Andrew Donnellan
On 1/4/20 7:48 pm, Dan Williams wrote: On Sun, Mar 29, 2020 at 10:53 PM Alastair D'Silva wrote: OpenCAPI LPC memory is allocated per link, but each link supports multiple AFUs, and each AFU can have LPC memory assigned to it. Is there an OpenCAPI primer to decode these objects and their

Re: [PATCH V2 3/5] selftests/powerpc: Add NX-GZIP engine compress testcase

2020-04-02 Thread Daniel Axtens
Raphael Moreira Zinsly writes: > Add a compression testcase for the powerpc NX-GZIP engine. > > Signed-off-by: Bulent Abali > Signed-off-by: Raphael Moreira Zinsly > --- > .../selftests/powerpc/nx-gzip/Makefile| 21 + > .../selftests/powerpc/nx-gzip/gzfht_test.c| 489

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