On 7/24/20 3:10 PM, Waiman Long wrote:
On 7/24/20 4:16 AM, Will Deacon wrote:
On Thu, Jul 23, 2020 at 08:47:59PM +0200, pet...@infradead.org wrote:
On Thu, Jul 23, 2020 at 02:32:36PM -0400, Waiman Long wrote:
BTW, do you have any comment on my v2 lock holder cpu info
qspinlock patch?
I will ha
Hari Bathini writes:
> On 24/07/20 5:36 am, Thiago Jung Bauermann wrote:
>>
>> Hari Bathini writes:
>>
>>> Kdump kernel, used for capturing the kernel core image, is supposed
>>> to use only specific memory regions to avoid corrupting the image to
>>> be captured. The regions are crashkernel r
On 7/24/20 9:14 AM, Nicholas Piggin wrote:
Updated with everybody's feedback (thanks all), and more performance
results.
What I've found is I might have been measuring the worst load point for
the paravirt case, and by looking at a range of loads it's clear that
queued spinlocks are overall bett
On 7/24/20 9:14 AM, Nicholas Piggin wrote:
This implements smp_cond_load_relaed with the slowpath busy loop using the
Nit: "smp_cond_load_relaxed"
Cheers,
Longman
Some of the kexec_file_load code isn't PPC64 specific. Move PPC64
specific code from kexec/file_load.c to kexec/file_load_64.c. Also,
rename purgatory/trampoline.S to purgatory/trampoline_64.S in the
same spirit. No functional changes.
Signed-off-by: Hari Bathini
Tested-by: Pingfan Liu
Reviewed-
Some architectures may have special memory regions, within the given
memory range, which can't be used for the buffer in a kexec segment.
Implement weak arch_kexec_locate_mem_hole() definition which arch code
may override, to take care of special regions, while trying to locate
a memory hole.
Also
This patch series enables kdump support for kexec_file_load system
call (kexec -s -p) on PPC64. The changes are inspired from kexec-tools
code but heavily modified for kernel consumption.
The first patch adds a weak arch_kexec_locate_mem_hole() function to
override locate memory hole logic suiting
On 7/24/20 4:16 AM, Will Deacon wrote:
On Thu, Jul 23, 2020 at 08:47:59PM +0200, pet...@infradead.org wrote:
On Thu, Jul 23, 2020 at 02:32:36PM -0400, Waiman Long wrote:
BTW, do you have any comment on my v2 lock holder cpu info qspinlock patch?
I will have to update the patch to fix the report
Michael Ellerman a écrit :
We have two uses of CONFIG_BOOK3S_601, which doesn't exist. Fix them
to use CONFIG_PPC_BOOK3S_601 which is the correct symbol.
Fixes: 12c3f1fd87bf ("powerpc/32s: get rid of CPU_FTR_601 feature")
Signed-off-by: Michael Ellerman
---
I think the bug in get_cycles() at
> On 24-Jul-2020, at 5:56 PM, Ravi Bangoria wrote:
>
> Hi Athira,
>
>> +/* Function to return the extended register values */
>> +static u64 get_ext_regs_value(int idx)
>> +{
>> +switch (idx) {
>> +case PERF_REG_POWERPC_MMCR0:
>> +return mfspr(SPRN_MMCR0);
>> +case PER
> On 24-Jul-2020, at 4:32 PM, Ravi Bangoria wrote:
>
> Hi Athira,
>
> On 7/17/20 8:08 PM, Athira Rajeev wrote:
>> From: Anju T Sudhakar
>> Add extended regs to sample_reg_mask in the tool side to use
>> with `-I?` option. Perf tools side uses extended mask to display
>> the platform supporte
Pingfan Liu writes:
> On Thu, Jul 23, 2020 at 9:27 PM Nathan Lynch wrote:
>> Pingfan Liu writes:
>> > This will introduce extra dt updating payload for each involved lmb when
>> > hotplug.
>> > But it should be fine since drmem_update_dt() is memory based operation and
>> > hotplug is not a hot
On 24/07/20 5:36 am, Thiago Jung Bauermann wrote:
>
> Hari Bathini writes:
>
>> Kdump kernel, used for capturing the kernel core image, is supposed
>> to use only specific memory regions to avoid corrupting the image to
>> be captured. The regions are crashkernel range - the memory reserved
>
On Mon, 13 Jul 2020 09:39:33 -0500, wenxi...@linux.vnet.ibm.com wrote:
> Several device drivers hit EEH(Extended Error handling) when triggering
> kdump on Pseries PowerVM. This patch implemented a reset of the PHBs
> in pci general code when triggering kdump. PHB reset stop all PCI
> transactions
On Fri, 17 Jul 2020 19:27:14 +0800, YueHaibing wrote:
> Both of those functions are only called from 64-bit only code, so the
> stubs should not be needed at all.
Applied to powerpc/next.
[1/1] powerpc: Remove unneeded inline functions
https://git.kernel.org/powerpc/c/a3f3f8aa1f72dafe1450cc
On Tue, 21 Jul 2020 14:49:15 +0530, Santosh Sivaraj wrote:
> hash_low_64.S was removed in [1] and since flush_hash_page is not called
> from any assembly routine.
>
> [1]: commit a43c0eb8364c0 ("powerpc/mm: Convert 4k insert from asm to C")
Applied to powerpc/next.
[1/1] powerpc/mm/hash64: Remov
On Thu, 9 Jul 2020 19:21:41 +0530, Santosh Sivaraj wrote:
> Introduce notification chain which lets us know about uncorrected memory
> errors(UE). This would help prospective users in pmem or nvdimm subsystem
> to track bad blocks for better handling of persistent memory allocations.
Applied to po
On Tue, 21 Jul 2020 21:07:05 +0530, Pratik Rajesh Sampat wrote:
> v3: https://lkml.org/lkml/2020/7/17/1093
> Changelog v3-->v4:
> Based on comments from Nicholas Piggin and Gautham Shenoy,
> 1. Changed the naming of pnv_first_spr_loss_level from
> pnv_first_fullstate_loss_level to deep_spr_loss_sta
On Thu, 16 Jul 2020 12:38:20 -0700, Palmer Dabbelt wrote:
> This primitive has been renamed, but because it was spelled incorrectly in the
> first place it must have escaped the fixup patch. As far as I can tell this
> logic is still correct: smp_mb__after_spinlock() uses the default smp_mb()
> im
On Thu, 16 Jul 2020 11:35:22 +1000, Nicholas Piggin wrote:
> powerpc return from interrupt and return from system call sequences are
> context synchronising.
Applied to powerpc/next.
[1/1] powerpc: Select ARCH_HAS_MEMBARRIER_SYNC_CORE
https://git.kernel.org/powerpc/c/2384b36f9156c3b815a5ce5
On Fri, 3 Jul 2020 11:19:55 +1000, Nicholas Piggin wrote:
> It was suggested that I post this to a wider audience on account of
> the change to supported userspace features in patch 2 particularly.
>
> Thanks,
> Nick
>
> Nicholas Piggin (3):
> powerpc: remove stale calc_vm_prot_bits comment
>
On Fri, 3 Jul 2020 09:33:43 +1000, Nicholas Piggin wrote:
>
Applied to powerpc/next.
[1/1] powerpc/powernv: Machine check handler for POWER10
https://git.kernel.org/powerpc/c/201220bb0e8cbc163ec7f550b3b7b3da46eb5877
cheers
On Fri, 8 May 2020 23:06:33 +1000, Michael Ellerman wrote:
> Currently the spu coredump code triggers an RCU warning:
>
> =
> WARNING: suspicious RCU usage
> 5.7.0-rc3-01755-g7cd49f0b7ec7 #1 Not tainted
> -
> include/linux/fdtable.h
On Thu, 11 Jun 2020 18:12:02 +1000, Nicholas Piggin wrote:
> The scv instruction causes an interrupt which can enter the kernel with
> MSR[EE]=1, thus allowing interrupts to hit at any time. These must not
> be taken as normal interrupts, because they come from MSR[PR]=0 context,
> and yet the kern
On Wed, 22 Jul 2020 15:53:15 +1000, Michael Ellerman wrote:
> Update our memcmp selftest, to test the case where we're comparing up
> to the end of a page and the subsequent page is not mapped. We have to
> make sure we don't read off the end of the page and cause a fault.
>
> We had a bug there i
On Thu, 16 Jul 2020 22:21:42 +1000, Michael Ellerman wrote:
> The per_event_excludes test wants to run on Power8 or later. But
> currently it checks that AT_BASE_PLATFORM *equals* power8, which means
> it only runs on Power8.
>
> Fix it to check for the ISA 2.07 feature, which will be set on Power
On Sun, 14 Jun 2020 14:06:04 +0530, Madhavan Srinivasan wrote:
> Compilation error:
>
> arch/powerpc/perf/perf_regs.c:80:undefined reference to `.is_sier_available'
>
> Currently is_sier_available() is part of core-book3s.c.
> But then, core-book3s.c is added to build based on
> CONFIG_PPC_PERF_C
On Mon, 6 Jul 2020 21:48:12 -0300, Leonardo Bras wrote:
> On PAPR+ the hcall() on 0x1B0 is called H_DISABLE_AND_GET, but got
> defined as H_DISABLE_AND_GETC instead.
>
> This define was introduced with a typo in commit
> ("[PATCH] powerpc: Extends HCALL interface for InfiniBand usage"), and was
>
On Mon, 25 May 2020 12:59:19 +1000, Jordan Niethe wrote:
> Add tests for the prefixed versions of the integer load/stores that are
> currently tested. This includes the following instructions:
> * Prefixed Load Doubleword (pld)
> * Prefixed Load Word and Zero (plwz)
> * Prefixed Store Doublew
On Tue, 2 Jun 2020 15:27:25 +1000, Jordan Niethe wrote:
> There are quite a few places where instructions are printed, this is
> done using a '%x' format specifier. With the introduction of prefixed
> instructions, this does not work well. Currently in these places,
> ppc_inst_val() is used for the
On Wed, 10 Jun 2020 10:55:54 +0200, Christoph Hellwig wrote:
> Both the ->dump method and snprintf return an int. So switch to an
> int and properly handle errors from ->dump.
Applied to powerpc/next.
[1/1] powerpc/spufs: Fix the type of ret in spufs_arch_write_note
https://git.kernel.org/
On Sat, 18 Jul 2020 12:39:58 +0200, Alexander A. Klimov wrote:
> Rationale:
> Reduces attack surface on kernel devs opening the links for MITM
> as HTTPS traffic is much harder to manipulate.
>
> Deterministic algorithm:
> For each file:
> If not .svg:
> For each line:
> If doesn't con
On Fri, 17 Jul 2020 20:29:40 +0200, Alexander A. Klimov wrote:
> Rationale:
> Reduces attack surface on kernel devs opening the links for MITM
> as HTTPS traffic is much harder to manipulate.
>
> Deterministic algorithm:
> For each file:
> If not .svg:
> For each line:
> If doesn't con
On Fri, 17 Jul 2020 20:35:22 +0200, Alexander A. Klimov wrote:
> Rationale:
> Reduces attack surface on kernel devs opening the links for MITM
> as HTTPS traffic is much harder to manipulate.
>
> Deterministic algorithm:
> For each file:
> If not .svg:
> For each line:
> If doesn't con
On Fri, 26 Jun 2020 15:21:54 +0530, Balamuruhan S wrote:
> This patchset adds support to test negative scenarios and adds testcase
> for paddi with few fixes. It is based on powerpc/next and on top of
> Jordan's tests for prefixed instructions patchsets,
>
> https://lists.ozlabs.org/pipermail/linu
On Fri, 17 Jul 2020 10:38:12 -0400, Athira Rajeev wrote:
> The patch series adds support for power10 PMU hardware.
>
> Patches 1..3 are the clean up patches which refactors the way how
> PMU SPR's are stored in core-book3s and in KVM book3s, as well as update
> data type for PMU cache_events.
>
>
On Thu, 9 Jul 2020 08:59:23 +0530, Aneesh Kumar K.V wrote:
> This patch series update the pkey subsystem with more documentation and
> rename variables so that it is easy to follow the code. We drop the changes
> to support KUAP/KUEP with hash translation in this update. The changes
> are adding 20
On Thu, 9 Jul 2020 18:49:21 +0530, Aneesh Kumar K.V wrote:
> This is the next version of the fixes for memory unplug on radix.
> The issues and the fix are described in the actual patches.
>
> Changes from v2:
> - Address review feedback
>
> Changes from v1:
> - Added back patch to drop split_ker
There's a comment in time.h referring to CONFIG_POWER, which doesn't
exist. That confuses scripts/checkkconfigsymbols.py.
Presumably the comment was referring to a CONFIG_POWER vs CONFIG_PPC,
in which case for CONFIG_POWER we would #define __USE_RTC to 1. But
instead we have CONFIG_PPC_BOOK3S_601,
This comment refers to the non-existent CONFIG_PPC_BOOK3S_XX, which
confuses scripts/checkkconfigsymbols.py.
Change it to use the correct symbol.
Signed-off-by: Michael Ellerman
---
arch/powerpc/kvm/book3s_interrupts.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/pow
Commit 866bfc75f40e ("powerpc: conditionally compile platform-specific
serial drivers") made some code depend on CONFIG_PPC_MPC52XX, which
doesn't exist.
Fix it to use CONFIG_PPC_MPC52xx.
Fixes: 866bfc75f40e ("powerpc: conditionally compile platform-specific serial
drivers")
Signed-off-by: Micha
We have two uses of CONFIG_BOOK3S_601, which doesn't exist. Fix them
to use CONFIG_PPC_BOOK3S_601 which is the correct symbol.
Fixes: 12c3f1fd87bf ("powerpc/32s: get rid of CPU_FTR_601 feature")
Signed-off-by: Michael Ellerman
---
I think the bug in get_cycles() at least demonstrates that no one
All 32 and 64-bit builds that don't have CONFIG_TAU_INT enabled (all
of them), get a definition of TAUException() in traps.c.
On 64-bit it's completely useless, and just wastes ~120 bytes of text.
On 32-bit it allows the kernel to link because head_32.S calls it
unconditionally.
Instead follow th
There's a comment in lite5200_sleep.S that refers to "CONFIG_BDI*".
This confuses scripts/checkkconfigsymbols.py, which thinks it should
be able to find CONFIG_BDI.
Change the comment to refer to CONFIG_BDI_SWITCH which is presumably
roughly what it was referring to. AFAICS there never has been a
This code was merged 11 years ago in commit 13363ab9b9d0 ("powerpc:
Add definitions used by exception handling on 64-bit Book3E") but was
never able to be built because CONFIG_BOOK3E_MMU_TLB_STATS never
existed. Remove it.
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/exception-64
Remove references to symbols that no longer exist as reported by
scripts/checkkconfigsymbols.py.
Signed-off-by: Michael Ellerman
---
arch/powerpc/configs/44x/akebono_defconfig | 1 -
arch/powerpc/configs/85xx/xes_mpc85xx_defconfig | 3 ---
arch/powerpc/configs/86xx-hw.config | 2
ppc6xx_defconfig refers to quite a few symbols that no longer exist,
as reported by scripts/checkkconfigsymbols.py, remove them.
Signed-off-by: Michael Ellerman
---
arch/powerpc/configs/ppc6xx_defconfig | 39 ---
1 file changed, 39 deletions(-)
diff --git a/arch/powerpc/
When I "fixed" the ppc64e build in Nick's recent patch, I typoed the
CONFIG symbol, resulting in one that doesn't exist. Fix it to use the
correct symbol.
Reported-by: Christophe Leroy
Fixes: 7fa95f9adaee ("powerpc/64s: system call support for scv/rfscv
instructions")
Signed-off-by: Michael Elle
This implements smp_cond_load_relaed with the slowpath busy loop using the
preferred SMT priority pattern.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/barrier.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/powerpc/include/asm/barrier.h
b/arch/powerpc/
This brings the behaviour of the uncontended fast path back to roughly
equivalent to simple spinlocks -- a single atomic op with lock hint.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/atomic.h| 28
arch/powerpc/include/asm/qspinlock.h | 2 +-
2 f
This implements the generic paravirt qspinlocks using H_PROD and H_CONFER to
kick and wait.
This uses an un-directed yield to any CPU rather than the directed yield to
a pre-empted lock holder that paravirtualised simple spinlocks use, that
requires no kick hcall. This is something that could be i
These have shown significantly improved performance and fairness when
spinlock contention is moderate to high on very large systems.
With this series including subsequent patches, on a 16 socket 1536 thread
POWER9, a stress test such as same-file open/close from all CPUs gets big
speedups, 11620op
To prepare for queued spinlocks. This is a simple rename except to update
preprocessor guard name and a file reference.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/simple_spinlock.h| 288 ++
.../include/asm/simple_spinlock_types.h | 21 ++
arch/powerpc/
These functions will be used by queued spinlock implementation,
and may be useful elsewhere too, so move them out of spinlock.h.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/paravirt.h | 59 +
arch/powerpc/include/asm/spinlock.h | 24 +---
arch/
Updated with everybody's feedback (thanks all), and more performance
results.
What I've found is I might have been measuring the worst load point for
the paravirt case, and by looking at a range of loads it's clear that
queued spinlocks are overall better even on PV, doubly so when you look
at the
Hi Athira,
+/* Function to return the extended register values */
+static u64 get_ext_regs_value(int idx)
+{
+ switch (idx) {
+ case PERF_REG_POWERPC_MMCR0:
+ return mfspr(SPRN_MMCR0);
+ case PERF_REG_POWERPC_MMCR1:
+ return mfspr(SPRN_MMCR1);
+
On Thu, Jul 23, 2020 at 9:27 PM Nathan Lynch wrote:
>
> Pingfan Liu writes:
> > A bug is observed on pseries by taking the following steps on rhel:
> > -1. drmgr -c mem -r -q 5
> > -2. echo c > /proc/sysrq-trigger
> >
> > And then, the failure looks like:
> > kdump: saving to /sysroot//var/crash/
On Fri, Jul 24, 2020 at 09:52:14PM +1000, Michael Ellerman wrote:
> Bharata B Rao writes:
> > On Tue, Jul 21, 2020 at 10:25:58PM +1000, Michael Ellerman wrote:
> >> Bharata B Rao writes:
> >> > On Tue, Jul 21, 2020 at 11:45:20AM +1000, Michael Ellerman wrote:
> >> >> Nathan Lynch writes:
> >> >>
Bharata B Rao writes:
> On Tue, Jul 21, 2020 at 10:25:58PM +1000, Michael Ellerman wrote:
>> Bharata B Rao writes:
>> > On Tue, Jul 21, 2020 at 11:45:20AM +1000, Michael Ellerman wrote:
>> >> Nathan Lynch writes:
>> >> > "Aneesh Kumar K.V" writes:
>> >> >> This is the next version of the fixes
Ram Pai writes:
> On Wed, Jul 22, 2020 at 12:06:06PM +1000, Michael Ellerman wrote:
>> Ram Pai writes:
>> > An instruction accessing a mmio address, generates a HDSI fault. This
>> > fault is
>> > appropriately handled by the Hypervisor. However in the case of
>> > secureVMs, the
>> > fault i
Hi Athira,
On 7/17/20 8:08 PM, Athira Rajeev wrote:
From: Anju T Sudhakar
Add extended regs to sample_reg_mask in the tool side to use
with `-I?` option. Perf tools side uses extended mask to display
the platform supported register names (with -I? option) to the user
and also send this mask to
MAX_NUMNODES is a theoretical maximum number of nodes thats is supported
by the kernel. Device tree properties exposes the number of possible
nodes on the current platform. The kernel would detected this and would
use it for most of its resource allocations. If the platform now
increases the nodes
Hi Bill,
Bill Wendling writes:
> Clang's objdump emits slightly different output from GNU's objdump,
> causing a list of warnings to be emitted during relocatable builds.
> E.g., clang's objdump emits this:
>
>c004: 2c 00 00 48 b 0xc030
>...
>c0005c6c
Christophe Leroy writes:
> Michael Ellerman a écrit :
>
>> Nicholas Piggin writes:
>>> diff --git a/arch/powerpc/include/asm/ppc-opcode.h
>>> b/arch/powerpc/include/asm/ppc-opcode.h
>>> index 2a39c716c343..b2bdc4de1292 100644
>>> --- a/arch/powerpc/include/asm/ppc-opcode.h
>>> +++ b/arch/power
Now that the powerpc code behaves the same as other architectures we
can drop the special cases we had.
Signed-off-by: Michael Ellerman
---
.../powerpc/mm/stack_expansion_ldst.c | 41 +++
1 file changed, 5 insertions(+), 36 deletions(-)
v2: no change just rebased.
diff
We have powerpc specific logic in our page fault handling to decide if
an access to an unmapped address below the stack pointer should expand
the stack VMA.
The logic aims to prevent userspace from doing bad accesses below the
stack pointer. However as long as the stack is < 1MB in size, we allow
Update the stack expansion load/store test to take into account the
new allowance of 4224 bytes below the stack pointer.
Signed-off-by: Michael Ellerman
---
.../selftests/powerpc/mm/stack_expansion_ldst.c| 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
v2: Update for cha
We have powerpc specific logic in our page fault handling to decide if
an access to an unmapped address below the stack pointer should expand
the stack VMA.
The code was originally added in 2004 "ported from 2.4". The rough
logic is that the stack is allowed to grow to 1MB with no extra
checking.
We have custom stack expansion checks that it turns out are extremely
badly tested and contain bugs, surprise. So add some tests that
exercise the code and capture the current boundary conditions.
The signal test currently fails on 64-bit kernels because the 2048
byte allowance for the signal fram
Daniel Axtens writes:
> Hi Michael,
>
> Unfortunately, this patch doesn't completely solve the problem.
>
> Trying the original reproducer, I'm still able to trigger the crash even
> with this patch, although not 100% of the time. (If I turn ASLR off
> outside of tmux it reliably crashes, if I tur
When a secure memslot is dropped, all the pages backed in the secure
device (aka really backed by secure memory by the Ultravisor)
should be paged out to a normal page. Previously, this was
achieved by triggering the page fault mechanism which is calling
kvmppc_svm_page_out() on each pages.
This c
+++ Jarkko Sakkinen [24/07/20 10:36 +0300]:
On Thu, Jul 23, 2020 at 03:42:09PM +0300, Ard Biesheuvel wrote:
On Thu, 23 Jul 2020 at 04:52, Jarkko Sakkinen
wrote:
>
> On Thu, Jul 16, 2020 at 06:49:09PM +0200, Christophe Leroy wrote:
> > Jarkko Sakkinen a écrit :
> >
> > > Rename module_alloc() t
On Thu, Jul 23, 2020 at 03:42:09PM +0300, Ard Biesheuvel wrote:
> On Thu, 23 Jul 2020 at 04:52, Jarkko Sakkinen
> wrote:
> >
> > On Thu, Jul 16, 2020 at 06:49:09PM +0200, Christophe Leroy wrote:
> > > Jarkko Sakkinen a écrit :
> > >
> > > > Rename module_alloc() to text_alloc() and module_memfree
> On 23-Jul-2020, at 8:26 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Thu, Jul 23, 2020 at 11:14:16AM +0530, kajoljain escreveu:
>>
>>
>> On 7/21/20 11:32 AM, kajoljain wrote:
>>>
>>>
>>> On 7/17/20 8:08 PM, Athira Rajeev wrote:
From: Anju T Sudhakar
Add support for perf ex
On Thu, Jul 23, 2020 at 08:47:59PM +0200, pet...@infradead.org wrote:
> On Thu, Jul 23, 2020 at 02:32:36PM -0400, Waiman Long wrote:
> > BTW, do you have any comment on my v2 lock holder cpu info qspinlock patch?
> > I will have to update the patch to fix the reported 0-day test problem, but
> > I
This adds a kernel command line option that can be used to disable GTSE support.
Disabling GTSE implies kernel will make hcalls to invalidate TLB entries.
This was done so that we can do VM migration between configs that enable/disable
GTSE support via hypervisor. To migrate a VM from a system tha
Le 24/07/2020 à 05:03, Bharata B Rao a écrit :
On Thu, Jul 23, 2020 at 01:07:24PM -0700, Ram Pai wrote:
From: Laurent Dufour
When a secure memslot is dropped, all the pages backed in the secure
device (aka really backed by secure memory by the Ultravisor)
should be paged out to a normal page.
On Wed, Jul 22, 2020 at 11:06 PM Atish Patra wrote:
>
> On Wed, Jul 22, 2020 at 1:23 PM Arnd Bergmann wrote:
> >
> > I just noticed that rv32 allows 2GB of lowmem rather than just the usual
> > 768MB or 1GB, at the expense of addressable user memory. This seems
> > like an unusual choice, but I a
On Thu, Jul 23, 2020 at 02:21:11PM +0530, Srikar Dronamraju wrote:
> Current code assumes that cpumask of cpus sharing a l2-cache mask will
> always be a superset of cpu_sibling_mask.
>
> Lets stop that assumption. cpu_l2_cache_mask is a superset of
> cpu_sibling_mask if and only if shared_cache
On Wed, Jul 22, 2020 at 12:27:47PM +0530, Srikar Dronamraju wrote:
> * Gautham R Shenoy [2020-07-22 11:51:14]:
>
> > Hi Srikar,
> >
> > > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> > > index 72f16dc0cb26..57468877499a 100644
> > > --- a/arch/powerpc/kernel/smp.c
> > > +
On Thu, Jul 23, 2020 at 02:21:10PM +0530, Srikar Dronamraju wrote:
> Move topology fixup based on the platform attributes into its own
> function which is called just before set_sched_topology.
>
> Cc: linuxppc-dev
> Cc: LKML
> Cc: Michael Ellerman
> Cc: Nicholas Piggin
> Cc: Anton Blanchard
On Thu, Jul 23, 2020 at 02:21:08PM +0530, Srikar Dronamraju wrote:
> A new sched_domain_topology_level was added just for Power9. However the
> same can be achieved by merging powerpc_topology with power9_topology
> and makes the code more simpler especially when adding a new sched
> domain.
>
> C
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