The seems to be missing quite a lot of details w.r.t allocating
the correct pgtable_t page (huge_pte_alloc()), holding the right
lock (huge_pte_lock()) etc. The vma used is also not a hugetlb VMA.
ppc64 do have runtime checks within CONFIG_DEBUG_VM for most of these.
Hence disable the test on ppc6
pmd_clear() should not be used to clear pmd level pte entries.
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
index 061c19bba7f0..529892b9be2f 100644
--- a/mm/debug
Make sure we call pte accessors with correct lock held.
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable.c | 34 --
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
index 90e9c2d3a092..061c19bba7f
This will help in adding proper locks in a later patch
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable.c | 53 +++
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
index 48475d288df1..90e
Architectures like ppc64 use deposited page table while updating the huge pte
entries.
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
index 644d28861ce9..48475d288
set_pud_at() should not be used to set a pte entry at locations that
already holds a valid pte entry. Architectures like ppc64 don't do TLB
invalidate in set_pud_at() and hence expect it to be used to set locations
that are not a valid PTE.
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable
set_pmd_at() should not be used to set a pte entry at locations that
already holds a valid pte entry. Architectures like ppc64 don't do TLB
invalidate in set_pmd_at() and hence expect it to be used to set locations
that are not a valid PTE.
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable
kernel expect entries to be marked huge before we use set_pud_at().
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
index b6aca2526e01..cd609a212dd4 100644
---
kernel expect entries to be marked huge before we use set_pmd_at().
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
index de8a62d0a931..b6aca2526e01 100644
--- a/mm
Saved write support was added to track the write bit of a pte after marking the
pte protnone. This was done so that AUTONUMA can convert a write pte to protnone
and still track the old write bit. When converting it back we set the pte write
bit correctly thereby avoiding a write fault again. Hence
ppc64 supports huge vmap only with radix translation. Hence use arch helper
to determine the huge vmap support.
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
index 02a7c2
set_pte_at() should not be used to set a pte entry at locations that
already holds a valid pte entry. Architectures like ppc64 don't do TLB
invalidate in set_pte_at() and hence expect it to be used to set locations
that are not a valid PTE.
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable
ppc64 use bit 62 to indicate a pte entry (_PAGE_PTE). Avoid setting that bit in
random value.
Signed-off-by: Aneesh Kumar K.V
---
mm/debug_vm_pgtable.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
index 086309fb9b6f..4c3206
With the hash page table, the kernel should not use pmd_clear for clearing
huge pte entries. Add a DEBUG_VM WARN to catch the wrong usage.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/pow
Hi Andrew, Michal, David
* Andrew Morton [2020-08-06 21:32:11]:
> On Fri, 3 Jul 2020 18:28:23 +0530 Srikar Dronamraju
> wrote:
>
> > > The memory hotplug changes that somehow because you can hotremove numa
> > > nodes and therefore make the nodemask sparse but that is not a common
> > > case.
Hi Srikar,
On Mon, Aug 10, 2020 at 12:48:30PM +0530, Srikar Dronamraju wrote:
> In start_secondary, even if shared_cache was already set, system does a
> redundant match for cpumask. This redundant check can be removed by
> checking if shared_cache is already set.
>
> While here, localize the sib
Le 12/08/2020 à 03:20, Nathan Lynch a écrit :
The drmem lmb list can have hundreds of thousands of entries, and
unfortunately lookups take the form of linear searches. As long as
this is the case, traversals have the potential to monopolize the CPU
and provoke lockup reports, workqueue stalls,
Hello Michael,
Do you suggest any change for this patchset?
Any chance it can get in this merge window?
Best regards,
Leonardo Bras
On Wed, 2020-08-05 at 00:04 -0300, Leonardo Bras wrote:
> There are some devices in which a hypervisor may only allow 1 DMA window
> to exist at a time, and in thos
On 11/8/20 11:41 pm, Daniel Axtens wrote:
+static bool block_rtas_call(int token, int nargs,
+ struct rtas_args *args)
+{
+ int i;
+ const char *reason;
+ char *token_name = rtas_token_name(token);
This code isn't particularly performance critical, bu
Michael Roth writes:
> For a power9 KVM guest with XIVE enabled, running a test loop
> where we hotplug 384 vcpus and then unplug them, the following traces
> can be seen (generally within a few loops) either from the unplugged
> vcpu:
>
> [ 1767.353447] cpu 65 (hwid 65) Ready to die...
> [
Nathan Lynch writes:
> Michael Ellerman writes:
>> One thought, which I possibly should not put in writing, is that we
>> could use the alignment of the pointer as a poor man's substitute for a
>> counter, eg:
>>
>> +static inline struct drmem_lmb *drmem_lmb_next(struct drmem_lmb *lmb)
>> +{
>> +
The drmem lmb list can have hundreds of thousands of entries, and
unfortunately lookups take the form of linear searches. As long as
this is the case, traversals have the potential to monopolize the CPU
and provoke lockup reports, workqueue stalls, and the like unless
they explicitly yield.
Rather
On 2020/8/12 0:32, Jonathan Cameron wrote:
> On Mon, 10 Aug 2020 12:27:24 +1000
> Nicholas Piggin wrote:
>
>> Not tested on x86 or arm64, would appreciate a quick test there so I can
>> ask Andrew to put it in -mm. Other option is I can disable huge vmallocs
>> for them for the time being.
>
> H
On Tue, Aug 11, 2020 at 06:28:39PM +0300, Horia Geantă wrote:
>
> What about, for example, CBC?
> AFAICT cbc(aes) with input length = 0 is valid.
That's just because CBC accepts any input which is a multiple
of blocksize.
> Same for CTR (with the note that blocksize = 1) and several other algorit
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20200811
x86_64 randconfig-a001-20200811
x86_64 randconfig-a003-20200811
x86_64
allmodconfig
powerpc allnoconfig
i386 randconfig-a001-20200811
i386 randconfig-a002-20200811
i386 randconfig-a003-20200811
i386 randconfig-a004-20200811
i386 randconfig-a005-20200811
i386
allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20200811
x86_64 randconfig-a001-20200811
x86_64 randconfig-a003-20200811
x86_64 randconfig-a005-20200811
x86_64 randconfig-a004-20200811
x86_64
Le 03/08/2020 à 09:35, Oliver O'Halloran a écrit :
On Thu, Apr 30, 2020 at 11:15 PM Max Gurtovoy wrote:
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 57d3a6a..9ecc576 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch
On Mon, 10 Aug 2020 12:27:24 +1000
Nicholas Piggin wrote:
> Not tested on x86 or arm64, would appreciate a quick test there so I can
> ask Andrew to put it in -mm. Other option is I can disable huge vmallocs
> for them for the time being.
Hi Nicholas,
For arm64 testing with a Kunpeng920.
I ran
For a power9 KVM guest with XIVE enabled, running a test loop
where we hotplug 384 vcpus and then unplug them, the following traces
can be seen (generally within a few loops) either from the unplugged
vcpu:
[ 1767.353447] cpu 65 (hwid 65) Ready to die...
[ 1767.952096] Querying DEAD? cpu 66 (6
On 8/10/2020 8:03 PM, Eric Biggers wrote:
> On Mon, Aug 10, 2020 at 05:33:39PM +0300, Horia Geantă wrote:
>> On 8/10/2020 4:45 PM, Herbert Xu wrote:
>>> On Mon, Aug 10, 2020 at 10:20:20AM +, Van Leeuwen, Pascal wrote:
With all due respect, but this makes no sense.
>>>
>>> I agree. Th
Michael Ellerman writes:
> Michael Roth writes:
>> Quoting Nathan Lynch (2020-08-07 02:05:09)
> ...
>>> wait_for_cpu_stopped() should be able to accommodate a time-based
>>> warning if necessary, but speaking as a likely recipient of any bug
>>> reports that would arise here, I'm not convinced o
Le 11/08/2020 à 14:07, Michael Ellerman a écrit :
Christophe Leroy writes:
10 files changed, 44 insertions(+), 1 deletion(-)
In general this looks fine.
It's a bit #ifdef heavy. Maybe some of those can be cleaned up a bit
with some wrapper inlines?
Looking at it once more, looks like
If we can't find the address of __end_interrupts, then we still exit
successfully as that is the current behaviour.
Cc: Nicholas Piggin
Signed-off-by: Stephen Rothwell
---
arch/powerpc/tools/unrel_branch_check.sh | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/power
Cc: Nicholas Piggin
Signed-off-by: Stephen Rothwell
---
arch/powerpc/tools/unrel_branch_check.sh | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/tools/unrel_branch_check.sh
b/arch/powerpc/tools/unrel_branch_check.sh
index 54ebd05615d4..4489f16a4
Cc: Nicholas Piggin
Signed-off-by: Stephen Rothwell
---
arch/powerpc/tools/unrel_branch_check.sh | 26 +---
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/tools/unrel_branch_check.sh
b/arch/powerpc/tools/unrel_branch_check.sh
index dc82289b2252.
Also start using sed -E and make all the separate expressions into a
single one with comments. Pull the stripping of condition registers
back into the sed command.
Cc: Nicholas Piggin
Signed-off-by: Stephen Rothwell
---
arch/powerpc/tools/unrel_branch_check.sh | 30
1
We don't use the raw hex instruction dump, so elide it and adjust the
following expressions.
Also use \s instead of [[:space:]] everywhere.
Cc: Nicholas Piggin
Signed-off-by: Stephen Rothwell
---
arch/powerpc/tools/unrel_branch_check.sh | 12 ++--
1 file changed, 6 insertions(+), 6 del
Also some minor style changes.
There should still be no change in behaviour.
Cc: Nicholas Piggin
Signed-off-by: Stephen Rothwell
---
arch/powerpc/tools/unrel_branch_check.sh | 25 +++-
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/tools/unrel_
No functional change
Cc: Nicholas Piggin
Signed-off-by: Stephen Rothwell
---
arch/powerpc/tools/unrel_branch_check.sh | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/tools/unrel_branch_check.sh
b/arch/powerpc/tools/unrel_branch_check.sh
index 6e6a
Michael Ellerman: "who wants to make
arch/powerpc/tools/unrel_branch_check.sh suck less"
This series is based off the current powerpc/next branch and keeps the
same functionaity as the original except that it suppresses some error
messages for early failures that still cause this script to succeed
Le 11/08/2020 à 14:07, Michael Ellerman a écrit :
Christophe Leroy writes:
There is no point in copying floating point regs when there
is no FPU and MATH_EMULATION is not selected.
Yeah I guess you're right. I've never touched a system with neither, but
if such a thing exists then it does
Andrew Donnellan writes:
> On 10/8/20 4:40 pm, Michael Ellerman wrote:
>> Hi ajd,
>>
>> Thanks for taking care of this.
>>
>> I was going to merge this as-is, but given it's fixing a long standing
>> issue there's not really a big rush. So a few comments below.
>
> Thanks for the review.
>
>>>
On Mon, 10 Aug 2020 15:56:23 +0530, Aneesh Kumar K.V wrote:
> On p6 and before we should avoid updating UAMOR SPRN. This resulted
> in boot failure on Nemo board.
Applied to powerpc/fixes.
[1/1] powerpc/pkeys: Fix boot failures with Nemo board (A-EON AmigaOne X1000)
https://git.kernel.org/p
Christophe Leroy writes:
> There is no point in copying floating point regs when there
> is no FPU and MATH_EMULATION is not selected.
Yeah I guess you're right. I've never touched a system with neither, but
if such a thing exists then it does seem silly to copy regs around that
can't be used.
>
Michael Roth writes:
> Quoting Nathan Lynch (2020-08-07 02:05:09)
...
>> wait_for_cpu_stopped() should be able to accommodate a time-based
>> warning if necessary, but speaking as a likely recipient of any bug
>> reports that would arise here, I'm not convinced of the need and I
>> don't know what
Andrew Donnellan writes:
> On 10/8/20 4:40 pm, Michael Ellerman wrote:
>> Hi ajd,
>>
>> Thanks for taking care of this.
>>
>> I was going to merge this as-is, but given it's fixing a long standing
>> issue there's not really a big rush. So a few comments below.
>
> Thanks for the review.
>
>>> d
From: Hou Zhiqiang
The commit 0a121f9bc3f5 ("misc: pci_endpoint_test: Use streaming DMA
APIs for buffer allocation") changed to use streaming DMA APIs, however,
dma_map_single() might not return a 4KB aligned address, so add the
default_data as driver data for Layerscape PCIe controllers to make
From: Xiaowei Bao
Add LS1088a in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in LS1088a.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
drivers/misc/pci_endpoint_test.c
From: Xiaowei Bao
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++
1 file chang
From: Xiaowei Bao
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver
before, because the ls1046a platform don't support the MSIX feature
and msix_capable was always set to false.
Now that add the ls1088a platform with MSIX support, use the doorbell
method to support the MSIX featur
From: Xiaowei Bao
Add PCIe EP mode support for ls1088a and ls2088a, there are some
difference between LS1 and LS2 platform, so refactor the code of
the EP driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Rob Herring
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality
From: Xiaowei Bao
The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.
Signed-off-by: Xiaowei Bao
Reviewed-by: Rob Herring
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch wit
From: Xiaowei Bao
Fix some format issue of the code in EP driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
1 file changed, 2 insertions
From: Xiaowei Bao
Each PF of EP device should have its own MSI or MSIX capabitily
struct, so create a dw_pcie_ep_func struct and move the msi_cap
and msix_cap to this struct from dw_pcie_ep, and manage the PFs
via a list.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase
From: Xiaowei Bao
Add compatible strings for ls1088a and ls2088a.
Signed-off-by: Xiaowei Bao
Acked-by: Rob Herring
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 ++
1 file changed, 2 inserti
From: Xiaowei Bao
Move the function of getting MSI capability to the front of init
function, because the init function of the EP platform driver will use
the return value by the function of getting MSI capability.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqian
From: Xiaowei Bao
Add the doorbell mode of MSI-X in DWC EP driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++
drivers/pci/con
From: Xiaowei Bao
Add multiple PFs support for DWC, due to different PF have different
config space, we use func_conf_select callback function to access
the different PF's config space, the different chip company need to
implement this callback function when use the DWC IP core and intend
to supp
From: Hou Zhiqiang
Add the PCIe EP multiple PF support for DWC and Layerscape, and use
a list to manage the PFs of each PCIe controller; add the doorbell
MSIX function for DWC; and refactor the Layerscape EP driver due to
some difference in Layercape platforms PCIe integration.
Hou Zhiqiang (1):
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
next-test
head: 0a2900256840208c4a4248ff5900ae57990d55dc
commit: 7f24f76bc606cbae1b56a8a445a5353594c3cf18 [33/34] powerpc/smp: Move
ppc_md.cpu_die() to smp_ops.cpu_offline_self()
config: powerpc-randconfig-r024-20200811
On 10/8/20 4:40 pm, Michael Ellerman wrote:
Hi ajd,
Thanks for taking care of this.
I was going to merge this as-is, but given it's fixing a long standing
issue there's not really a big rush. So a few comments below.
Thanks for the review.
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powe
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