Excerpts from Nicholas Piggin's message of November 11, 2020 2:46 pm:
> Excerpts from Christophe Leroy's message of November 10, 2020 9:19 pm:
>>
>>
>> Le 10/11/2020 à 09:34, Nicholas Piggin a écrit :
>>> Excerpts from Christophe Leroy's message of November 6, 2020 6:14 pm:
Le
The hardware trace macros which use the memory provided by memtrace are
able to use trace sizes as small as 16MB. Only memblock aligned values
can be removed from each NUMA node by writing that value to
memtrace/enable in debugfs. This means setting up, say, a 16MB trace is
not possible. To
In Power9, L2/L3 bus events are always available as a
"bank" of 4 events. To obtain the counts for any of the
l2/l3 bus events in a given bank, the user will have to
program PMC4 with corresponding l2/l3 bus event for that
bank.
Commit 59029136d750 ("powerpc/perf: Add constraints for power9 l2/l3
On Tue 03 Nov 09:28 CST 2020, Lee Jones wrote:
> This set is part of a larger effort attempting to clean-up W=1
> kernel builds, which are currently overwhelmingly riddled with
> niggly little warnings.
>
For patches 2, 3, 12, 15, 16, 17, 18, 19, 20, 21, 22 (i.e. the soc/qcom
patches):
Fix the event code for events: branch-instructions (to PM_BR_FIN),
branch-misses (to PM_BR_MPRED_FIN) and cache-misses (to
PM_LD_DEMAND_MISS_L1_FIN) for power10 PMU. Update the
list of generic events with this modified event code.
Export l2l3 events (PM_L2_ST_MISS and PM_L2_ST) and LLC-prefetches
power10 uses bit 9 of the raw event code as RADIX_SCOPE_QUAL.
This bit is used for enabling the radix process events.
Patch fixes the PMU counter support functions to program bit
18 of MMCR1 ( Monitor Mode Control Register1 ) with the
RADIX_SCOPE_QUAL bit value. Since this field is not per-pmc,
Excerpts from Christophe Leroy's message of November 10, 2020 9:31 pm:
>
>
> Le 10/11/2020 à 09:49, Nicholas Piggin a écrit :
>> Excerpts from Christophe Leroy's message of November 7, 2020 8:35 pm:
>>>
>>>
>>> Le 06/11/2020 à 16:59, Nicholas Piggin a écrit :
This series attempts to improve
PowerISA v3.1 introduces new control bit (PMCCEXT) for enabling
secure access to group B PMU registers in problem state when
MMCR0 PMCC=0b00. This patch adds support for MMCR0 PMCCEXT bit
in power10 by enabling this bit during boot and during the PMU
event enable/disable operations when MMCR0
Patchset contains PMU fixes for power10.
This patchset contains 4 patches.
Patch1 includes fix to update event code with radix_scope_qual
bit in power10.
Patch2 updates the event group constraints for L2/L3 and threshold
events in power10.
Patch3 includes the event code changes for l2/l3 events
Excerpts from Christophe Leroy's message of November 10, 2020 9:19 pm:
>
>
> Le 10/11/2020 à 09:34, Nicholas Piggin a écrit :
>> Excerpts from Christophe Leroy's message of November 6, 2020 6:14 pm:
>>>
>>>
>>> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
This also moves the 32s DABR
Excerpts from Christophe Leroy's message of November 10, 2020 9:15 pm:
>
>
> Le 10/11/2020 à 09:29, Nicholas Piggin a écrit :
>> Excerpts from Christophe Leroy's message of November 6, 2020 5:59 pm:
>>>
>>>
>>> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
Make mm fault handlers all just
This reverts commit a0ff72f9f5a780341e7ff5e9ba50a0dad5fa1980.
Since the commit b015f6bc9547 ("powerpc/pseries: Add cpu DLPAR
support for drc-info property"), the 'cpu_drcs' wouldn't be double
freed when the 'cpus' node not found.
So we needn't apply this patch, otherwise, the memory will be
On 11/6/20 4:19 AM, Michael Ellerman wrote:
> Cédric Le Goater writes:
>> When accessing the ESB page of a source interrupt, the fault handler
>> will retrieve the page address from the XIVE interrupt 'xive_irq_data'
>> structure. If the associated KVM XIVE interrupt is not valid, that is
>> not
On Mon, 2 Nov 2020 18:18:10 +0200, Viorel Suman (OSS) wrote:
> The break condition copied by mistake as same
> as loop condition in the previous version, but must
> be the opposite. So fix it.
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
On 11/9/20 11:26 PM, Mauro Carvalho Chehab wrote:
> Hi Jonathan,
>
> Let's view ABI from the PoV of a system admin that doesn't know
> yet about a certain ABI symbol.
>
> He'll try to seek for the symbol, more likely using the HTML
> documentation. Only very senior system admins might try to
From: zhangxiaoxu
If the cpus nodes not exist, we lost to free the 'cpu_drcs', which
will leak memory.
Fixes: a0ff72f9f5a7 ("powerpc/pseries/hotplug-cpu: Remove double free in error
path")
Reported-by: Hulk Robot
Signed-off-by: zhangxiaoxu
---
arch/powerpc/platforms/pseries/hotplug-cpu.c |
On 11/10/20 6:08 AM, Nathan Lynch wrote:
> Zhang Xiaoxu writes:
>> From: zhangxiaoxu
>>
>> If the cpus nodes not exist, we lost to free the 'cpu_drcs', which
>> will leak memory.
>>
>> Fixes: a0ff72f9f5a7 ("powerpc/pseries/hotplug-cpu: Remove double free in
>> error path")
>> Reported-by: Hulk
On 11/10/2020 7:20 PM, Rob Herring wrote:
> On Mon, Nov 9, 2020 at 4:11 PM Rob Herring wrote:
>>
>> On Mon, 09 Nov 2020 12:46:35 +0200, Laurentiu Tudor wrote:
>>> From: Ionut-robert Aron
>>>
>>> Convert fsl,qoriq-mc to YAML in order to automate the verification
>>> process of dts files. In
On Mon, Nov 9, 2020 at 4:11 PM Rob Herring wrote:
>
> On Mon, 09 Nov 2020 12:46:35 +0200, Laurentiu Tudor wrote:
> > From: Ionut-robert Aron
> >
> > Convert fsl,qoriq-mc to YAML in order to automate the verification
> > process of dts files. In addition, update MAINTAINERS accordingly
> > and,
It seems noone is going to get involved in the discussion. Therefore I'll
fix the patch in the way I suggested in my previous message. Alas I'll
have to remove the reviewed-by tags of Rob from some patches.
-Sergey
On Mon, Oct 26, 2020 at 07:46:49PM +0300, Serge Semin wrote:
> Folks, any comment
Zhang Xiaoxu writes:
> From: zhangxiaoxu
>
> If the cpus nodes not exist, we lost to free the 'cpu_drcs', which
> will leak memory.
>
> Fixes: a0ff72f9f5a7 ("powerpc/pseries/hotplug-cpu: Remove double free in
> error path")
> Reported-by: Hulk Robot
> Signed-off-by: zhangxiaoxu
> ---
>
On 10/11/20 10:19 pm, xiakaixu1...@gmail.com wrote:
From: Kaixu Xia
Fix coccicheck warning:
./arch/powerpc/platforms/powernv/pci-sriov.c:443:7-10: WARNING: Unsigned
expression compared with zero: win < 0
./arch/powerpc/platforms/powernv/pci-sriov.c:462:7-10: WARNING: Unsigned
expression
Le 10/11/2020 à 09:49, Nicholas Piggin a écrit :
Excerpts from Christophe Leroy's message of November 7, 2020 8:35 pm:
Le 06/11/2020 à 16:59, Nicholas Piggin a écrit :
This series attempts to improve the speed of interrupts and system calls
in two major ways.
Firstly, the SRR/HSRR
From: Kaixu Xia
Fix coccicheck warning:
./arch/powerpc/platforms/powernv/pci-sriov.c:443:7-10: WARNING: Unsigned
expression compared with zero: win < 0
./arch/powerpc/platforms/powernv/pci-sriov.c:462:7-10: WARNING: Unsigned
expression compared with zero: win < 0
Reported-by: Tosk Robot
Le 10/11/2020 à 09:34, Nicholas Piggin a écrit :
Excerpts from Christophe Leroy's message of November 6, 2020 6:14 pm:
Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
This also moves the 32s DABR match to C.
Is there a real benefit doing this ?
Oh I missed doing it, but yes I think
Le 10/11/2020 à 09:29, Nicholas Piggin a écrit :
Excerpts from Christophe Leroy's message of November 6, 2020 5:59 pm:
Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
Make mm fault handlers all just take the pt_regs * argument and load
DAR/DSISR from that. Make those that return a value
Le 10/11/2020 à 09:53, Wang Qing a écrit :
PREEMPT_RT is a separate preemption model, CONFIG_PREEMPT will
be disabled when CONFIG_PREEMPT_RT is enabled, so we need
to add CONFIG_PREEMPT_RT output to __die().
Signed-off-by: Wang Qing
Reviewed-by: Christophe Leroy
Changes in v3:
-
On 09.11.20 20:21, Mike Rapoport wrote:
From: Mike Rapoport
For architectures that enable ARCH_HAS_SET_MEMORY having the ability to
verify that a page is mapped in the kernel direct map can be useful
regardless of hibernation.
Add RISC-V implementation of kernel_page_present(), update its
PREEMPT_RT is a separate preemption model, CONFIG_PREEMPT will
be disabled when CONFIG_PREEMPT_RT is enabled, so we need
to add CONFIG_PREEMPT_RT output to __die().
Signed-off-by: Wang Qing
Changes in v3:
- Fix typo issue.
Changes in v2:
- Modify as Christophe suggested.
---
Excerpts from Christophe Leroy's message of November 7, 2020 8:35 pm:
>
>
> Le 06/11/2020 à 16:59, Nicholas Piggin a écrit :
>> This series attempts to improve the speed of interrupts and system calls
>> in two major ways.
>>
>> Firstly, the SRR/HSRR registers do not need to be reloaded if they
On Mon, Nov 09 2020 at 20:59, Ira Weiny wrote:
> On Tue, Nov 10, 2020 at 02:13:56AM +0100, Thomas Gleixner wrote:
> Also, we can convert the new memcpy_*_page() calls to kmap_local() as well.
> [For now my patch just uses kmap_atomic().]
>
> I've not looked at all of the patches in your latest
Excerpts from Christophe Leroy's message of November 9, 2020 2:57 am:
> In head_64.S, we have two places using RFI to return to
> kernel. Use RFI_TO_KERNEL instead.
>
> They are the two only places using RFI on book3s/64, so
> the RFI macro can go away.
Looks good to me.
Acked-by: Nicholas
Excerpts from Christophe Leroy's message of November 7, 2020 7:43 pm:
>
>
> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
>> Christophe asked about doing this, most of the code is still in
>> asm but maybe it's slightly nicer? I don't know if it's worthwhile.
>
> Heu... I don't think I was
Excerpts from Christophe Leroy's message of November 6, 2020 6:14 pm:
>
>
> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
>> This also moves the 32s DABR match to C.
>
> Is there a real benefit doing this ?
Oh I missed doing it, but yes I think bad_page_fault and do_break should
probably be
Excerpts from Christophe Leroy's message of November 6, 2020 5:59 pm:
>
>
> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
>> Make mm fault handlers all just take the pt_regs * argument and load
>> DAR/DSISR from that. Make those that return a value return long.
>>
>> This is done to make the
Excerpts from Christophe Leroy's message of November 7, 2020 6:15 pm:
>
>
> Le 07/11/2020 à 04:23, Nicholas Piggin a écrit :
>> ISA v2.06 (POWER7 and up) as well as e6500 support lbarx and lwarx.
>> Add a compile option that allows code to use it, and add support in
>> cmpxchg and xchg 8 and 16
On Tue, Nov 10, 2020 at 04:02:47PM +0800, Wang Qing wrote:
> PREEMPT_RT is a separate preemption model, CONFIG_PRTTMPT will
Minor typo on this line with your config option :(
PREEMPT_RT is a separate preemption model, CONFIG_PRTTMPT will
be disabled when CONFIG_PREEMPT_RT is enabled, so you need
to add CONFIG_PREEMPT_RT judgments to __die().
Signed-off-by: Wang Qing
Changes in v2:
- Modify as Christophe suggested.
---
arch/powerpc/kernel/traps.c | 3 ++-
1 file
Le 10/11/2020 à 09:02, Wang Qing a écrit :
PREEMPT_RT is a separate preemption model, CONFIG_PRTTMPT will
s/CONFIG_PRTTMPT/CONFIG_PREEMPT
be disabled when CONFIG_PREEMPT_RT is enabled, so you need
to add CONFIG_PREEMPT_RT judgments to __die().
Signed-off-by: Wang Qing
Otherwise
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