On 05/12/2020 22.27, Jakub Kicinski wrote:
> On Sat, 5 Dec 2020 22:11:39 +0100 Rasmus Villemoes wrote:
>>> Looks like a nice clean up on a quick look.
>>>
>>> Please separate patches 1 and 11 (which are the two bug fixes I see)
>>
>> I think patch 2 is a bug fix as well, but I'd like someone from
Hi "Gautham,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on powerpc/next]
[also build test WARNING on v5.10-rc7 next-20201209]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '
On Wed, Dec 09, 2020 at 03:15:42PM +1100, Paul Mackerras wrote:
> On Mon, Oct 19, 2020 at 04:56:41PM +0530, Bharata B Rao wrote:
> > Implements H_RPT_INVALIDATE hcall and supports only nested case
> > currently.
> >
> > A KVM capability KVM_CAP_RPT_INVALIDATE is added to indicate the
> > support f
On Sat, 05 Dec 2020 18:24:19 +0300, Serge Semin wrote:
> The DWC USB3 driver and some DTS files like Exynos 5250, Keystone k2e, etc
> expects the DWC USB3 DT node to have the compatible string with the
> "synopsys" vendor prefix. Let's add the corresponding compatible string to
> the controller DT
On Sat, 05 Dec 2020 18:24:08 +0300, Serge Semin wrote:
> There can be three distinctive types of the USB controllers: USB hosts,
> USB peripherals/gadgets and USB OTG, which can switch from one role to
> another. In order to have that hierarchy handled in the DT binding files,
> we need to collect
On Sat, Dec 05, 2020 at 08:17:30PM +0100, Rasmus Villemoes wrote:
> This removes the explicit NULL checks, and allows us to stop storing
> at least some of the _offset values separately.
>
> Signed-off-by: Rasmus Villemoes
This seems to rely on one of the missing patches. Please don't split
patc
On Sat, Dec 05, 2020 at 08:17:24PM +0100, Rasmus Villemoes wrote:
> All the buffers and registers are already set up appropriately for an
> MTU slightly above 1500, so we just need to expose this to the
> networking stack. AFAICT, there's no need to implement .ndo_change_mtu
> when the receive buff
Hi "Gautham,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v5.10-rc7 next-20201209]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base'
On Mon, 7 Dec 2020 16:58:01 + (UTC), Christophe Leroy wrote:
> Since commit c33165253492 ("powerpc: use non-set_fs based maccess
> routines"), userspace access is not granted anymore when using
> copy_from_kernel_nofault()
>
> However, kthread_probe_data() uses copy_from_kernel_nofault()
> to
Christophe Leroy writes:
> Le 09/12/2020 à 11:43, Michael Ellerman a écrit :
>> Christophe Leroy writes:
>>> There is no big poing in not pinning kernel text anymore, as now
>>> we can keep pinned TLB even with things like DEBUG_PAGEALLOC.
>>>
>>> Remove CONFIG_PIN_TLB_TEXT, making it always righ
Stephen Rothwell writes:
> Hi Michael,
>
> On Wed, 09 Dec 2020 15:44:35 +1100 Michael Ellerman
> wrote:
>>
>> They should really be in DATA_DATA or similar shouldn't they?
>
> No other architecture appears t need them ...
Any arch with orphan-handling=warn should see them I thought?
cheers
Hi "Gautham,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on powerpc/next]
[also build test WARNING on v5.10-rc7 next-20201209]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '
On Wed, Dec 09, 2020 at 11:43:59PM +0200, Vladimir Oltean wrote:
> On Wed, Dec 09, 2020 at 03:34:49PM -0600, Bjorn Helgaas wrote:
> > On Wed, Dec 09, 2020 at 11:20:17PM +0200, Vladimir Oltean wrote:
> > > On Wed, Dec 09, 2020 at 02:59:13PM -0600, Bjorn Helgaas wrote:
> > > > Yep, that's the theory.
On Wed, Dec 09, 2020 at 03:34:49PM -0600, Bjorn Helgaas wrote:
> On Wed, Dec 09, 2020 at 11:20:17PM +0200, Vladimir Oltean wrote:
> > On Wed, Dec 09, 2020 at 02:59:13PM -0600, Bjorn Helgaas wrote:
> > > Yep, that's the theory. Thanks for testing it!
> >
> > Testing what? I'm not following.
>
> You
On Wed, Dec 09, 2020 at 11:20:17PM +0200, Vladimir Oltean wrote:
> On Wed, Dec 09, 2020 at 02:59:13PM -0600, Bjorn Helgaas wrote:
> > Yep, that's the theory. Thanks for testing it!
>
> Testing what? I'm not following.
You posted a patch that you said fixed the bug for you. The fix is
exactly th
Hi Christophe,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on next-20201209]
[cannot apply to robh/for-next linus/master mpe/next v5.10-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting
On Wed, Dec 09, 2020 at 02:59:13PM -0600, Bjorn Helgaas wrote:
> Yep, that's the theory. Thanks for testing it!
Testing what? I'm not following.
On Wed, Dec 09, 2020 at 10:29:04PM +0200, Vladimir Oltean wrote:
> On Wed, Dec 09, 2020 at 04:40:52PM +0100, Michael Walle wrote:
> > Hopefully my mail client won't mess up the output that much.
>
> I can reproduce on my LS1028A as well. The following fixes the bug for
> me. I did not follow the d
On Wed, Dec 09, 2020 at 04:40:52PM +0100, Michael Walle wrote:
> Hopefully my mail client won't mess up the output that much.
I can reproduce on my LS1028A as well. The following fixes the bug for
me. I did not follow the discussion and see if it is helpful for others.
I don't understand how the b
On Tue, Dec 08, 2020 at 11:01:57PM +1100, Stephen Rothwell wrote:
> Hi Stephen,
>
> On Fri, 4 Dec 2020 21:00:00 +1100 Stephen Rothwell
> wrote:
> >
> > Hi all,
> >
> > After merging the akpm tree, today's linux-next build (powerpc
> > allyesconfig) produced warnings like this:
> >
> > ld: warn
From: "Gautham R. Shenoy"
On platforms which have the "ibm,thread-groups" property, the per-cpu
variable cpu_l1_cache_map keeps a track of which group of threads
within the same core share the L1 cache, Instruction and Data flow.
This patch renames the variable to "thread_group_l1_cache_map" to
From: "Gautham R. Shenoy"
The "ibm,thread-groups" device-tree property is an array that is used
to indicate if groups of threads within a core share certain
properties. It provides details of which property is being shared by
which groups of threads. This array can encode information about
multip
From: "Gautham R. Shenoy"
On POWER systems, groups of threads within a core sharing the L2-cache
can be indicated by the "ibm,thread-groups" property array with the
identifier "2".
This patch adds support for detecting this, and when present, populate
the populating the cpu_l2_cache_mask of ever
From: "Gautham R. Shenoy"
On POWER platforms where only some groups of threads within a core
share the L2-cache (indicated by the ibm,thread-groups device-tree
property), we currently print the incorrect shared_cpu_map/list for
L2-cache in the sysfs.
This patch reports the correct shared_cpu_map
From: "Gautham R. Shenoy"
Hi,
This is the v2 of the patchset to extend parsing of "ibm,thread-groups" property
to discover the Shared-L2 cache information.
The v1 can be found here :
https://lore.kernel.org/linuxppc-dev/1607057327-29822-1-git-send-email-...@linux.vnet.ibm.com/T/#m0fabffa1ea1a28
From: "Gautham R. Shenoy"
init_thread_group_l1_cache_map() initializes the per-cpu cpumask
thread_group_l1_cache_map with the core-siblings which share L1 cache
with the CPU. Make this function generic to the cache-property (L1 or
L2) and update a suitable mask. This is a preparatory patch for th
On 12/9/20 5:39 AM, Aneesh Kumar K.V wrote:
> Cédric Le Goater writes:
>
>> The 'chip_id' field of the XIVE CPU structure is used to choose a
>> target for a source located on the same chip when possible. This field
>> is assigned on the PowerNV platform using the "ibm,chip-id" property
>> on pSe
On 12/9/20 4:50 PM, Greg Kurz wrote:
> On Tue, 8 Dec 2020 16:11:18 +0100
> Cédric Le Goater wrote:
>
>> Full state of the Linux interrupt descriptors can be dumped under
>> debugfs when compiled with CONFIG_GENERIC_IRQ_DEBUGFS. Add support for
>> the XIVE interrupt controller.
>>
>> Signed-off-by
On Tue, 8 Dec 2020 16:11:23 +0100
Cédric Le Goater wrote:
> Previous patches removed the need of the first argument which was a
> hack for Firwmware EOI. Remove it and flatten the routine which has
> became simpler.
>
> Signed-off-by: Cédric Le Goater
> ---
Much nicer indeed.
Reviewed-by: Gre
On Tue, 8 Dec 2020 16:11:18 +0100
Cédric Le Goater wrote:
> Full state of the Linux interrupt descriptors can be dumped under
> debugfs when compiled with CONFIG_GENERIC_IRQ_DEBUGFS. Add support for
> the XIVE interrupt controller.
>
> Signed-off-by: Cédric Le Goater
> ---
> arch/powerpc/sysde
Am 2020-12-09 15:57, schrieb Bjorn Helgaas:
[..]
Can you try the following just to get started?
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 46935695cfb9..569a45727bc7 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -79,6 +79,7 @@ int pci_generic_config_read(str
On Tue, 8 Dec 2020 16:11:24 +0100
Cédric Le Goater wrote:
> Introduce a vp_err() macro to standardize error reporting.
>
> Signed-off-by: Cédric Le Goater
> ---
Reviewed-by: Greg Kurz
> arch/powerpc/sysdev/xive/native.c | 28
> 1 file changed, 16 insertions(+),
On Tue, 8 Dec 2020 16:11:22 +0100
Cédric Le Goater wrote:
> This flag was used to support the P9 DD1 and we have stopped
> supporting this CPU when DD2 came out. See skiboot commit:
>
> https://github.com/open-power/skiboot/commit/0b0d15e3c170
>
> Also, remove eoi handler which is now unused.
On Tue, 8 Dec 2020 16:11:21 +0100
Cédric Le Goater wrote:
> This flag was used to support the PHB4 LSIs on P9 DD1 and we have
> stopped supporting this CPU when DD2 came out. See skiboot commit:
>
> https://github.com/open-power/skiboot/commit/0b0d15e3c170
>
> Signed-off-by: Cédric Le Goater
On Wed, Dec 09, 2020 at 02:08:00PM +0100, Michael Walle wrote:
> [+ Vladimir and Alex]
>
> Am 2020-12-09 13:36, schrieb Bjorn Helgaas:
> > On Tue, Dec 08, 2020 at 04:41:50PM +0100, Michael Walle wrote:
> > > >On Sun, 29 Nov 2020 23:07:38 +, Krzysztof Wilczyński wrote:
> > > >> Unify ECAM-relat
Ravi Bangoria writes:
> On powerpc, L1 hypervisor takes help of L0 using H_ENTER_NESTED
> hcall to load L2 guest state in cpu. L1 hypervisor prepares the
> L2 state in struct hv_guest_state and passes a pointer to it via
> hcall. Using that pointer, L0 reads/writes that state directly
> from/to L
Now that 40x platforms have gone, remove support
for 40x in the core of powerpc arch.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 8 +-
arch/powerpc/Kconfig.debug | 13 -
arch/powerpc/Makefile| 1 -
arch/powerp
CONFIG_4xx was corresponding to CONFIG_40x | CONFIG_44x.
As CONFIG_40x is gone, CONFIG_4xx and CONFIG_44x are now equivalent.
And CONFIG_BOOKE is also set when CONFIG_44x is set.
Replace (CONFIG_4xx | CONFIG_BOOKE) by CONFIG_BOOKE
Replace other CONFIG_4xx by CONFIG_44x
Remove CONFIG_4xx.
Signed-
Only 44x uses 4xx now, so only keep one directory.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/44x/Makefile | 9 +++-
arch/powerpc/platforms/{4xx => 44x}/cpm.c | 0
arch/powerpc/platforms/{4xx => 44x}/gpio.c| 0
.../powerpc/platforms/{4xx => 44x}/hsta_msi.
40x platforms have been orphaned for many years.
Remove them.
Signed-off-by: Christophe Leroy
---
Resend with correct Author
---
MAINTAINERS | 1 -
arch/powerpc/configs/40x/acadia_defconfig | 61
arch/powerpc/configs/40x/kilauea_defconfig | 6
Remove 40x platforms from the boot directory.
Signed-off-by: Christophe Leroy
---
arch/powerpc/boot/4xx.c | 266 -
arch/powerpc/boot/4xx.h | 4 -
arch/powerpc/boot/Makefile | 11 -
arch/powerpc/boot/cuboot-acadia.c | 171 ---
arch/pow
[+ Vladimir and Alex]
Am 2020-12-09 13:36, schrieb Bjorn Helgaas:
On Tue, Dec 08, 2020 at 04:41:50PM +0100, Michael Walle wrote:
>On Sun, 29 Nov 2020 23:07:38 +, Krzysztof Wilczyński wrote:
>> Unify ECAM-related constants into a single set of standard constants
>> defining memory address sh
From: Christophe Leroy
CONFIG_4xx was corresponding to CONFIG_40x | CONFIG_44x.
As CONFIG_40x is gone, CONFIG_4xx and CONFIG_44x are now equivalent.
And CONFIG_BOOKE is also set when CONFIG_44x is set.
Replace (CONFIG_4xx | CONFIG_BOOKE) by CONFIG_BOOKE
Replace other CONFIG_4xx by CONFIG_44x
Re
From: Christophe Leroy
40x platforms have been orphaned for many years.
Remove them.
Signed-off-by: Christophe Leroy
---
MAINTAINERS | 1 -
arch/powerpc/configs/40x/acadia_defconfig | 61
arch/powerpc/configs/40x/kilauea_defconfig | 69
From: Christophe Leroy
Only 44x uses 4xx now, so only keep one directory.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/44x/Makefile | 9 +++-
arch/powerpc/platforms/{4xx => 44x}/cpm.c | 0
arch/powerpc/platforms/{4xx => 44x}/gpio.c| 0
.../powerpc/platfor
From: Christophe Leroy
Now that 40x platforms have gone, remove support
for 40x in the core of powerpc arch.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 8 +-
arch/powerpc/Kconfig.debug | 13 -
arch/powerpc/Makefile
From: Christophe Leroy
Remove 40x platforms from the boot directory.
Signed-off-by: Christophe Leroy
---
arch/powerpc/boot/4xx.c | 266 -
arch/powerpc/boot/4xx.h | 4 -
arch/powerpc/boot/Makefile | 11 -
arch/powerpc/boot/cuboot-acadia.c |
On Tue, Dec 08, 2020 at 04:41:50PM +0100, Michael Walle wrote:
> >On Sun, 29 Nov 2020 23:07:38 +, Krzysztof Wilczyński wrote:
> >> Unify ECAM-related constants into a single set of standard constants
> >> defining memory address shift values for the byte-level address that can
> >> be used when
Le 09/12/2020 à 11:43, Michael Ellerman a écrit :
Christophe Leroy writes:
There is no big poing in not pinning kernel text anymore, as now
we can keep pinned TLB even with things like DEBUG_PAGEALLOC.
Remove CONFIG_PIN_TLB_TEXT, making it always right.
Signed-off-by: Christophe Leroy
---
Hi Enrico,
On Wed, Dec 09, 2020 at 12:11:36PM +0100, Enrico Weigelt, metux IT consult
wrote:
> On 08.12.20 16:54, Laurent Pinchart wrote:
> >> diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c
> >> b/drivers/usb/gadget/udc/atmel_usba_udc.c
> >> index 2b893bceea45..4834fafb3f70 100644
> >> ---
On 08.12.20 16:54, Laurent Pinchart wrote:
Hi,
>> diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c
>> b/drivers/usb/gadget/udc/atmel_usba_udc.c
>> index 2b893bceea45..4834fafb3f70 100644
>> --- a/drivers/usb/gadget/udc/atmel_usba_udc.c
>> +++ b/drivers/usb/gadget/udc/atmel_usba_udc.c
>> @@ -
Christophe Leroy writes:
> There is no big poing in not pinning kernel text anymore, as now
> we can keep pinned TLB even with things like DEBUG_PAGEALLOC.
>
> Remove CONFIG_PIN_TLB_TEXT, making it always right.
>
> Signed-off-by: Christophe Leroy
> ---
> arch/powerpc/Kconfig | 3
Hi all,
On Tue, 8 Dec 2020 23:01:57 +1100 Stephen Rothwell
wrote:
>
> I will try the following patch tomorrow:
>
> From: Stephen Rothwell
> Date: Tue, 8 Dec 2020 22:58:24 +1100
> Subject: [PATCH] powerpc: Add .data..Lubsan_data*/.data..Lubsan_type*
> sections explicitly
>
> Similarly to comm
* Gautham R Shenoy [2020-12-08 23:12:37]:
>
> > For L2 we have thread_group_l2_cache_map to store the tasks from the thread
> > group. but cpu_l2_cache_map for keeping track of tasks.
>
> >
> > I think we should do some renaming to keep the names consistent.
> > I would say probably say move
On Wed, Dec 09, 2020 at 02:09:21PM +0530, Srikar Dronamraju wrote:
> * Gautham R Shenoy [2020-12-08 23:26:47]:
>
> > > The drawback of this is even if cpus 0,2,4,6 are released L1 cache will
> > > not
> > > be released. Is this as expected?
> >
> > cacheinfo populates the cache->shared_cpu_map
On Wed, Dec 09, 2020 at 02:05:41PM +0530, Srikar Dronamraju wrote:
> * Gautham R Shenoy [2020-12-08 22:55:40]:
>
> > >
> > > NIT:
> > > tglx mentions in one of his recent comments to try keep a reverse fir tree
> > > ordering of variables where possible.
> >
> > I suppose you mean moving the lo
* Gautham R Shenoy [2020-12-08 23:26:47]:
> > The drawback of this is even if cpus 0,2,4,6 are released L1 cache will not
> > be released. Is this as expected?
>
> cacheinfo populates the cache->shared_cpu_map on the basis of which
> CPUs share the common device-tree node for a particular cache.
* Gautham R Shenoy [2020-12-08 22:55:40]:
> >
> > NIT:
> > tglx mentions in one of his recent comments to try keep a reverse fir tree
> > ordering of variables where possible.
>
> I suppose you mean moving the longer local variable declarations to to
> the top and shorter ones to the bottom. Th
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