* C?dric Le Goater [2021-03-12 15:31:54]:
> Initial commit 15863ff3b8da ("powerpc: Make chip-id information
> available to userspace") introduce a cpu_to_chip_id() routine for the
> PowerNV platform using the "ibm,chip-id" property to query the chip id
> of a CPU. But PAPR does not specify such
On Thu, 4 Mar 2021 17:28:44 +0800, Jiapeng Chong wrote:
> Fix the following coccicheck warnings:
>
> ./drivers/scsi/ibmvscsi/ibmvfc.c:3483:60-61: WARNING opportunity for
> kobj_to_dev().
Applied to 5.13/scsi-queue, thanks!
[1/1] scsi: ibmvfc: Switch to using the new API kobj_to_dev()
Excerpts from Davidlohr Bueso's message of March 9, 2021 11:59 am:
> 49a7d46a06c3 (powerpc: Implement smp_cond_load_relaxed()) added
> busy-waiting pausing with a preferred SMT priority pattern, lowering
> the priority (reducing decode cycles) during the whole loop slowpath.
>
> However, data
warning: symbol 'rfi_flush' was not declared.
warning: symbol 'entry_flush' was not declared.
warning: symbol 'uaccess_flush' was not declared.
We found warnings above in arch/powerpc/kernel/setup_64.c by using
sparse tool.
Define 'entry_flush' and 'uaccess_flush' as static because they are not
On Tue, 2021-03-16 at 14:17 +1100, Jordan Niethe wrote:
> setup_text_poke_area() is a late init call so it runs before
> mark_rodata_ro() and after the init calls. This lets all the init
> code
> patching simply write to their locations. In the future, kprobes is
> going to allocate its
Excerpts from Daniel Axtens's message of March 12, 2021 3:45 pm:
> Nicholas Piggin writes:
>
>> System calls / hcalls have a different calling convention than
>> other interrupts, so there is code in the KVMTEST to massage these
>> into the same form as other interrupt handlers.
>>
>> Move this
From: Christophe Leroy
Use set_memory_attr() instead of the PPC32 specific change_page_attr()
change_page_attr() was checking that the address was not mapped by
blocks and was handling highmem, but that's unneeded because the
affected pages can't be in highmem and block mapping verification
is
From: Christophe Leroy
In addition to the set_memory_xx() functions which allows to change
the memory attributes of not (yet) used memory regions, implement a
set_memory_attr() function to:
- set the final memory protection after init on currently used
kernel regions.
- enable/disable kernel
From: Russell Currey
skiroot_defconfig is the only powerpc defconfig with STRICT_KERNEL_RWX
enabled, and if you want memory protection for kernel text you'd want it
for modules too, so enable STRICT_MODULE_RWX there.
Acked-by: Joel Stanley
Signed-off-by: Russell Currey
Signed-off-by: Jordan
From: Russell Currey
To enable strict module RWX on powerpc, set:
CONFIG_STRICT_MODULE_RWX=y
You should also have CONFIG_STRICT_KERNEL_RWX=y set to have any real
security benefit.
ARCH_HAS_STRICT_MODULE_RWX is set to require ARCH_HAS_STRICT_KERNEL_RWX.
This is due to a quirk in
From: Russell Currey
Very rudimentary, just
echo 1 > [debugfs]/check_wx_pages
and check the kernel log. Useful for testing strict module RWX.
Updated the Kconfig entry to reflect this.
Also fixed a typo.
Reviewed-by: Kees Cook
Signed-off-by: Russell Currey
Signed-off-by: Jordan
From: Russell Currey
With CONFIG_STRICT_KERNEL_RWX=y and CONFIG_KPROBES=y, there will be one
W+X page at boot by default. This can be tested with
CONFIG_PPC_PTDUMP=y and CONFIG_PPC_DEBUG_WX=y set, and checking the
kernel log during boot.
Add an arch specific insn page allocator which returns
setup_text_poke_area() is a late init call so it runs before
mark_rodata_ro() and after the init calls. This lets all the init code
patching simply write to their locations. In the future, kprobes is
going to allocate its instruction pages RO which means they will need
setup_text__poke_area() to
From: Russell Currey
The set_memory_{ro/rw/nx/x}() functions are required for STRICT_MODULE_RWX,
and are generally useful primitives to have. This implementation is
designed to be completely generic across powerpc's many MMUs.
It's possible that this could be optimised to be faster for
On Wed, 10 Mar 2021 19:22:12 -0600, Tyrel Datwyler wrote:
> The buffer for negotiating channel setup is DMA allocated at device
> probe time. However, the remove path fails to free this allocation which
> will prevent the hypervisor from releasing the virtual device in the
> case of a hotplug
allnoconfig
x86_64 randconfig-a006-20210315
x86_64 randconfig-a001-20210315
x86_64 randconfig-a005-20210315
x86_64 randconfig-a004-20210315
x86_64 randconfig-a002-20210315
x86_64 randconfig-a003
allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210315
x86_64 randconfig
allnoconfig
x86_64 randconfig-a006-20210315
x86_64 randconfig-a001-20210315
x86_64 randconfig-a005-20210315
x86_64 randconfig-a004-20210315
x86_64 randconfig-a002-20210315
x86_64 randconfig-a003-20210315
i386
Hi!
On Mon, Mar 15, 2021 at 02:41:59PM +1100, Michael Ellerman wrote:
> The ".machine" directive allows changing the machine for which code is
> being generated. It's equivalent to passing an -mcpu option on the
> command line.
>
> Although it can be useful, it's generally a bad idea because it
Excerpts from Nathan Lynch's message of March 15, 2021 6:00 pm:
> pseries VMs in shared processor mode are susceptible to failed
> migrations becasue stray H_PRODs from the paravirt spinlock
> implementation can bump threads out of joining state before the
> suspend has occurred. Fix this by
Dear Cédric Le Goater and Christophe Leroy,
Thanks for all your suggestions! I'll pick them in my patch and resent
it soon.
Thanks again.
在 2021/3/15 21:14, Cédric Le Goater 写道:
On 3/15/21 2:01 PM, Christophe Leroy wrote:
Le 15/03/2021 à 13:57, Cédric Le Goater a écrit :
On 3/15/21
Paul Menzel writes:
> Am 15.03.21 um 08:53 schrieb Michael Ellerman:
>> Paul Menzel writes:
>
>>> On the POWER8 system IBM S822LC, Linux 5.12-rc2+ logs the errors below.
>>
>> That's a bare metal system, you can see that from the line "Using
>> PowerNV machine description" in the boot log.
>>
The vio bus is a fake bus, which we use on pseries LPARs (guests) to
discover devices provided by the hypervisor. There's no need or sense
in creating the vio bus on bare metal systems.
Which is why commit 4336b9337824 ("powerpc/pseries: Make vio and
ibmebus initcalls pseries specific") made the
On Mon, Mar 15, 2021 at 04:38:52PM +, David Laight wrote:
> From: Rasmus Villemoes
> > Sent: 15 March 2021 16:24
> > On 12/03/2021 03.29, Segher Boessenkool wrote:
> > > On Tue, Mar 09, 2021 at 06:19:30AM +, Christophe Leroy wrote:
> > >> With some defconfig including
On Mon, Mar 15, 2021 at 05:23:44PM +0100, Rasmus Villemoes wrote:
> On 12/03/2021 03.29, Segher Boessenkool wrote:
> > On Tue, Mar 09, 2021 at 06:19:30AM +, Christophe Leroy wrote:
> >> With some defconfig including CONFIG_CC_OPTIMIZE_FOR_SIZE,
> >> (for instance mvme5100_defconfig and
On Mon, Mar 15, 2021 at 01:22:09PM +0530, Athira Rajeev wrote:
SNIP
> +
> +static char *setup_dynamic_sort_keys(char *str)
> +{
> + unsigned int j;
> +
> + if (sort__mode == SORT_MODE__MEMORY)
> + for (j = 0; j < ARRAY_SIZE(dynamic_sort_keys_mem); j++)
> +
Change the default PPR to userspace to 4 (medium), matching the
normal kernel PPR.
This allows system calls and user interrupts to avoid setting PPR on
entry and exit, providing a significant speedup.
This is a change to the user environment. The problem with changing
the kernel to match
Similarly to the system call change in the previous patch, the mtmsrd to
enable RI can be combined with the mtmsrd to enable EE for interrupts
which enable the latter, which tends to be the important synchronous
interrupts (i.e., page faults).
Do this by enabling EE and RI together at the
This extends the MSR[RI]=0 window a little further into the system
call in order to pair RI and EE enabling with a single mtmsrd.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 2 --
arch/powerpc/kernel/interrupt_64.S | 6 +++---
2 files changed, 3 insertions(+), 5
64e does not have a PPR register.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/ptrace.h | 4 +++-
arch/powerpc/kernel/asm-offsets.c | 2 ++
arch/powerpc/kernel/interrupt_64.S | 2 +-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git
The restart table facility is used to return from interrupt without
disabling MSR EE or RI.
Interrupt return code is put into the low soft-masked region.
Critical code that has no exit work, SRRs set, soft-masked state set to
return state, saves r1 in the PACA and then begins to run instructions
Treat code below __end_soft_masked as soft-masked for the purpose
of alternate return. 64s already mostly does this for scv entry.
This will be used to exit from interrupts without disabling MSR[EE].
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/interrupt.h | 8
Prevent interrupt restore from allowing racing hard interrupts going
ahead of previous soft-pending ones, by using the soft-masked restart
handler to allow a store to clear the soft-mask while knowing nothing
is soft-pending.
This probably doesn't matter much in practice, but it's a simple
The exception table fixup adjusts a failed page fault's interrupt return
location if it was taken at an address specified in the exception table,
to a corresponding fixup handler address.
Introduce a variation of that idea which adds a fixup table for NMIs and
soft-masked asynchronous interrupts.
This frees up one more register (and takes advantage of that to
clean things up a little bit).
This register will be used in the following patch.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 34
1 file changed, 20 insertions(+), 14
The next patch would like to move interrupt return assembly code to a low
location before general text, so move it into its own file and include via
head_64.S
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/head-64.h | 2 +-
arch/powerpc/kernel/entry_64.S | 632
This makes no real difference yet except that HSRR type interrupts will
use hrfid to return. This is important for the next patch.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/entry_64.S | 63 ---
arch/powerpc/kernel/exceptions-64e.S | 4 ++
When an interrupt is taken, the SRR registers are set to return to
where it left off. Unless they are modified in the meantime, or the
return address or MSR are modified, there is no need to reload these
registers when returning from interrupt.
Introduce per-CPU flags that track the validity of
The fallback sequences for L1D flushing and store forwarding barriers
requires reloading r13, and saving and reloading registers from a
special PACA save area and SPRGs.
This is painful, and has caused a few difficult bugs (recently the scv
interrupt re-entrancy). Things would get even more hairy
This applies to powerpc next-test (particularly Christophe's ppc32
interrupt conversion) plus the 64e interrupt conversion patches I
recently posted.
This series attempts to improve the speed of interrupts and system calls
in three major ways.
Firstly, the SRR/HSRR registers do not need to be
The msr argument is not used, remove it.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/asm-prototypes.h | 4 ++--
arch/powerpc/kernel/interrupt.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/asm-prototypes.h
Both add_slot_store() and remove_slot_store() try to fix up the drc_name
copied from the store buffer by placing a NULL terminator at nbyte + 1
or in place of a '\n' if present. However, the static buffer that we
copy the drc_name data into is not zeored and can contain anything past
the n-th
This applies to powerpc next-test (particularly Christophe's ppc32
interrupt conversion) plus the 64e interrupt conversion patches I
recently posted.
This series attempts to improve the speed of interrupts and system calls
in three major ways.
Firstly, the SRR/HSRR registers do not need to be
On Fri, 12 Mar 2021 15:31:54 +0100
Cédric Le Goater wrote:
> Initial commit 15863ff3b8da ("powerpc: Make chip-id information
> available to userspace") introduce a cpu_to_chip_id() routine for the
> PowerNV platform using the "ibm,chip-id" property to query the chip id
> of a CPU. But PAPR does
On 3/15/21 1:16 PM, Cédric Le Goater wrote:
On 3/15/21 4:12 PM, Daniel Henrique Barboza wrote:
On 3/12/21 11:31 AM, Cédric Le Goater wrote:
Initial commit 15863ff3b8da ("powerpc: Make chip-id information
available to userspace") introduce a cpu_to_chip_id() routine for the
PowerNV
On 3/14/21 7:52 PM, Michael Ellerman wrote:
> Tyrel Datwyler writes:
>> On 3/13/21 1:17 AM, Michal Suchánek wrote:
>>> On Wed, Mar 10, 2021 at 04:30:21PM -0600, Tyrel Datwyler wrote:
Both add_slot_store() and remove_slot_store() try to fix up the drc_name
copied from the store buffer by
From: Rasmus Villemoes
> Sent: 15 March 2021 16:24
>
> On 12/03/2021 03.29, Segher Boessenkool wrote:
> > Hi!
> >
> > On Tue, Mar 09, 2021 at 06:19:30AM +, Christophe Leroy wrote:
> >> With some defconfig including CONFIG_CC_OPTIMIZE_FOR_SIZE,
> >> (for instance mvme5100_defconfig and
On 12/03/2021 03.29, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Mar 09, 2021 at 06:19:30AM +, Christophe Leroy wrote:
>> With some defconfig including CONFIG_CC_OPTIMIZE_FOR_SIZE,
>> (for instance mvme5100_defconfig and ps3_defconfig), gcc 5
>> generates a call to _restgpr_31_x.
>
>> I
On 3/15/21 4:12 PM, Daniel Henrique Barboza wrote:
>
>
> On 3/12/21 11:31 AM, Cédric Le Goater wrote:
>> Initial commit 15863ff3b8da ("powerpc: Make chip-id information
>> available to userspace") introduce a cpu_to_chip_id() routine for the
>> PowerNV platform using the "ibm,chip-id" property
On 3/12/21 11:31 AM, Cédric Le Goater wrote:
Initial commit 15863ff3b8da ("powerpc: Make chip-id information
available to userspace") introduce a cpu_to_chip_id() routine for the
PowerNV platform using the "ibm,chip-id" property to query the chip id
of a CPU. But PAPR does not specify such a
In fault.c, #ifdef CONFIG_PPC_MEM_KEYS is not needed because all
functions are always defined, and arch_vma_access_permitted()
always returns true when CONFIG_PPC_MEM_KEYS is not defined so
access_pkey_error() will return false so bad_access_pkey()
will never be called.
Include linux/pkeys.h to
Le 15/03/2021 à 04:17, Nicholas Piggin a écrit :
With non-volatile registers saved on interrupt, bad_page_fault
can now be called by do_page_fault.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64e.S | 6 --
arch/powerpc/mm/fault.c | 5 +
2 files
On 3/15/21 2:01 PM, Christophe Leroy wrote:
>
>
> Le 15/03/2021 à 13:57, Cédric Le Goater a écrit :
>> On 3/15/21 1:48 PM, heying (H) wrote:
>>>
>>> 在 2021/3/15 20:17, Christophe Leroy 写道:
You subject doesn't match the content of the patch.
>>> OK. I'll adapt that.
Le 15/03/2021 à
Le 25/02/2020 à 18:35, Nicholas Piggin a écrit :
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack store.
The stack store emulation is significantly simplfied, rather than creating
a new return frame and
On Tue, 9 Mar 2021 06:19:30 + (UTC), Christophe Leroy wrote:
> With some defconfig including CONFIG_CC_OPTIMIZE_FOR_SIZE,
> (for instance mvme5100_defconfig and ps3_defconfig), gcc 5
> generates a call to _restgpr_31_x.
>
> Until recently it went unnoticed, but
> commit 42ed6d56ade2
On Wed, 10 Mar 2021 12:10:34 + (UTC), Christophe Leroy wrote:
> The code relies on constant folding of cpu_has_feature() based
> on possible and always true values as defined per
> CPU_FTRS_ALWAYS and CPU_FTRS_POSSIBLE.
>
> Build failure is encountered with for instance
> book3e_all_defconfig
Le 15/03/2021 à 04:17, Nicholas Piggin a écrit :
Update the new C and asm interrupt return code to account for 64e
specifics, switch over to use it.
The now-unused old ret_from_except code, that was moved to 64e after the
64s conversion, is removed.
Signed-off-by: Nicholas Piggin
---
Le 15/03/2021 à 12:02, Geert Uytterhoeven a écrit :
Hi Christophe,
On Mon, Mar 15, 2021 at 11:55 AM Christophe Leroy
wrote:
Le 15/03/2021 à 11:49, Geert Uytterhoeven a écrit :
On Mon, Mar 15, 2021 at 11:46 AM Geert Uytterhoeven
wrote:
JFYI, when comparing v5.12-rc3[1] to v5.12-rc2[3],
Le 15/03/2021 à 13:59, Aneesh Kumar K.V a écrit :
On 3/15/21 5:36 PM, Christophe Leroy wrote:
Le 25/11/2020 à 06:16, Aneesh Kumar K.V a écrit :
Reviewed-by: Sandipan Das
Signed-off-by: Aneesh Kumar K.V
PPC_HAVE_KUAP is only selected on book3s/64 when PPC_RADIX_MMU is selected. Is
Le 15/03/2021 à 13:57, Cédric Le Goater a écrit :
On 3/15/21 1:48 PM, heying (H) wrote:
在 2021/3/15 20:17, Christophe Leroy 写道:
You subject doesn't match the content of the patch.
OK. I'll adapt that.
Le 15/03/2021 à 13:04, He Ying a écrit :
The variables 'uaccess_fulsh' and
On 3/15/21 5:36 PM, Christophe Leroy wrote:
Le 25/11/2020 à 06:16, Aneesh Kumar K.V a écrit :
Reviewed-by: Sandipan Das
Signed-off-by: Aneesh Kumar K.V
PPC_HAVE_KUAP is only selected on book3s/64 when PPC_RADIX_MMU is
selected. Is that normal ?
I guess we missed fixing that with
Le 15/03/2021 à 13:48, heying (H) a écrit :
在 2021/3/15 20:17, Christophe Leroy 写道:
You subject doesn't match the content of the patch.
OK. I'll adapt that.
Le 15/03/2021 à 13:04, He Ying a écrit :
The variables 'uaccess_fulsh' and 'entry_flush' are not referenced
outside the file. So
On 3/15/21 1:48 PM, heying (H) wrote:
>
> 在 2021/3/15 20:17, Christophe Leroy 写道:
>> You subject doesn't match the content of the patch.
> OK. I'll adapt that.
>>
>> Le 15/03/2021 à 13:04, He Ying a écrit :
>>> The variables 'uaccess_fulsh' and 'entry_flush' are not referenced
>>> outside the
在 2021/3/15 20:17, Christophe Leroy 写道:
You subject doesn't match the content of the patch.
OK. I'll adapt that.
Le 15/03/2021 à 13:04, He Ying a écrit :
The variables 'uaccess_fulsh' and 'entry_flush' are not referenced
outside the file. So define them as static to avoid the warnings.
You subject doesn't match the content of the patch.
Le 15/03/2021 à 13:04, He Ying a écrit :
The variables 'uaccess_fulsh' and 'entry_flush' are not referenced
outside the file. So define them as static to avoid the warnings.
And add a prototype for the function 'panic_smp_self_stop' for the
Le 25/11/2020 à 06:16, Aneesh Kumar K.V a écrit :
Reviewed-by: Sandipan Das
Signed-off-by: Aneesh Kumar K.V
PPC_HAVE_KUAP is only selected on book3s/64 when PPC_RADIX_MMU is selected. Is
that normal ?
---
arch/powerpc/mm/book3s64/pkeys.c | 7 ++-
1 file changed, 6
The variables 'uaccess_fulsh' and 'entry_flush' are not referenced
outside the file. So define them as static to avoid the warnings.
And add a prototype for the function 'panic_smp_self_stop' for the
same purpose.
Sparse also warns that 'rfi_flush' should be static. However, it's
referenced
Sparse reports the following problems:
arch/powerpc/math-emu/math.c:228:21: warning: Using plain integer as NULL
pointer
arch/powerpc/math-emu/math.c:228:31: warning: Using plain integer as NULL
pointer
arch/powerpc/math-emu/math.c:228:41: warning: Using plain integer as NULL
pointer
This patchset enables MOVE_PMD/MOVE_PUD support on power. This requires
the platform to support updating higher-level page tables without
updating page table entries. This also needs to invalidate the Page Walk
Cache on architecture supporting the same.
The patchset does that by switching the
mremap HAVE_MOVE_PMD/PUD optimization time comparison for 1GB region:
1GB mremap - Source PTE-aligned, Destination PTE-aligned
mremap time: 1114318ns
1GB mremap - Source PMD-aligned, Destination PMD-aligned
mremap time: 1097715ns
1GB mremap - Source PUD-aligned,
With a large mmap map size, we can overlap with the text area and using
MAP_FIXED results in unmapping that area. Switch to MAP_FIXED_NOREPLACE
and handle the EEXIST error.
Signed-off-by: Aneesh Kumar K.V
---
tools/testing/selftests/vm/mremap_test.c | 5 +++--
1 file changed, 3 insertions(+), 2
Some architectures do have the concept of page walk cache and only mmu gather
interface supports flushing them. A fast mremap that involves moving page
table pages instead of copying pte entries should flush page walk cache since
the old translation cache is no more valid. Hence switch to mm
Architectures like ppc64 can only support faster mremap only with radix
translation. Hence allow a runtime check w.r.t support for fast mremap.
Signed-off-by: Aneesh Kumar K.V
---
arch/arc/include/asm/tlb.h | 5 +
arch/arm64/include/asm/tlb.h | 6 ++
pmd/pud_populate is the right interface to be used to set the respective
page table entries. Some architectures like ppc64 do assume that set_pmd/pud_at
can only be used to set a hugepage PTE. Since we are not setting up a hugepage
PTE here, use the pmd/pud_populate interface.
Signed-off-by:
Instead of hardcoding 4K page size fetch it using sysconf(). For the performance
measurements test still assume 2M and 1G are hugepage sizes.
Signed-off-by: Aneesh Kumar K.V
---
tools/testing/selftests/vm/mremap_test.c | 113 ---
1 file changed, 61 insertions(+), 52
Hi Christophe,
On Mon, Mar 15, 2021 at 11:55 AM Christophe Leroy
wrote:
> Le 15/03/2021 à 11:49, Geert Uytterhoeven a écrit :
> > On Mon, Mar 15, 2021 at 11:46 AM Geert Uytterhoeven
> > wrote:
> >> JFYI, when comparing v5.12-rc3[1] to v5.12-rc2[3], the summaries are:
> >>- build errors:
Commit aac6a91fea93 ("powerpc/asm: Remove unused symbols in
asm-offsets.c") removed GPR15 to GPR31 but kept GPR14,
probably because it pops up in a couple of comments when doing
a grep.
However, it was never used either, so remove it as well.
Fixes: aac6a91fea93 ("powerpc/asm: Remove unused
Le 15/03/2021 à 11:49, Geert Uytterhoeven a écrit :
On Mon, Mar 15, 2021 at 11:46 AM Geert Uytterhoeven
wrote:
JFYI, when comparing v5.12-rc3[1] to v5.12-rc2[3], the summaries are:
- build errors: +2/-2
2 error regressions:
+ /kisskb/src/include/linux/compiler_types.h: error: call
On Mon, Mar 15, 2021 at 11:46 AM Geert Uytterhoeven
wrote:
> JFYI, when comparing v5.12-rc3[1] to v5.12-rc2[3], the summaries are:
> - build errors: +2/-2
> 2 error regressions:
> + /kisskb/src/include/linux/compiler_types.h: error: call to
> '__compiletime_assert_248' declared with
From: Chris Packham
> Sent: 14 March 2021 21:26
>
> On 12/03/21 10:25 pm, David Laight wrote:
> > From: Linuxppc-dev Guenter Roeck
> >> Sent: 11 March 2021 21:35
> >>
> >> On 3/11/21 1:17 PM, Chris Packham wrote:
> >>> On 11/03/21 9:18 pm, Wolfram Sang wrote:
> > Bummer. What is really weird
Hello,
在 2021/3/15 17:16, Christophe Leroy 写道:
I think W=1 will only report missing function prototypes.
sparse also reports missing variables prototypes so that's better. All
should be fixed.
OK. I'll try to fix all the warnings in the file
"arch/powerpc/kernel/setup_64.c" reported by
Le 15/03/2021 à 07:51, heying (H) a écrit :
I think this is the case also for entry_flush. compiling with W=1 will tell you
more.
When I use these commands:
make allmodconfig ARCH=powerpc CROSS_COMPILE=powerpc64-linux-gnu-
make C=2 arch/powerpc/kernel/setup_64.o ARCH=powerpc
I think this is the case also for entry_flush. compiling with W=1 will tell you
more.
When I use these commands:
make allmodconfig ARCH=powerpc CROSS_COMPILE=powerpc64-linux-gnu-
make C=2 arch/powerpc/kernel/setup_64.o ARCH=powerpc
CROSS_COMPILE=powerpc64-linux-gnu-
I find warnings as
Thank you for maintenance and for following this request.
Regards
Christoph
-Original Message-
From: Michael Ellerman
Sent: Sonntag, 14. März 2021 11:01
To: Michael Ellerman ; Paul Mackerras ;
Benjamin Herrenschmidt ; PLATTNER Christoph
; Christophe Leroy
Cc:
Le 02/06/2016 à 00:56, Rashmica Gupta a écrit :
---
GPR15, GPR16, GPR17, GPR18, GPR19, GPR20, GPR21, GPR22, GPR23, GPR24,
GPR25, GPR26, GPR27, GPR28, GPR29 and GPR30: Added in commit
a4bcbe6a41ad ("powerpc: Remove old compile time disabled syscall tracing
code") and were never used.
---
On Fri, Mar 12, 2021 at 04:18:24PM +, Robin Murphy wrote:
>> Let me know what you think of the version here:
>>
>> http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/iommu-cleanup
>>
>> I'll happily switch the patch to you as the author if you're fine with
>> that as well.
>
> I
Le 15/03/2021 à 08:50, Christophe Leroy a écrit :
Le 15/03/2021 à 04:17, Nicholas Piggin a écrit :
Update the new C and asm interrupt return code to account for 64e
specifics, switch over to use it.
The now-unused old ret_from_except code, that was moved to 64e after the
64s conversion,
Le 15/03/2021 à 04:17, Nicholas Piggin a écrit :
Compact the trap flags down to use the low 4 bits of regs.trap.
A few 64e interrupt trap numbers set bit 4. Although they tended to be
trivial so it wasn't a real problem[1], it is not the right thing to do,
and confusing.
[*] E.g., 0x310
Dear Michael,
Thank you very much for your response.
Am 15.03.21 um 08:53 schrieb Michael Ellerman:
Paul Menzel writes:
On the POWER8 system IBM S822LC, Linux 5.12-rc2+ logs the errors below.
That's a bare metal system, you can see that from the line "Using
PowerNV machine description"
The pseries join/suspend sequence in its current form was written with
the assumption that it was the only user of H_PROD and that it needn't
handle spurious successful returns from H_JOIN. That's wrong;
powerpc's paravirt spinlock code uses H_PROD, and CPUs entering
do_join() can be woken
pseries VMs in shared processor mode are susceptible to failed
migrations becasue stray H_PRODs from the paravirt spinlock
implementation can bump threads out of joining state before the
suspend has occurred. Fix this by adding a small amount of shared
state and ordering accesses to it with
The atomic_t counter is the only shared state for the join/suspend
sequence so far, but that will change. Contain it in a
struct (pseries_suspend_info), and document its intended use. No
functional change.
Signed-off-by: Nathan Lynch
---
arch/powerpc/platforms/pseries/mobility.c | 22
Paul Menzel writes:
> Dear Linux folks,
>
>
> On the POWER8 system IBM S822LC, Linux 5.12-rc2+ logs the errors below.
That's a bare metal system, you can see that from the line "Using
PowerNV machine description" in the boot log.
> $ dmesg --level=err
> [1.555668] Driver
Hi Christoph,
On 3/14/21 4:58 PM, Christoph Hellwig wrote:
> On Sun, Mar 14, 2021 at 11:44:52AM +0100, Auger Eric wrote:
>> As mentionned by Robin, there are series planning to use
>> DOMAIN_ATTR_NESTING to get info about the nested caps of the iommu (ARM
>> and Intel):
>>
>> [Patch v8 00/10]
> On 12-Mar-2021, at 6:26 PM, Jiri Olsa wrote:
>
> On Tue, Mar 09, 2021 at 09:04:00AM -0500, Athira Rajeev wrote:
>> The pipeline stage cycles details can be recorded on powerpc from
>> the contents of Performance Monitor Unit (PMU) registers. On
>> ISA v3.1 platform, sampling registers
Le 15/03/2021 à 04:17, Nicholas Piggin a écrit :
Update the new C and asm interrupt return code to account for 64e
specifics, switch over to use it.
The now-unused old ret_from_except code, that was moved to 64e after the
64s conversion, is removed.
Signed-off-by: Nicholas Piggin
---
> On 12-Mar-2021, at 6:27 PM, Jiri Olsa wrote:
>
> On Tue, Mar 09, 2021 at 09:03:58AM -0500, Athira Rajeev wrote:
>> Currently the header string for different columns in perf report
>> is fixed. Some fields of perf sample could have different meaning
>> for different architectures than the
Fix the following coccicheck warning:
./arch/powerpc/platforms/maple/pci.c:37:16-17: WARNING comparing pointer
to 0.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
arch/powerpc/platforms/maple/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
fixed the following coccicheck:
./arch/powerpc/sysdev/xive/spapr.c:552:8-9: WARNING: return of 0/1 in
function 'xive_spapr_match' with return type bool
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
arch/powerpc/sysdev/xive/spapr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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