Hi Nathan,
Thanks for the detailed explanation.
I've not really worked with the partition migration code before I was
able to follow your logic.
> On VMs with NX encryption, compression, and/or RNG offload, these
> capabilities are described by nodes in the ibm,platform-facilities device
> tree
Le 21/10/2021 à 05:54, Nicholas Piggin a écrit :
Microwatt is radix-only, so it does not require hash MMU support.
Patches 15 and 16 could be squashed into a single patch, say Microwatt
is a radix-only POWER9.
This saves 20kB compressed dtbImage and 56kB vmlinux size.
Signed-off-by:
Le 21/10/2021 à 05:54, Nicholas Piggin a écrit :
Thisa adds Kconfig selection which allows the 64s hash MMU code to be
compiled out if radix is selected and the minimum supported CPU type is
POWER9 or higher, and KVM is not selected.
This saves 128kB kernel image size (90kB text) on
Le 21/10/2021 à 05:54, Nicholas Piggin a écrit :
Introduce a new option CONFIG_PPC_64S_HASH_MMU, and make 64s hash
code depend on it.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/include/asm/book3s/64/mmu.h | 19 +--
On Thu, 21 Oct 2021 at 04:04, Nicholas Piggin wrote:
>
> Microwatt is radix-only, so it does not require hash MMU support.
>
> This saves 20kB compressed dtbImage and 56kB vmlinux size.
>
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/configs/microwatt_defconfig | 1 -
>
Le 21/10/2021 à 05:54, Nicholas Piggin a écrit :
mmu_linear_psize is only set at boot once on 64e, is not necessarily
the correct size of the linear map pages, and is never used anywhere
except memremap_compat_align.
Remove mmu_linear_psize and hard code the 1GB value instead in
Le 21/10/2021 à 05:54, Nicholas Piggin a écrit :
Radix never sets mmu_linear_psize so it's always 4K, which causes pcpu
atom_size to always be PAGE_SIZE. 64e sets it to 1GB always.
Make paths for these platforms to be explicit about what value they set
atom_size to.
Signed-off-by: Nicholas
Microwatt is radix-only, so it does not require hash MMU support.
This saves 20kB compressed dtbImage and 56kB vmlinux size.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/configs/microwatt_defconfig | 1 -
arch/powerpc/platforms/microwatt/Kconfig | 1 -
2 files changed, 2 deletions(-)
diff
Microwatt implements a subset of ISA v3.0 (which is equivalent to
the POWER9_CPU option).
Signed-off-by: Nicholas Piggin
---
arch/powerpc/configs/microwatt_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs/microwatt_defconfig
Thisa adds Kconfig selection which allows the 64s hash MMU code to be
compiled out if radix is selected and the minimum supported CPU type is
POWER9 or higher, and KVM is not selected.
This saves 128kB kernel image size (90kB text) on powernv_defconfig
minus KVM, 350kB on pseries_defconfig minus
Introduce a new option CONFIG_PPC_64S_HASH_MMU, and make 64s hash
code depend on it.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/include/asm/book3s/64/mmu.h | 19 +--
.../include/asm/book3s/64/tlbflush-hash.h | 7
mmu_linear_psize is only set at boot once on 64e, is not necessarily
the correct size of the linear map pages, and is never used anywhere
except memremap_compat_align.
Remove mmu_linear_psize and hard code the 1GB value instead in
memremap_compat_align.
Signed-off-by: Nicholas Piggin
---
Radix never sets mmu_linear_psize so it's always 4K, which causes pcpu
atom_size to always be PAGE_SIZE. 64e sets it to 1GB always.
Make paths for these platforms to be explicit about what value they set
atom_size to.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/setup_64.c | 21
This file contains functions and data common to radix, so rename it to
remove the hash_ prefix.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/book3s64/Makefile | 2 +-
arch/powerpc/mm/book3s64/{hash_hugetlbpage.c => hugetlbpage.c} | 0
2 files changed, 1
The radix code uses some of the psize variables. Move the common
ones from hash_utils.c to pgtable.c.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/book3s64/hash_utils.c | 5 -
arch/powerpc/mm/book3s64/pgtable.c| 7 +++
2 files changed, 7 insertions(+), 5 deletions(-)
diff
The radix test can exclude slb_flush_all_realmode() from being called
because flush_and_reload_slb() is only expected to flush ERAT when
called by flush_erat(), which is only on pre-ISA v3.0 CPUs that do not
support radix.
This helps the later change to make hash support configurable to not
In preparation for making hash MMU support configurable, move THP
trace point function definitions out of an otherwise hash specific
file.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/book3s64/Makefile | 2 +-
arch/powerpc/mm/book3s64/hash_pgtable.c | 1 -
This avoids a change in behaviour in the later patch making hash
support configurable. This is possibly a user interface change, so
the alternative would be a hard-coded slb_size=0 here.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/platforms/pseries/lparcfg.c | 3 ++-
1 file changed, 2
This reduces ifdefs in a later change making hash support configurable.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/platforms/pseries/lpar.c | 56 +--
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/lpar.c
slb.c is hash-specific SLB management, but do_bad_slb_fault deals with
segment interrupts that occur with radix MMU as well.
---
arch/powerpc/include/asm/interrupt.h | 2 +-
arch/powerpc/kernel/exceptions-64s.S | 4 ++--
arch/powerpc/mm/book3s64/slb.c | 16
The pseries platform does not use the native hash code but the PAPR
virtualised hash interfaces, so remove PPC_HASH_MMU_NATIVE.
This requires moving tlbiel code from hash_native.c to hash_utils.c.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/book3s/64/tlbflush.h | 4 -
PPC_NATIVE now only controls the native HPT code, so rename it to be
more descriptive. Restrict it to Book3S only.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/book3s64/Makefile | 2 +-
arch/powerpc/mm/book3s64/hash_utils.c | 2 +-
arch/powerpc/platforms/52xx/Kconfig
FW_FEATURE_NATIVE_ALWAYS and FW_FEATURE_NATIVE_POSSIBLE are always
zero and never do anything. Remove them.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/firmware.h | 8
1 file changed, 8 deletions(-)
diff --git a/arch/powerpc/include/asm/firmware.h
Now that there's a platform that can make good use of it, here's
a series that can prevent the hash MMU code being built for 64s
platforms that don't need it.
Since v1:
- Split out most of the Kconfig change from the conditional compilation
changes.
- Split out several more changes into
On Wed, 9 Jan 2019 18:59:09 -0800, Tyrel Datwyler wrote:
> During driver probe we allocate a dma region for our event pool.
> Currently, zero is passed for the gfp_flags parameter. Driver probe
> callbacks run in process context and we hold no locks so we can sleep
> here if necessary.
>
> Fix
> On 19-Oct-2021, at 10:00 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Mon, Oct 18, 2021 at 05:19:46PM +0530, Athira Rajeev escreveu:
>> Patch set adds PMU registers namely Sampled Instruction Address Register
>> (SIAR) and Sampled Data Address Register (SDAR) as part of extended regs
>> in
[+cc Keith, Sinan, Oza]
On Tue, Oct 05, 2021 at 10:48:12PM +0530, Naveen Naidu wrote:
> In the EDR path, AER registers are cleared *after* DPC error event is
> processed. The process stack in EDR is:
>
> edr_handle_event()
> dpc_process_error()
> pci_aer_raw_clear_status()
>
On Tue, Oct 05, 2021 at 10:48:11PM +0530, Naveen Naidu wrote:
> dpc_process_error() clears both AER fatal and non fatal status
> registers. Instead of clearing each status registers via a different
> function call use pci_aer_clear_status().
>
> This helps clean up the code a bit.
>
>
powerpc allnoconfig
i386 randconfig-a004-20211020
i386 randconfig-a003-20211020
i386 randconfig-a002-20211020
i386 randconfig-a005-20211020
i386 randconfig-a006-20211020
i386
On Tue, Oct 05, 2021 at 10:48:08PM +0530, Naveen Naidu wrote:
> Currently, we do not print the "id" field in the AER error logs. Yet the
> aer_agent_string[] has the word "id" in it. The AER error log looks
> like:
>
> pcieport :00:03.0: PCIe Bus Error: severity=Corrected, type=Data Link
>
On Tue, Oct 05, 2021 at 10:48:10PM +0530, Naveen Naidu wrote:
> In the dpc_process_error() path, info->id isn't initialized before being
> passed to aer_print_error(). In the corresponding AER path, it is
> initialized in aer_isr_one_error().
>
> The error message shown during Coverity Scan is:
>
On Mon, Sep 20, 2021 at 07:05:07PM -0500, Gustavo A. R. Silva wrote:
>
>
> On 9/18/21 09:21, Len Baker wrote:
> > There is a regular need in the kernel to provide a way to declare having
> > a dynamically sized set of trailing elements in a structure. Kernel code
> > should always use "flexible
Now that force_fatal_sig exists it is unnecessary and a bit confusing
to use force_sigsegv in cases where the simpler force_fatal_sig is
wanted. So change every instance we can to make the code clearer.
Signed-off-by: "Eric W. Biederman"
---
arch/arc/kernel/process.c | 2 +-
On VMs with NX encryption, compression, and/or RNG offload, these
capabilities are described by nodes in the ibm,platform-facilities device
tree hierarchy:
$ tree -d /sys/firmware/devicetree/base/ibm,platform-facilities/
/sys/firmware/devicetree/base/ibm,platform-facilities/
├──
On Wed, Oct 6, 2021 at 11:43 AM Rob Herring wrote:
>
> The first 10 patches add a new function, of_get_cpu_hwid(), which parses
> CPU DT node 'reg' property, and then use it to replace all the open
> coded versions of parsing CPU node 'reg' properties.
>
> The last 2 patches add support for
While looking at some issues related to the exit path in the kernel I
found several instances where the code is not using the existing
abstractions properly.
This set of changes introduces force_fatal_sig a way of sending
a signal and not allowing it to be caught, and corrects the
misuse of the
If the register state may be partial and corrupted instead of calling
do_exit, call force_sigsegv(SIGSEGV). Which properly kills the
process with SIGSEGV and does not let any more userspace code execute,
instead of just killing one thread of the process and potentially
confusing everything.
Cc:
On 10/20/21 8:54 AM, Nathan Lynch wrote:
> Tyrel Datwyler writes:
>> On 10/19/21 2:36 PM, Nathan Lynch wrote:
>>> Tyrel Datwyler writes:
On 10/18/21 9:34 AM, Nathan Lynch wrote:
> On VMs with NX encryption, compression, and/or RNG offload, these
> capabilities are described by nodes
On 10/20/21 4:39 AM, Nathan Lynch wrote:
> Wan Jiabing writes:
>> Fix following coccicheck warning:
>> ./drivers/pci/hotplug/pnv_php.c:161:2-13: ERROR: probable double put.
>>
>> Device node iterators put the previous value of the index variable, so
>> an explicit put causes a double put.
>
> I
On 10/20/21 2:46 AM, Wan Jiabing wrote:
> Fix following coccicheck warning:
> ./drivers/pci/hotplug/pnv_php.c:161:2-13: ERROR: probable double put.
>
> Device node iterators put the previous value of the index variable, so
> an explicit put causes a double put.
>
> Signed-off-by: Wan Jiabing
Tyrel Datwyler writes:
> On 10/19/21 2:36 PM, Nathan Lynch wrote:
>> Tyrel Datwyler writes:
>>> On 10/18/21 9:34 AM, Nathan Lynch wrote:
On VMs with NX encryption, compression, and/or RNG offload, these
capabilities are described by nodes in the ibm,platform-facilities device
tree
Hello:
This patch was applied to netdev/net-next.git (master)
by David S. Miller :
On Tue, 19 Oct 2021 06:19:25 -0600 you wrote:
> Coverity complains of unsigned compare against 0. There are 2 cases in
> this function:
>
> 1821itp = (irq_holdoff * 1000) /
The iommu_init_table() helper takes an address range to reserve in
the IOMMU table being initialized to exclude MMIO addresses, this is
useful if the window stretches far beyond 4GB (although wastes some TCEs).
At the moment the code searches for such MMIO32 range and fails if none
found which is
At the moment this check is performed after we remove the default window
which is late and disallows to revert whatever changes enable_ddw()
has made to DMA windows.
This moves the check and error exit before removing the window.
This raised the message severity from "debug" to "warning" as this
The it_map array is vzalloc'ed so use vfree() for it when creating
a huge DMA window failed for whatever reason.
While at this, write zero to it_map.
Fixes: 381ceda88c4c ("powerpc/pseries/iommu: Make use of DDW for indirect
mapping")
Signed-off-by: Alexey Kardashevskiy
---
Found some issues on SRIOV enabled PHYP.
It probably should be one patch, or not?
Please comment. Thanks.
Alexey Kardashevskiy (4):
powerpc/pseries/iommu: Fix indentations
powerpc/pseries/iommu: Use correct vfree for it_map
powerpc/pseries/iommu: Check if the default window in use before
This fixes broken indentations. The first hunk might suggest that
the introducing patch was applied incorrectly but it is correct.
Fixes: 381ceda88c4c ("powerpc/pseries/iommu: Make use of DDW for indirect
mapping")
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/pseries/iommu.c
Wan Jiabing writes:
> Fix following coccicheck warning:
> ./drivers/pci/hotplug/pnv_php.c:161:2-13: ERROR: probable double put.
>
> Device node iterators put the previous value of the index variable, so
> an explicit put causes a double put.
I suppose Coccinelle doesn't take into account that
In isa206_idle_insn_mayloss() we store various registers into the stack
red zone, which is allowed.
However inside the IDLE_STATE_ENTER_SEQ_NORET macro we save r2 again,
to 0(r1), which corrupts the stack back chain.
We used to do the same in isa206_idle_insn_mayloss() itself, but we
fixed that
Fix following coccicheck warning:
./drivers/pci/hotplug/pnv_php.c:161:2-13: ERROR: probable double put.
Device node iterators put the previous value of the index variable, so
an explicit put causes a double put.
Signed-off-by: Wan Jiabing
---
drivers/pci/hotplug/pnv_php.c | 1 -
1 file
Excerpts from Laurent Vivier's message of October 20, 2021 4:29 pm:
> On 15/10/2021 04:23, Nicholas Piggin wrote:
>> Excerpts from Laurent Vivier's message of October 13, 2021 7:30 pm:
>>> On 13/10/2021 01:18, Michael Ellerman wrote:
Laurent Vivier writes:
> Commit 112665286d08 moved
A: http://en.wikipedia.org/wiki/Top_post
Q: Were do I find info about this thing called top-posting?
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
A: No.
Q: Should I
hi Greg，
Could I get your comments of this new version patches？ thanks
在 2021/10/15 上午10:46, Xianting Tian 写道:
As well known, hvc backend can register its opertions to hvc backend.
the operations contain put_chars(), get_chars() and so on.
Some hvc backend may do dma in its operations. eg,
On 15/10/2021 04:23, Nicholas Piggin wrote:
Excerpts from Laurent Vivier's message of October 13, 2021 7:30 pm:
On 13/10/2021 01:18, Michael Ellerman wrote:
Laurent Vivier writes:
Commit 112665286d08 moved guest_exit() in the interrupt protected
area to avoid wrong context warning (or
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