Re: [PATCH v1 2/2] powerpc64/dexcr: Enable PHIE on all CPUs

2024-03-24 Thread Benjamin Gray
OK, so I compile for corenet64 but not corenet32 apparently. I'll fix the shift overflow in the next round.

[PATCH v3 5/5] powerpc/code-patching: Add boot selftest for data patching

2024-03-24 Thread Benjamin Gray
Extend the code patching selftests with some basic coverage of the new data patching variants too. Signed-off-by: Benjamin Gray --- v3: * New in v3 --- arch/powerpc/lib/test-code-patching.c | 36 +++ 1 file changed, 36 insertions(+) diff --git

[PATCH v3 1/5] powerpc/code-patching: Add generic memory patching

2024-03-24 Thread Benjamin Gray
patch_instruction() is designed for patching instructions in otherwise readonly memory. Other consumers also sometimes need to patch readonly memory, so have abused patch_instruction() for arbitrary data patches. This is a problem on ppc64 as patch_instruction() decides on the patch width using

[PATCH v3 4/5] powerpc/32: Convert patch_instruction() to patch_uint()

2024-03-24 Thread Benjamin Gray
These changes are for patch_instruction() uses on data. Unlike ppc64 these should not be incorrect as-is, but using the patch_uint() alias better reflects what kind of data being patched and allows for benchmarking the effect of different patch_* implementations (e.g., skipping instruction

[PATCH v3 0/5] Add generic data patching functions

2024-03-24 Thread Benjamin Gray
Currently patch_instruction() bases the write length on the value being written. If the value looks like a prefixed instruction it writes 8 bytes, otherwise it writes 4 bytes. This makes it potentially buggy to use for writing arbitrary data, as if you want to write 4 bytes but it decides to write

[PATCH v3 2/5] powerpc/code-patching: Add data patch alignment check

2024-03-24 Thread Benjamin Gray
The new data patching still needs to be aligned within a cacheline too for the flushes to work correctly. To simplify this requirement, we just say data patches must be aligned. Detect when data patching is not aligned, returning an invalid argument error. Signed-off-by: Benjamin Gray --- v3:

[PATCH v3 3/5] powerpc/64: Convert patch_instruction() to patch_u32()

2024-03-24 Thread Benjamin Gray
This use of patch_instruction() is working on 32 bit data, and can fail if the data looks like a prefixed instruction and the extra write crosses a page boundary. Use patch_u32() to fix the write size. Fixes: 8734b41b3efe ("powerpc/module_64: Fix livepatching for RO modules") Link:

Re: [PATCH v3] arch/powerpc/kvm: Add support for reading VPA counters for pseries guests

2024-03-24 Thread Gautam Menghani
On Fri, Mar 22, 2024 at 03:41:32PM +0530, Gautam Menghani wrote: > PAPR hypervisor has introduced three new counters in the VPA area of > LPAR CPUs for KVM L2 guest (see [1] for terminology) observability - 2 > for context switches from host to guest and vice versa, and 1 counter > for getting the

[PATCH v2 1/2] powerpc/code-patching: Test patch_instructions() during boot

2024-03-24 Thread Benjamin Gray
patch_instructions() introduces new behaviour with a couple of variations. Test each case of * a repeated 32-bit instruction, * a repeated 64-bit instruction (ppc64), and * a copied sequence of instructions for both on a single page and when it crosses a page boundary. Signed-off-by:

[PATCH v2 2/2] powerpc/code-patching: Use dedicated memory routines for patching

2024-03-24 Thread Benjamin Gray
The patching page set up as a writable alias may be in quadrant 0 (userspace) if the temporary mm path is used. This causes sanitiser failures if so. Sanitiser failures also occur on the non-mm path because the plain memset family is instrumented, and KASAN treats the patching window as poisoned.

[FSL P50x0] Kernel 6.9-rc1 compiling issue

2024-03-24 Thread Christian Zigotzky
I have created a patch: --- a/arch/powerpc/platforms/85xx/smp.c 2024-03-25 06:14:02.201209476 +0100 +++ b/arch/powerpc/platforms/85xx/smp.c 2024-03-25 06:10:04.421425931 +0100 @@ -393,6 +393,7 @@ static void mpc85xx_smp_kexec_cpu_down(i     int disable_threadbit = 0;     long start =

[PATCH v1 1/2] powerpc64/dexcr: Compile kernel with privileged hash instructions

2024-03-24 Thread Benjamin Gray
There are dedicated hashstp and hashchkp instructions that can be inserted into a guest kernel to give it hypervisor managed ROP protection (the hypervisor sets the secret hash key and handles hashstp exceptions). In testing, the kernel appears to handle the compiler generated hash protection

[PATCH v1 2/2] powerpc64/dexcr: Enable PHIE on all CPUs

2024-03-24 Thread Benjamin Gray
While we can now compile the kernel with ROP protection, it's possible the hash instructions are acting as NOPs. Enable the PHIE aspect at an appropriate stage in boot so as to maximise coverage without requiring certain functions be compiled without ROP protection. For the boot CPU, there are

[FSL P50x0] Kernel 6.9-rc1 compiling issue

2024-03-24 Thread Christian Zigotzky
Hi All, The Compiling of the RC1 of kernel 6.9 doesn’t work anymore for our FSL P5020/P5040 boards [1] since the PowerPC updates 6.9-2 [2]. Error messages: arch/powerpc/platforms/85xx/smp.c: In function 'mpc85xx_smp_kexec_cpu_down': arch/powerpc/platforms/85xx/smp.c:401:13: error:

Re: [PATCH 00/11] Bump the minimum supported version of LLVM to 13.0.1

2024-03-24 Thread patchwork-bot+linux-riscv
Hello: This series was applied to riscv/linux.git (fixes) by Andrew Morton : On Thu, 25 Jan 2024 15:55:06 -0700 you wrote: > Hi all, > > This series bumps the minimum supported version of LLVM for building the > kernel to 13.0.1. The first patch does the bump and all subsequent > patches clean

Re: [PATCH v3 00/15] mm/memory: optimize fork() with PTE-mapped THP

2024-03-24 Thread patchwork-bot+linux-riscv
Hello: This series was applied to riscv/linux.git (fixes) by Andrew Morton : On Mon, 29 Jan 2024 13:46:34 +0100 you wrote: > Now that the rmap overhaul[1] is upstream that provides a clean interface > for rmap batching, let's implement PTE batching during fork when processing > PTE-mapped THPs.

Re: [PATCH 1/1] arch/arm/mm: fix major fault accounting when retrying under per-VMA lock

2024-03-24 Thread patchwork-bot+linux-riscv
Hello: This patch was applied to riscv/linux.git (fixes) by Andrew Morton : On Mon, 22 Jan 2024 22:43:05 -0800 you wrote: > The change [1] missed ARM architecture when fixing major fault accounting > for page fault retry under per-VMA lock. Add missing code to fix ARM > architecture fault

[PATCH 6.6 397/638] drivers/ps3: select VIDEO to provide cmdline functions

2024-03-24 Thread Sasha Levin
From: Randy Dunlap [ Upstream commit 7edd06233958d9086a9e3eb723a8768d3c5a9ce1 ] When VIDEO is not set, there is a build error. Fix that by selecting VIDEO for PS3_PS3AV. ERROR: modpost: ".video_get_options" [drivers/ps3/ps3av_mod.ko] undefined! Fixes: dae7fbf43fd0 ("driver/ps3: Include for

[PATCH 6.7 444/713] drivers/ps3: select VIDEO to provide cmdline functions

2024-03-24 Thread Sasha Levin
From: Randy Dunlap [ Upstream commit 7edd06233958d9086a9e3eb723a8768d3c5a9ce1 ] When VIDEO is not set, there is a build error. Fix that by selecting VIDEO for PS3_PS3AV. ERROR: modpost: ".video_get_options" [drivers/ps3/ps3av_mod.ko] undefined! Fixes: dae7fbf43fd0 ("driver/ps3: Include for

[PATCH 6.8 412/715] drivers/ps3: select VIDEO to provide cmdline functions

2024-03-24 Thread Sasha Levin
From: Randy Dunlap [ Upstream commit 7edd06233958d9086a9e3eb723a8768d3c5a9ce1 ] When VIDEO is not set, there is a build error. Fix that by selecting VIDEO for PS3_PS3AV. ERROR: modpost: ".video_get_options" [drivers/ps3/ps3av_mod.ko] undefined! Fixes: dae7fbf43fd0 ("driver/ps3: Include for

Re: [PATCHv3 pci-next 1/2] PCI/AER: correctable error message as KERN_INFO

2024-03-24 Thread Xi Ruoyao
On Mon, 2023-09-18 at 14:39 -0500, Bjorn Helgaas wrote: > On Mon, Sep 18, 2023 at 07:42:30PM +0800, Xi Ruoyao wrote: > > ... > > > My workstation suffers from too much correctable AER reporting as well > > (related to Intel's errata "RPL013: Incorrectly Formed PCIe Packets May > > Generate

Appropriate liburcu cache line size for Power

2024-03-24 Thread Mathieu Desnoyers
Hi, In the powerpc architecture support within the liburcu project [1] we have a cache line size defined as 256 bytes with the following comment: /* Include size of POWER5+ L3 cache lines: 256 bytes */ #define CAA_CACHE_LINE_SIZE 256 I recently received a pull request on github [2] asking