>> TCGv msr = tcg_temp_new();
>>
>> @@ -4411,9 +4423,6 @@ static void gen_mtmsr(DisasContext *ctx)
>> * power saving mode, we will exit the loop directly from
>> * ppc_store_msr
>> */
>> -if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
>> -gen_io_start();
>> -}
>> gen_update_nip(ctx, ctx->base.pc_next);
>> #if defined(TARGET_PPC64)
>> tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
>> @@ -4422,10 +4431,9 @@ static void gen_mtmsr(DisasContext *ctx)
>> #endif
>> gen_helper_store_msr(cpu_env, msr);
>> tcg_temp_free(msr);
>> -/* Must stop the translation as machine state (may have) changed */
>> -/* Note that mtmsr is not always defined as context-synchronizing */
>> -gen_stop_exception(ctx);
>> }
>> +/* Must stop the translation as machine state (may have) changed */
>> +gen_stop_exception(ctx);
>> #endif
>> }
>>
>>
--
Alex Bennée
Currently x86, powerpc and soon arm64 use the same two architecture
specific bits for guest debug support for software and hardware
breakpoints. This makes the shared values explicit.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed-by: Andrew Jones drjo...@redhat.com
-
v4
- claim
-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed-by: Andrew Jones drjo...@redhat.com
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index ab4d473..1731569 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
Christoffer Dall christoffer.d...@linaro.org writes:
On Tue, Mar 31, 2015 at 04:08:00PM +0100, Alex Bennée wrote:
Currently x86, powerpc and soon arm64 use the same two architecture
specific bits for guest debug support for software and hardware
breakpoints. This makes the shared values
-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index ab4d473..1731569 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -310,8 +310,8 @@ struct kvm_guest_debug_arch
