Hi Experts,
I was recently looking at ways to extend the randomization range for a
ASLR elf on a PPC64LE system.
I basically have been using 28-bits of randomization on x86_64 for an
ASLR elf using appropriate ARCH_MMAP_RND_BITS_MIN and
ARCH_MMAP_RND_BITS_MAX values:
http://lxr.free-electrons.co
and share their
test results/issues as well.
Cc: Alexander Graf
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Anatolij Gustschin
Cc: Alistair Popple
Cc: Matt Porter
Cc: Vitaly Bordug
Cc: Scott Wood
Cc: Kumar Gala
Cc: Daniel Cashman
Cc: Kees Cook
Bhupesh
: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Anatolij Gustschin
Cc: Alistair Popple
Cc: Matt Porter
Cc: Vitaly Bordug
Cc: Scott Wood
Cc: Kumar Gala
Cc: Daniel Cashman
Cc: Kees Cook
Signed-off-by: Bhupesh Sharma
---
arch/powerpc/Kconfig | 34
orter
Cc: Vitaly Bordug
Cc: Scott Wood
Cc: Kumar Gala
Cc: Daniel Cashman
Cc: Kees Cook
Signed-off-by: Bhupesh Sharma
---
arch/powerpc/include/asm/elf.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
Hi Kees,
On Thu, Jan 26, 2017 at 7:08 AM, Kees Cook wrote:
> On Sun, Jan 22, 2017 at 9:34 PM, Bhupesh Sharma wrote:
>> I was recently looking at ways to extend the randomization range for a
>> ASLR elf on a PPC64LE system.
>>
>> I basically have been using 28-bits of
Hi Kees,
On Thu, Feb 2, 2017 at 7:55 PM, Kees Cook wrote:
> On Wed, Feb 1, 2017 at 9:42 PM, Bhupesh Sharma wrote:
>> powerpc: arch_mmap_rnd() uses hard-coded values, (23-PAGE_SHIFT) for
>> 32-bit and (30-PAGE_SHIFT) for 64-bit, to generate the random offset
>> for
HI Balbir,
On Thu, Feb 2, 2017 at 2:41 PM, Balbir Singh wrote:
>> @@ -100,6 +132,8 @@ config PPC
>> select HAVE_EFFICIENT_UNALIGNED_ACCESS if !(CPU_LITTLE_ENDIAN &&
>> POWER7_CPU)
>> select HAVE_KPROBES
>> select HAVE_ARCH_KGDB
>> + select HAVE_ARCH_MMAP_RND_BITS
>> + s
Hi Kees,
Thanks for the review.
Please see my comments inline.
On Thu, Feb 2, 2017 at 7:51 PM, Kees Cook wrote:
> On Wed, Feb 1, 2017 at 9:42 PM, Bhupesh Sharma wrote:
>> This RFC patchset tries to make the powerpc ASLR elf randomness
>> implementation similar to other
Hi Balbir,
On Thu, Feb 2, 2017 at 12:14 PM, Balbir Singh wrote:
> On Thu, Feb 02, 2017 at 11:12:46AM +0530, Bhupesh Sharma wrote:
>> This RFC patchset tries to make the powerpc ASLR elf randomness
>> implementation similar to other ARCHs (like x86).
>>
>> The 1st patc
On 3 Feb 2017 00:49, "Kees Cook" wrote:
On Thu, Feb 2, 2017 at 10:08 AM, Bhupesh Sharma wrote:
> On Thu, Feb 2, 2017 at 7:51 PM, Kees Cook wrote:
>> On Wed, Feb 1, 2017 at 9:42 PM, Bhupesh Sharma
wrote:
>>> The 2nd patch increases the ELF_ET_DYN_BASE value from the
: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Anatolij Gustschin
Cc: Alistair Popple
Cc: Matt Porter
Cc: Vitaly Bordug
Cc: Scott Wood
Cc: Kumar Gala
Cc: Daniel Cashman
Signed-off-by: Bhupesh Sharma
Reviewed-by: Kees Cook
---
Changes since v1:
v1 can be seen here
(https
On Sat, Feb 4, 2017 at 6:13 AM, Kees Cook wrote:
> On Thu, Feb 2, 2017 at 9:11 PM, Bhupesh Sharma wrote:
>> powerpc: arch_mmap_rnd() uses hard-coded values, (23-PAGE_SHIFT) for
>> 32-bit and (30-PAGE_SHIFT) for 64-bit, to generate the random offset
>> for the mmap base addr
HI Michael,
On Thu, Feb 2, 2017 at 3:53 PM, Michael Ellerman wrote:
> Bhupesh Sharma writes:
>
>> powerpc: arch_mmap_rnd() uses hard-coded values, (23-PAGE_SHIFT) for
>> 32-bit and (30-PAGE_SHIFT) for 64-bit, to generate the random offset
>> for the mmap base a
Hi Michael,
On Tue, Feb 7, 2017 at 7:57 AM, Michael Ellerman wrote:
> Bhupesh Sharma writes:
>
>> powerpc: arch_mmap_rnd() uses hard-coded values, (23-PAGE_SHIFT) for
>> 32-bit and (30-PAGE_SHIFT) for 64-bit, to generate the random offset
>> for the mmap base a
On Fri, Feb 10, 2017 at 4:31 PM, Michael Ellerman wrote:
> Bhupesh Sharma writes:
>
>> HI Michael,
>>
>> On Thu, Feb 2, 2017 at 3:53 PM, Michael Ellerman wrote:
>>> Bhupesh Sharma writes:
>>>
>>>> powerpc: arch_mmap_rnd() uses hard
Hi Michael,
On Fri, Feb 10, 2017 at 4:41 PM, Bhupesh Sharma wrote:
> On Fri, Feb 10, 2017 at 4:31 PM, Michael Ellerman wrote:
>> Bhupesh Sharma writes:
>>
>>> HI Michael,
>>>
>>> On Thu, Feb 2, 2017 at 3:53 PM, Michael Ellerman
>>> wro
Hi Michael,
On Thu, Feb 16, 2017 at 10:19 AM, Bhupesh Sharma wrote:
> Hi Michael,
>
> On Fri, Feb 10, 2017 at 4:41 PM, Bhupesh Sharma wrote:
>> On Fri, Feb 10, 2017 at 4:31 PM, Michael Ellerman
>> wrote:
>>> Bhupesh Sharma writes:
>>>
>>>> H
, platform
developers may choose where to place this compromise.
Also this patch keeps the default values as new minimums.
Signed-off-by: Bhupesh Sharma
Reviewed-by: Kees Cook
---
* Changes since v2:
v2 can be seen here (https://patchwork.kernel.org/patch/9551509/)
- Changed a few minimum and
Hi Michael,
On Wed, Mar 29, 2017 at 1:15 AM, Bhupesh Sharma wrote:
> powerpc arch_mmap_rnd() currently uses hard-coded values - (23-PAGE_SHIFT) for
> 32-bit and (30-PAGE_SHIFT) for 64-bit, to generate the random offset
> for the mmap base address for a ASLR ELF.
>
> This patch
Hi Aneesh,
On Thu, Apr 13, 2017 at 12:06 PM, Aneesh Kumar K.V
wrote:
> Bhupesh Sharma writes:
>
>> powerpc arch_mmap_rnd() currently uses hard-coded values - (23-PAGE_SHIFT)
>> for
>> 32-bit and (30-PAGE_SHIFT) for 64-bit, to generate the random offset
>> for th
On Thu, Apr 13, 2017 at 12:28 PM, Aneesh Kumar K.V
wrote:
>
>
> On Thursday 13 April 2017 12:22 PM, Bhupesh Sharma wrote:
>>
>> Hi Aneesh,
>>
>> On Thu, Apr 13, 2017 at 12:06 PM, Aneesh Kumar K.V
>> wrote:
>>>
>>> Bhupesh Sharma writes:
&
On Thu, Apr 13, 2017 at 12:39 PM, Balbir Singh wrote:
>>>
>>> Yes. It was derived from TASK_SIZE :
>>>
>>> http://lxr.free-electrons.com/source/arch/powerpc/include/asm/processor.h#L105
>>>
>>
>> That is getting update to 128TB by default and conditionally to 512TB
>>
>
> Since this is compile tim
Hi Michael,
On Wed, Apr 19, 2017 at 7:59 PM, Michael Ellerman wrote:
> Add powerpc support for mmap_rnd_bits and mmap_rnd_compat_bits, which are two
> sysctls that allow a user to configure the number of bits of randomness used
> for
> ASLR.
>
> Because of the way the Kconfig for ARCH_MMAP_RND_B
s 64-bit, but also the configured PAGE_SIZE. Furthermore now that we
> have 128TB address space support on Book3S, we also have to take that into
> account.
>
> Finally we can wire up the value in arch_mmap_rnd().
>
> Signed-off-by: M
7fff8a68-7fff8a6a r-xp 00:00 0
[vdso]
7fffc6d9-7fffc6dc rw-p 00:00 0
[stack]
Done
Cc: Anton Blanchard
Cc: Daniel Cashman
Cc: Kees Cook
Cc: Michael Ellerman
Cc: Benjamin Herrenschmidt
Signed-off-by: Bhupesh Sharma
---
arch/power
On Wed, Jun 7, 2017 at 2:59 PM, Michael Ellerman wrote:
> Daniel Micay writes:
>
>> Rather than doing this, the base should just be split for an ELF
>> interpreter like PaX.
>
> I don't quite parse that, I think you mean PaX uses a different base for
> an ELF interpreter vs a regular ET_DYN?
I a
n which reads the
'MAX_PHYSMEM_BITS' value from vmcoreinfo in a arch-independent fashion
is available here:
[0].
https://github.com/bhupesh-sharma/makedumpfile/blob/remove-max-phys-mem-bit-v1/arch/ppc64.c#L471
Cc: Boris Petkov
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: James Morse
Cc: Ma
ito Hagio
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: ke...@lists.infradead.org
Bhupesh Sharma (3):
crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo
arm
ok at the same.
[0]. http://lists.infradead.org/pipermail/kexec/2019-November/023963.html
[1].
https://github.com/bhupesh-sharma/makedumpfile/tree/52-bit-va-support-via-vmcore-upstream-v4
Regards,
Bhupesh
>
> Thanks,
> -Takahiro Akashi
>
> On Mon, Nov 11, 2019 at 01:31:19PM +0530, B
Hi Akashi,
On Fri, Nov 15, 2019 at 7:29 AM AKASHI Takahiro
wrote:
>
> Bhupesh,
>
> On Fri, Nov 15, 2019 at 01:24:17AM +0530, Bhupesh Sharma wrote:
> > Hi Akashi,
> >
> > On Wed, Nov 13, 2019 at 12:11 PM AKASHI Takahiro
> > wrote:
> > >
> > &g
Hi Dave,
On 03/11/2019 02:35 PM, Dave Young wrote:
Hi Bhupesh,
On 03/10/19 at 03:34pm, Bhupesh Sharma wrote:
Changes since v1:
- v1 was sent out as a single patch which can be seen here:
http://lists.infradead.org/pipermail/kexec/2019-February/022411.html
- v2 breaks the
27;SECTIONS_SHIFT' value in user-land.
A reference 'makedumpfile' implementation which reads the
'MAX_PHYSMEM_BITS' value from vmcoreinfo in a arch-independent fashion
is available here:
[0].
https://github.com/bhupesh-sharma/makedumpfile/blob/remove-max-phys-mem-bit-v1/
Morse
Cc: Will Deacon
Cc: Boris Petkov
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: Michael Ellerman
Cc: Paul Mackerras
Cc: Benjamin Herrenschmidt
Cc: Dave Anderson
Cc: Kazuhito Hagio
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: lin
n which reads the
'MAX_PHYSMEM_BITS' value from vmcoreinfo in a arch-independent fashion
is available here:
[0].
https://github.com/bhupesh-sharma/makedumpfile/blob/remove-max-phys-mem-bit-v1/arch/ppc64.c#L471
Cc: Boris Petkov
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: James Morse
Cc: W
: Paul Mackerras
Cc: Benjamin Herrenschmidt
Cc: Dave Anderson
Cc: Kazuhito Hagio
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: ke...@lists.infradead.org
Signed-off-by: Bhupesh Sharma
---
Documentation/kdum
is Petkov
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: Michael Ellerman
Cc: Dave Anderson
Cc: Dave Young
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: ke...@lists.infradead.org
Signed-off-by: Bhupesh Sharma
-
Hi Amit,
On Fri, Feb 21, 2020 at 2:36 PM Amit Kachhap wrote:
>
> Hi Bhupesh,
>
> On 1/13/20 5:44 PM, Bhupesh Sharma wrote:
> > Hi James,
> >
> > On 01/11/2020 12:30 AM, Dave Anderson wrote:
> >>
> >> - Original Message -
> >>>
Hi David,
Thanks for the patch.
On Mon, Jan 14, 2019 at 6:29 PM David Hildenbrand wrote:
>
> This will be done by free_reserved_page().
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Bhupesh Sharma
> Cc: James Morse
> Cc: Marc Zyngier
> Cc: Dave Kleikamp
>
y marking pages as PG_reserved is not necessary, they are
> already in the desired state (otherwise they would have been handed over
> to the buddy as free pages and bad things would happen).
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: James Morse
> Cc: Bhupesh Shar
o Molnar
Cc: Thomas Gleixner
Cc: Michael Ellerman
Cc: Paul Mackerras
Cc: Benjamin Herrenschmidt
Cc: Dave Anderson
Cc: Kazuhito Hagio
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: ke...@lists.infradead.org
Bhupe
n which reads the
'MAX_PHYSMEM_BITS' value from vmcoreinfo in a arch-independent fashion
is available here:
[0].
https://github.com/bhupesh-sharma/makedumpfile/blob/remove-max-phys-mem-bit-v1/arch/ppc64.c#L471
Cc: Boris Petkov
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: James Morse
Cc: W
On Tue, Nov 19, 2019 at 12:03 PM Prabhakar Kushwaha
wrote:
>
> Hi Akashi,
>
> On Fri, Nov 15, 2019 at 7:29 AM AKASHI Takahiro
> wrote:
> >
> > Bhupesh,
> >
> > On Fri, Nov 15, 2019 at 01:24:17AM +0530, Bhupesh Sharma wrote:
> > > Hi Akashi,
>
Hi Dave,
On Thu, Nov 21, 2019 at 8:51 AM Dave Young wrote:
>
> On 11/11/19 at 01:31pm, Bhupesh Sharma wrote:
> > Changes since v3:
> >
> > - v3 can be seen here:
> > http://lists.infradead.org/pipermail/kexec/2019-March/022590.html
> >
: Kazuhito Hagio
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: ke...@lists.infradead.org
Bhupesh Sharma (5):
crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo
n which reads the
'MAX_PHYSMEM_BITS' value from vmcoreinfo in a arch-independent fashion
is available here:
[0].
https://github.com/bhupesh-sharma/makedumpfile/blob/remove-max-phys-mem-bit-v1/arch/ppc64.c#L471
Cc: Boris Petkov
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: James Morse
Cc: Ma
f-by: Bhupesh Sharma
---
arch/arm64/include/asm/pgtable-hwdef.h | 1 +
arch/arm64/kernel/crash_core.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h
b/arch/arm64/include/asm/pgtable-hwdef.h
index d9fbd433cc17..d2e7aff5821e 100644
--- a/
Fix a simple typo in arm64/memory.rst
Cc: Jonathan Corbet
Cc: James Morse
Cc: Mark Rutland
Cc: Will Deacon
Cc: Steve Capper
Cc: Catalin Marinas
Cc: Ard Biesheuvel
Cc: linux-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Bhupesh
: Paul Mackerras
Cc: Benjamin Herrenschmidt
Cc: Dave Anderson
Cc: Kazuhito Hagio
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: ke...@lists.infradead.org
Signed-off-by: Bhupesh Sharma
---
Documentation/admin-guide/
Cc: Ard Biesheuvel
Cc: Dave Anderson
Cc: Kazuhito Hagio
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: ke...@lists.infradead.org
Signed-off-by: Bhupesh Sharma
---
Documentation/admin-guide/kdump/vmcoreinfo.rst | 6 ++
1 file changed, 6 insertions(+)
diff
mes Morse
Cc: Mark Rutland
Cc: Will Deacon
Cc: Steve Capper
Cc: Catalin Marinas
Cc: Ard Biesheuvel
Cc: Michael Ellerman
Cc: Paul Mackerras
Cc: Benjamin Herrenschmidt
Cc: Dave Anderson
Cc: Kazuhito Hagio
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.
n which reads the
'MAX_PHYSMEM_BITS' value from vmcoreinfo in a arch-independent fashion
is available here:
[0].
https://github.com/bhupesh-sharma/makedumpfile/blob/remove-max-phys-mem-bit-v1/arch/ppc64.c#L471
Cc: Boris Petkov
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: James Morse
Cc: Ma
v@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: ke...@lists.infradead.org
Bhupesh Sharma (5):
crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo
arm64/crash_core: Export TCR_EL1.T1SZ i
n which reads the
'MAX_PHYSMEM_BITS' value from vmcoreinfo in a arch-independent fashion
is available here:
[0].
https://github.com/bhupesh-sharma/makedumpfile/blob/remove-max-phys-mem-bit-v1/arch/ppc64.c#L471
Cc: Boris Petkov
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: James Morse
Cc: Ma
f-by: Bhupesh Sharma
---
arch/arm64/include/asm/pgtable-hwdef.h | 1 +
arch/arm64/kernel/crash_core.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h
b/arch/arm64/include/asm/pgtable-hwdef.h
index d9fbd433cc17..d2e7aff5821e 100644
--- a/
Fix a simple typo in arm64/memory.rst
Cc: Jonathan Corbet
Cc: James Morse
Cc: Mark Rutland
Cc: Will Deacon
Cc: Steve Capper
Cc: Catalin Marinas
Cc: Ard Biesheuvel
Cc: linux-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Bhupesh
: Paul Mackerras
Cc: Benjamin Herrenschmidt
Cc: Dave Anderson
Cc: Kazuhito Hagio
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: ke...@lists.infradead.org
Signed-off-by: Bhupesh Sharma
---
Documentation/admin-guide/
Cc: Ard Biesheuvel
Cc: Dave Anderson
Cc: Kazuhito Hagio
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: ke...@lists.infradead.org
Signed-off-by: Bhupesh Sharma
---
Documentation/admin-guide/kdump/vmcoreinfo.rst | 6 ++
1 file changed, 6 insertions(+)
diff
Hi Will,
On Fri, Nov 29, 2019 at 3:54 PM Will Deacon wrote:
>
> On Fri, Nov 29, 2019 at 01:53:36AM +0530, Bhupesh Sharma wrote:
> > Changes since v4:
> >
> > - v4 can be seen here:
> > http://lists.infradead.org/pipermail/kexec/2019-Novemb
Hi Boris,
On Sat, Dec 14, 2019 at 5:57 PM Borislav Petkov wrote:
>
> On Fri, Nov 29, 2019 at 01:53:36AM +0530, Bhupesh Sharma wrote:
> > Bhupesh Sharma (5):
> > crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo
> > arm64/crash_core:
Hi James,
On 12/12/2019 04:02 PM, James Morse wrote:
Hi Bhupesh,
I am sorry this review mail skipped my attention due to holidays and
focus on other urgent issues.
On 29/11/2019 19:59, Bhupesh Sharma wrote:
Add documentation for TCR_EL1.T1SZ variable being added to
vmcoreinfo.
It
Hi James,
On 12/12/2019 04:02 PM, James Morse wrote:
Hi Bhupesh,
On 29/11/2019 19:59, Bhupesh Sharma wrote:
vabits_actual variable on arm64 indicates the actual VA space size,
and allows a single binary to support both 48-bit and 52-bit VA
spaces.
If the ARMv8.2-LVA optional feature is
Hi James,
On 01/11/2020 12:30 AM, Dave Anderson wrote:
- Original Message -
Hi Bhupesh,
On 25/12/2019 19:01, Bhupesh Sharma wrote:
On 12/12/2019 04:02 PM, James Morse wrote:
On 29/11/2019 19:59, Bhupesh Sharma wrote:
vabits_actual variable on arm64 indicates the actual VA space
linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: ke...@lists.infradead.org
Tested-by: John Donnelly
Signed-off-by: Bhupesh Sharma
---
Documentation/admin-guide/kdump/vmcoreinfo.rst | 5 +
kernel/crash_core.c| 1 +
2 files changed, 6
Cc: scott.bran...@broadcom.com
Cc: Amit Kachhap
Cc: x...@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: ke...@lists.infradead.org
Bhupesh Sharma (2):
crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BI
Hello,
On Thu, May 14, 2020 at 12:22 AM Bhupesh Sharma wrote:
>
> Apologies for the delayed update. Its been quite some time since I
> posted the last version (v5), but I have been really caught up in some
> other critical issues.
>
> Changes since v5:
>
Hello Scott,
On Thu, Jun 4, 2020 at 12:17 AM Scott Branden
wrote:
>
> Hi Bhupesh,
>
> Would be great to get this patch series upstreamed?
>
> On 2019-12-25 10:49 a.m., Bhupesh Sharma wrote:
> > Hi James,
> >
> > On 12/12/2019 04:02 PM, James Morse wrote:
>
Hello Catalin, Will,
On Tue, Jun 2, 2020 at 10:54 AM Bhupesh Sharma wrote:
>
> Hello,
>
> On Thu, May 14, 2020 at 12:22 AM Bhupesh Sharma wrote:
> >
> > Apologies for the delayed update. Its been quite some time since I
> > posted the last version (v5), but I have
gt; changes are present)
> When I used crash utility, following is the error:
>
> Thanks,
> -Bharat
>
>
> -Original Message-
> From: Scott Branden [mailto:scott.bran...@broadcom.com]
> Sent: Thursday, April 30, 2020 4:34 AM
> To: Bhupesh Sharma; Amit Kachhap
>
On Thu, Jul 2, 2020 at 10:45 PM Catalin Marinas wrote:
>
> On Thu, 14 May 2020 00:22:35 +0530, Bhupesh Sharma wrote:
> > Apologies for the delayed update. Its been quite some time since I
> > posted the last version (v5), but I have been really caught up in some
> &g
powerpc architecture (both 64-bit and 32-bit) supports stack protector
mechanism since some time now [see commit 06ec27aea9fc ("powerpc/64:
add stack protector support")].
Update stackprotector arch support documentation to reflect the same.
Signed-off-by: Bhupesh Sharma
---
Doc
On Thu, May 30, 2019 at 6:25 PM Michael Ellerman wrote:
>
> Bhupesh Sharma writes:
> > powerpc architecture (both 64-bit and 32-bit) supports stack protector
> > mechanism since some time now [see commit 06ec27aea9fc ("powerpc/64:
> > add stack protector support"
ld be copied in.
> diff --git a/arch/x86/include/asm/page_64_types.h
> b/arch/x86/include/asm/page_64_types.h
> index 793c14c372cb..288b065955b7 100644
> --- a/arch/x86/include/asm/page_64_types.h
> +++ b/arch/x86/include/asm/page_64_types.h
> @@ -48,7 +48,7 @@
>
> #define __START_KERNEL_map _AC(0x8000, UL)
>
> -/* See Documentation/x86/x86_64/mm.txt for a description of the memory map.
> */
> +/* See Documentation/x86/x86_64/mm.rst for a description of the memory map.
> */
>
> #define __PHYSICAL_MASK_SHIFT 52
>
> diff --git a/arch/x86/include/asm/pgtable_64_types.h
> b/arch/x86/include/asm/pgtable_64_types.h
> index 88bca456da99..52e5f5f2240d 100644
> --- a/arch/x86/include/asm/pgtable_64_types.h
> +++ b/arch/x86/include/asm/pgtable_64_types.h
> @@ -103,7 +103,7 @@ extern unsigned int ptrs_per_p4d;
> #define PGDIR_MASK (~(PGDIR_SIZE - 1))
>
> /*
> - * See Documentation/x86/x86_64/mm.txt for a description of the memory map.
> + * See Documentation/x86/x86_64/mm.rst for a description of the memory map.
>*
>* Be very careful vs. KASLR when changing anything here. The KASLR address
>* range must not overlap with anything except the KASAN shadow area, which
> diff --git a/arch/x86/kernel/cpu/microcode/amd.c
> b/arch/x86/kernel/cpu/microcode/amd.c
> index e1f3ba19ba54..06d4e67f31ab 100644
> --- a/arch/x86/kernel/cpu/microcode/amd.c
> +++ b/arch/x86/kernel/cpu/microcode/amd.c
> @@ -61,7 +61,7 @@ static u8 amd_ucode_patch[PATCH_MAX_SIZE];
>
> /*
>* Microcode patch container file is prepended to the initrd in cpio
> - * format. See Documentation/x86/microcode.txt
> + * format. See Documentation/x86/microcode.rst
>*/
> static const char
> ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin";
> diff --git a/arch/x86/kernel/kexec-bzimage64.c
> b/arch/x86/kernel/kexec-bzimage64.c
> index 22f60dd26460..b07e7069b09e 100644
> --- a/arch/x86/kernel/kexec-bzimage64.c
> +++ b/arch/x86/kernel/kexec-bzimage64.c
> @@ -416,7 +416,7 @@ static void *bzImage64_load(struct kimage *image, char
> *kernel,
> efi_map_offset = params_cmdline_sz;
> efi_setup_data_offset = efi_map_offset + ALIGN(efi_map_sz, 16);
>
> - /* Copy setup header onto bootparams. Documentation/x86/boot.txt */
> + /* Copy setup header onto bootparams. Documentation/x86/boot.rst */
> setup_header_size = 0x0202 + kernel[0x0201] - setup_hdr_offset;
For the arm, arm64 and x86 kexec bits:
Reviewed-by: Bhupesh Sharma
Thanks,
Bhupesh
Hi Jonathan,
On Fri, May 31, 2019 at 8:44 PM Michael Ellerman wrote:
>
> Jonathan Corbet writes:
> > On Thu, 30 May 2019 18:37:46 +0530
> > Bhupesh Sharma wrote:
> >
> >> > This should probably go via the documentation tree?
> >> >
> >&g
Cc: linux-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Bhupesh Sharma
---
Resend, this time Cc'ing Jonathan and doc-list.
Documentation/features/debug/stackprotector/arch-support.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
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