On 10/14/24 4:54 PM, Ritesh Harjani (IBM) wrote:
> Madhavan Srinivasan writes:
>
>> On 10/11/24 8:30 PM, Ritesh Harjani (IBM) wrote:
>>> We anyway don't use any return values from fadump_cma_init(). Since
>>> fadump_reserve_mem() from where fadump_cma_init()
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi Linus,
Please pull my first pullrequest for powerpc tree.
My gpg key is available in pgpkeys.git and it is signed by Michael Ellerman and
others.
https://git.kernel.org/pub/scm/docs/kernel/pgpkeys.git/commit/?id=5931604633197aa5cdbf6c4c9de0f
4e4
> free_unref_page+0x458/0x6d0
> init_cma_reserved_pageblock+0x114/0x198
> cma_init_reserved_areas+0x270/0x3e0
> do_one_initcall+0x80/0x2f8
> kernel_init_freeable+0x33c/0x530
> kernel_init+0x34/0x26c
> ret_from_kernel_user_thread+0x14/0x1c
>
Changes looks fine to me.
Revi
On 10/11/24 8:30 PM, Ritesh Harjani (IBM) wrote:
> This patch refactors all CMA related initialization and alignment code
> to within fadump_cma_init() which gets called in the end. This also means
> that we keep [reserve_dump_area_start, boot_memory_size] page aligned
> during fadump_reserve_me
On 9/20/24 11:17 PM, Colton Lewis wrote:
> Make sure powerpc uses the arch-specific function now that those have
> been reorganized.
>
Changes looks fine to me.
Acked-by: Madhavan Srinivasan
> Signed-off-by: Colton Lewis
> ---
> arch/powerpc/perf/callchain.c| 2
ned-off-by: Colton Lewis
For powerpc changes
Acked-by: Madhavan Srinivasan
> ---
> arch/arm64/include/asm/perf_event.h | 6 +++---
> arch/arm64/kernel/perf_callchain.c | 4 ++--
> arch/powerpc/include/asm/perf_event_server.h | 6 +++---
> arch/powerpc/per
On 10/14/24 4:54 PM, Ritesh Harjani (IBM) wrote:
> Madhavan Srinivasan writes:
>
>> On 10/11/24 8:30 PM, Ritesh Harjani (IBM) wrote:
>>> We anyway don't use any return values from fadump_cma_init(). Since
>>> fadump_reserve_mem() from where fadump_cma_init()
On 10/11/24 8:30 PM, Ritesh Harjani (IBM) wrote:
> We anyway don't use any return values from fadump_cma_init(). Since
> fadump_reserve_mem() from where fadump_cma_init() gets called today,
> already has the required checks.
> This patch makes this function return type as void. Let's also handle
On 10/2/24 5:31 PM, Corentin LABBE wrote:
> Hello
>
> I have a 8335-GCA POWER8 which got a kernel crash during boot:
> [ 11.754238] Kernel attempted to read user page (0) - exploit attempt?
> (uid: 0)
> [ 11.754437] BUG: Kernel NULL pointer dereference on read at 0x
> [ 11.754499
On 9/30/24 1:57 PM, Christophe Leroy wrote:
>
>
> Le 30/09/2024 à 09:56, Zhang Zekun a écrit :
>> [Vous ne recevez pas souvent de courriers de zhangzeku...@huawei.com.
>> Découvrez pourquoi ceci est important à
>> https://aka.ms/LearnAboutSenderIdentification ]
>>
>> The of_property_read_u64
On 9/13/24 2:21 AM, Colton Lewis wrote:
For clarity, rename the arch-specific definitions of these functions
to perf_arch_* to denote they are arch-specifc. Define the
generic-named functions in one place where they can call the
arch-specific ones as needed.
Signed-off-by: Colton Lewis
---
ed-by: Madhavan Srinivasan
Cc: Michael Ellerman
Cc: Nicholas Piggin
Cc: Christophe Leroy
Cc: Naveen N Rao
Cc: Kajol Jain
Cc: Athira Rajeev
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Namhyung Kim
---
arch/powerpc/perf/core-book3s.c | 4 +++-
1 file changed, 3 insertions(+), 1 del
-single
vdso: 2500 times in 0.787943615 seconds
libc: 2500 times in 14.101887252 seconds
syscall: 2500 times in 14.047475082 seconds
Impressive, thanks for enabling it.
Tested-by: Madhavan Srinivasan
Signed-off-by: Christophe Leroy
---
v5:
- VDSO32 for both PPC32 and PPC64 is
Add documentation to 'papr_hcalls.rst' describing the
input, output and return values of the H_HTM hcall as
per the internal specification.
Signed-off-by: Madhavan Srinivasan
---
Changelog v2:
- No changes
Changelog v1:
- Updated commit message to include htmdump folder files
Doc
s/kernel/debug/powerpc/htmdump
coreindexonchip htmtype nodalchipindex nodeindex trace
Signed-off-by: Madhavan Srinivasan
---
Changelog v2:
- Made driver as modules based on review comments
Changelog v1:
- Changed from tristate to bool with dependency flags
- Trimmed the include headers
arch/pow
Define macros and wrapper functions to handle
H_HTM (Hardware Trace Macro) hypervisor call.
H_HTM is new HCALL added to export data from
Hardware Trace Macro (HTM) function.
Signed-off-by: Madhavan Srinivasan
---
Changelog v2:
- No changes
Changelog v1:
- No changes
arch/powerpc/include/asm
On 8/27/24 12:06 PM, Michael Ellerman wrote:
Maddy will be helping out with upstream maintenance, add him as a
reviewer.
Signed-off-by: Michael Ellerman
Acked-by: Madhavan Srinivasan
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
/CANiq72=QeTgtZL4k9=4CJP6C_Hv=rh3fsn3b9s3kfopxkyw...@mail.gmail.com/
Signed-off-by: Madhavan Srinivasan
---
Changelog v2:
- Fixed the loop upper limit from KSYM_NAME_LEN to
(KSYM_NAME_LEN - 1) since last index is initialized
with zero at the end of the loop. Thanks mpe for
pointing it out.
- Checkpatch scr
On 8/13/24 1:11 PM, Michael Ellerman wrote:
Madhavan Srinivasan writes:
Currently exec-target.c file is linked as static and this
post a requirement to install libc dev package to build.
I think specifically the problem is that the test requires a static
libc, which is packaged separately in
://lore.kernel.org/linuxppc-dev/CANiq72=QeTgtZL4k9=4CJP6C_Hv=rh3fsn3b9s3kfopxkyw...@mail.gmail.com/
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Updated commit message based on Miguel's review comments
arch/powerpc/xmon/xmon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 8/14/24 3:53 PM, Miguel Ojeda wrote:
On Wed, Aug 14, 2024 at 12:10 PM Madhavan Srinivasan
wrote:
Reported-by: Miguel Ojeda
Signed-off-by: Madhavan Srinivasan
Link - https://lore.kernel.org/linuxppc-dev/87ilc8ym6v.fsf@mail.lhotse/
Thanks for fixing this!
The "Link -" shoul
_symbol__r2_resolution_symbol
c01021a0 3c4c0249 addis r2,r12,585
c01021a4 3842ae60 addir2,r2,-20896
c01021a8 7c0802a6 mflrr0
c01021ac 6000 nop
.
Reported-by: Miguel Ojeda
Signed-off-by: Madhavan Srinivasan
Link - https://lore.kernel.or
status
exec_target.c is using "syscall" library function which
could be replaced with a inline assembly and the same is
proposed as a fix here.
Suggested-by: Michael Ellerman
Signed-off-by: Madhavan Srinivasan
---
Chnagelog v1:
- Add comment for clobber register and proper list of
On 8/9/24 10:24 AM, Christophe Leroy wrote:
Le 09/08/2024 à 06:25, Madhavan Srinivasan a écrit :
On 8/6/24 12:24 PM, Christophe Leroy wrote:
Le 05/08/2024 à 10:30, Madhavan Srinivasan a écrit :
Currently exec-target.c file is linked as static and this
post a requirement to install libc
On 8/6/24 12:24 PM, Christophe Leroy wrote:
Le 05/08/2024 à 10:30, Madhavan Srinivasan a écrit :
Currently exec-target.c file is linked as static and this
post a requirement to install libc dev package to build.
Without it, build-breaks when compiling selftest/powerpc/benchmark.
CC
status
exec_target.c is using "syscall" library function which
could be replaced with a inline assembly and the same is
proposed as a fix here.
Suggested-by: Michael Ellerman
Signed-off-by: Madhavan Srinivasan
---
tools/testing/selftests/powerpc/benchmarks/Makefile| 2 +-
.
case.
Signed-off-by: Gautam Menghani
---
V1 -> V2:
1. Reword changelog to point out mutual exclusivity of HFSCR bits.
2. Reword commit message to match other commits in book3s_hv.c
Minor: I guess you mean "Reword the subject line"
Reviewed-by: Madhavan Srinivasan
lchipindex nodeindex trace
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Updated commit message to include htmdump folder files
Documentation/arch/powerpc/papr_hcalls.rst | 11 +++
1 file changed, 11 insertions(+)
diff --git a/Documentation/arch/powerpc/papr_hcalls.rst
b/Doc
path
# pwd
/sys/kernel/debug/powerpc/htmdump
# ls
coreindexonchip htmtype nodalchipindex nodeindex trace
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Changed from tristate to bool with dependency flags
- Trimmed the include headers
arch/powerpc/platforms/pseries/Kconfig |
Define macros and wrapper functions to handle
H_HTM (Hardware Trace Macro) hypervisor call.
H_HTM is new HCALL added to export data from
Hardware Trace Macro (HTM) function.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- No changes
arch/powerpc/include/asm/hvcall.h | 34
On 6/22/24 1:57 PM, Ritesh Harjani (IBM) wrote:
Madhavan Srinivasan writes:
Add documentation to 'papr_hcalls.rst' describing the
input, output and return values of the H_HTM hcall as
per the internal specification.
Signed-off-by: Madhavan Srinivasan
---
Documentation/ar
On 6/22/24 1:10 PM, Ritesh Harjani (IBM) wrote:
This is a generic review and I haven't looked into the PAPR spec for
htmdump hcall and it's interface.
Sure
Madhavan Srinivasan writes:
This patch adds debugfs interface to export Hardware Trace Macro (HTM)
function data in a
Add documentation to 'papr_hcalls.rst' describing the
input, output and return values of the H_HTM hcall as
per the internal specification.
Signed-off-by: Madhavan Srinivasan
---
Documentation/arch/powerpc/papr_hcalls.rst | 11 +++
1 file changed, 11 insertions(+)
di
path
# pwd
/sys/kernel/debug/powerpc/htmdump
# ls
coreindexonchip htmtype nodalchipindex nodeindex trace
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/platforms/pseries/Kconfig | 8 ++
arch/powerpc/platforms/pseries/Makefile | 1 +
arch/powerpc/platforms/pseries/htmdump.c |
Define macros and wrapper functions to handle
H_HTM (Hardware Trace Macro) hypervisor call.
H_HTM is new HCALL added to export data from
Hardware Trace Macro (HTM) function.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/hvcall.h | 34 +++
arch
On 4/29/24 7:39 PM, Michael Ellerman wrote:
Madhavan Srinivasan writes:
When running `make -C powerpc/pmu run_tests` from top level selftests
directory, currently this error is being reported
make: Entering directory '/home/maddy/linux/tools/testing/selftests/powerpc/pmu'
M
On 4/22/24 7:04 PM, Michael Ellerman wrote:
The pmu Makefile has grown more sub directories over the years. Rather
than open coding the rules for each subdir, use for loops.
Nice cleanup. Thanks.
Tested-by: Madhavan Srinivasan
Signed-off-by: Michael Ellerman
---
tools/testing
On 3/26/24 3:10 PM, Gautam Menghani wrote:
PAPR hypervisor has introduced three new counters in the VPA area of
LPAR CPUs for KVM L2 guest (see [1] for terminology) observability - 2
for context switches from host to guest and vice versa, and 1 counter
for getting the total time spent inside the
ile.
Also remove the CFLAGS and GIT_VERSION macros from powerpc/
folder Makefile since the same is definied in flags.mk
Signed-off-by: Madhavan Srinivasan
---
tools/testing/selftests/powerpc/Makefile | 7 +--
tools/testing/selftests/powerpc/alignment/Makefile | 1 +
too
ing specific sub-folder test directly,
a new rule file has been addded by the patch called "flags.mk" under
selftest/powerpc/ folder and is linked to all the Makefile of powerpc/pmu
sub-folders.
Reported-by: Sachin Sant
Signed-off-by: Madhavan Srinivasan
---
Changelog RFC:
- Rename the r
In some powerpc/ sub-folder Makefiles, CFLAGS are
defined before lib.mk include. Clean it up by
re-ordering it to follow after the mk include.
This is needed to support sub-folders in powerpc/
buildable on its own.
Signed-off-by: Madhavan Srinivasan
---
.../selftests/powerpc/benchmarks/Makefile
se of executing specific sub-folder test directly,
a new rule file has been addded by the patch called "include.mk" under
selftest/powerpc/ folder and is linked to all Makefile of powerpc/pmu
sub-folders.
Signed-off-by: Madhavan Srinivasan
---
tools/testing/selftests/powerpc/include.mk
Base enablement patch to register performance monitoring
hardware support for Power11. Most of fields are copied
from power10_pmu struct for power11_pmu struct.
Signed-off-by: Madhavan Srinivasan
---
Changelog V2:
- No change
Changelog v1:
- Copied power10 struct for power11 with name change
-off-by: Madhavan Srinivasan
---
Changelog v2:
- added macro to address logical PVR to
handle compat mode PCR setting
- removed power11 functions which were
just re-direction to power10. Instead
used power10 functions as suggested.
Changelog v1
- No change
arch/powerpc/include/asm
On 2/5/24 2:13 PM, Aneesh Kumar K.V wrote:
Madhavan Srinivasan writes:
reg.h is updated with Power11 pvr. pvr_mask value of 0x0F07
means we are arch v3.1 compliant.
If it is called arch v3.1, it will conflict with.
#define PVR_ARCH_31 0x0f06
Nice catch. My bad, missed to
Base enablement patch to register performance monitoring
hardware support for Power11. Most of fields are copied
from power10_pmu struct for power11_pmu struct.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Copied power10 struct for power11 with name change
arch/powerpc/perf/core
relevant
Power11 setup/restore and device tree routines.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- no change in this patch.
arch/powerpc/include/asm/cpu_setup.h | 2 ++
arch/powerpc/include/asm/cputable.h | 3 ++
arch/powerpc/include/asm/mce.h| 1 +
arch
Update the Power11 PVR to json mapfile to enable
json events. Power11 is PowerISA v3.1 compliant
and support Power10 events.
Signed-off-by: Madhavan Srinivasan
---
tools/perf/pmu-events/arch/powerpc/mapfile.csv | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/pmu-events/arch
: Madhavan Srinivasan
---
arch/powerpc/perf/Makefile | 3 +-
arch/powerpc/perf/core-book3s.c | 2 +
arch/powerpc/perf/internal.h| 1 +
arch/powerpc/perf/power11-events-list.h | 8 +
arch/powerpc/perf/power11-pmu.c | 475
5 files
Power11 setup/restore and device tree routines.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/cpu_setup.h | 2 ++
arch/powerpc/include/asm/cputable.h | 3 ++
arch/powerpc/include/asm/mce.h| 1 +
arch/powerpc/include/asm/mmu.h| 1 +
arch
On 10/3/23 3:16 AM, Gaurav Batra wrote:
When a device is initialized, the driver invokes dma_supported() twice - first
for streaming mappings followed by coherent mappings. For an SR-IOV device,
default window is deleted and DDW created. With vPMEM enabled, TCE mappings
are dynamically created
On 3/2/23 8:49 AM, Madhavan Srinivasan wrote:
On 3/2/23 3:35 AM, Benjamin Gray wrote:
On Wed, 2023-03-01 at 22:39 +0530, Kajol Jain wrote:
From: Madhavan Srinivasan
event.h header already includes utlis.h. Avoid including
the same explicitly in the code when event.h included.
Signed-off
On 3/2/23 3:35 AM, Benjamin Gray wrote:
On Wed, 2023-03-01 at 22:39 +0530, Kajol Jain wrote:
From: Madhavan Srinivasan
event.h header already includes utlis.h. Avoid including
the same explicitly in the code when event.h included.
Signed-off-by: Madhavan Srinivasan
As I understand
On 10/18/22 1:35 PM, Michael Ellerman wrote:
Kajol Jain writes:
Based on getPerfCountInfo v1.018 documentation, some of the
hv_gpci events got deprecated for platforms firmware that
supports counter_info_version 0x8 or above.
Patch fixes the hv_gpci event list by adding a new attribute
group
inator of the metric expression as a fix.
Result in powerpc box after this patch changes:
90: perf all metrics test : Ok
Looks ok, applied. Next time please try to ask others to provide a
Reviewed-by or at least an Acked-by.
Reviewed-by: Madhavan Srinivasan
I did review this patch yesterday. B
On 7/13/22 11:11 AM, Nicholas Piggin wrote:
Excerpts from Kajol Jain's message of July 11, 2022 1:49 pm:
File book3s_hv_p9_entry.c in powerpc/kvm folder consists of functions
like freeze_pmu, switch_pmu_to_guest and switch_pmu_to_host which are
specific to Performance Monitoring Unit(PMU) for
On 5/26/22 12:07 PM, Joel Stanley wrote:
When booting on a machine that uses the compat pmu driver we see this:
[0.071192] GENERIC_COMPAT performance monitor hardware support registered
Sorry that was my mistake.
I agree having it as ISAv3 is better.
Maddy
Which is a bit shouty. Giv
r, file is linked with thirty_two_instruction_loop() in
loop.S from top folder. Since fixed_instruction_loop.S not used, patch
removes the file.
Signed-off-by: Madhavan Srinivasan
---
.../powerpc/pmu/ebb/fixed_instruction_loop.S | 43 ---
1 file changed, 43 deletions(-)
delete m
IBM pseries platform nmem* device
performance stats using this interface.
Result from power9 pseries lpar with 2 nvdimm device:
Patchset looks fine to me.
Reviewed-by: Madhavan Srinivasan
Ex: List all event by perf list
command:# perf list nmem
nmem0/cache_rh_cnt
On 10/21/21 11:03 PM, Nathan Lynch wrote:
Nicholas Piggin writes:
Excerpts from Athira Rajeev's message of July 11, 2021 10:25 pm:
During Live Partition Migration (LPM), it is observed that perf
counter values reports zero post migration completion. However
'perf stat' with workload continue
On 8/16/21 12:59 PM, Nicholas Piggin wrote:
Interrupt handling code would like to know whether perf is enabled, to
know whether it should enable MSR[EE] to improve PMI coverage.
Cc: Madhavan Srinivasan
Cc: Athira Rajeev
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/hw_irq.h
On 8/16/21 12:26 PM, Christophe Leroy wrote:
Le 16/08/2021 à 08:44, kajoljain a écrit :
On 8/14/21 6:14 PM, Michael Ellerman wrote:
Christophe Leroy writes:
Le 13/08/2021 à 10:24, Kajol Jain a écrit :
Incase of random sampling, there can be scenarios where SIAR is not
latching sample a
On 8/6/21 4:08 PM, Nicholas Piggin wrote:
Excerpts from Madhavan Srinivasan's message of August 6, 2021 5:33 pm:
On 7/26/21 9:19 AM, Nicholas Piggin wrote:
It can be useful in simulators (with very constrained environments)
to allow some PMCs to run from boot so they can be sampled directly
b
On 7/26/21 9:19 AM, Nicholas Piggin wrote:
It can be useful in simulators (with very constrained environments)
to allow some PMCs to run from boot so they can be sampled directly
by a test harness, rather than having to run perf.
A previous change freezes counters at boot by default, so provid
On 7/14/21 6:09 PM, Nicholas Piggin wrote:
Excerpts from Nicholas Piggin's message of July 12, 2021 12:41 pm:
Excerpts from Athira Rajeev's message of July 10, 2021 12:50 pm:
On 22-Jun-2021, at 4:27 PM, Nicholas Piggin wrote:
KVM PMU management code looks for particular frozen/disabled bi
On 7/2/21 5:57 AM, Nicholas Piggin wrote:
Excerpts from Madhavan Srinivasan's message of July 1, 2021 11:17 pm:
On 6/22/21 4:27 PM, Nicholas Piggin wrote:
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
On 6/22/21 4:27 PM, Nicholas Piggin wrote:
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term th
On 6/16/21 11:56 AM, Christophe Leroy wrote:
Le 16/06/2021 à 05:40, Athira Rajeev a écrit :
On 16-Jun-2021, at 8:53 AM, Madhavan Srinivasan
wrote:
On 6/15/21 8:35 PM, Christophe Leroy wrote:
For your information, I'm getting the following Oops. Detected with
5.13-rc6, it also o
On 6/15/21 8:35 PM, Christophe Leroy wrote:
For your information, I'm getting the following Oops. Detected with
5.13-rc6, it also oopses on 5.12 and 5.11.
Runs ok on 5.10. I'm starting bisecting now.
Thanks for reporting, got the issue. What has happened in this case is
that, pmu device is
architected. The
Yeah as you pointed, this was aimed at IBM system implementations.
Thanks for the patch and patch looks fine to me.
Reviewed-by: Madhavan Srinivasan
I can send a follow up patch to return EINVAL for a non-zero value
other than pmc and pmcsel filed via check_attr_config
to freeze counting based on the Control Register
CTRL[RUN] state. CTRL[RUN] is not set when idle task is
running. Patch adds a check for event attr.exclude_idle to
set MMCR2[FCnWAIT] bit.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/isa207-common.c | 3 +++
arch/powerpc/perf/isa207-common.
for a given platform.
Signed-off-by: Madhavan Srinivasan
---
Changelog v3:
-Made the check_attr_config() to be called for all event type of instead
only for raw event type.
Changelog v2:
-Fixed commit message
Changelog v1:
-Fixed commit message and in-code comments
arch/powerpc/include/asm/perf
Add platform specific attr.config value checks. Patch
includes checks for both power9 and power10.
Signed-off-by: Madhavan Srinivasan
---
Changelog v3:
- No changes
Changelog v2:
- Changed function name as suggested.
- Added name of source document referred for reserved values
Changelog v1
On 4/7/21 5:08 PM, Michael Ellerman wrote:
Madhavan Srinivasan writes:
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 6817331e22ff..c6eeb4fdc5fd 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1958,6 +1958,20
On 3/25/21 6:36 PM, Arnaldo Carvalho de Melo wrote:
Em Wed, Mar 24, 2021 at 10:05:23AM +0530, Madhavan Srinivasan escreveu:
On 3/22/21 8:27 PM, Athira Rajeev wrote:
Performance Monitoring Unit (PMU) registers in powerpc provides
information on cycles elapsed between different stages in the
for a given platform.
"check_attr_config" is valid only for raw event type.
Signed-off-by: Madhavan Srinivasan
---
Changelog v2:
-Fixed commit message
Changelog v1:
-Fixed commit message and in-code comments
arch/powerpc/include/asm/perf_event_server.h | 6 ++
arch/powerpc/perf/c
Add platform specific attr.config value checks. Patch
includes checks for both power9 and power10.
Signed-off-by: Madhavan Srinivasan
---
Changelog v2:
- Changed function name as suggested.
- Added name of source document referred for reserved values
Changelog v1:
- No changes
arch/powerpc
ple_weight structure.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/perf_event_server.h | 2 +-
arch/powerpc/perf/core-book3s.c | 4 ++--
arch/powerpc/perf/isa207-common.c
On 3/10/21 6:46 PM, Alexey Kardashevskiy wrote:
On 26/02/2021 17:50, Madhavan Srinivasan wrote:
Add platform specific attr.config value checks. Patch
includes checks for both power9 and power10.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- No changes.
arch/powerpc/perf/isa207
On 2/26/21 7:33 PM, Paul A. Clarke wrote:
Another drive-by review... just some minor nits, below...
On Fri, Feb 26, 2021 at 12:20:24PM +0530, Madhavan Srinivasan wrote:
Introduce code to support the checking of attr.config* for
values which are reserved for a given platform.
Performance
memory events to use issue
to complete.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
We should also CC stable to include this fix?
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/powe
fixes the functions to handle type value 7 for
CPU_FTR_ARCH_31.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-com
Add platform specific attr.config value checks. Patch
includes checks for both power9 and power10.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- No changes.
arch/powerpc/perf/isa207-common.c | 41 +++
arch/powerpc/perf/isa207-common.h | 2 ++
arch/powerpc
config* values for a given platform.
"check_attr_config" is valid only for raw event type.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
-Fixed commit message and in-code comments
arch/powerpc/include/asm/perf_event_server.h | 6 ++
arch/powerpc/perf/core-book3s.c
On 2/24/21 8:17 PM, Paul A. Clarke wrote:
On Wed, Feb 24, 2021 at 07:58:39PM +0530, Madhavan Srinivasan wrote:
Introduce code to support the checking of attr.config* for
values which are reserved for a given platform.
Performance Monitoring Unit (PMU) configuration registers
have fileds that
Add platform specific attr.config value checks. Patch
includes checks for power9 and power10 platforms.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/isa207-common.c | 41 +++
arch/powerpc/perf/isa207-common.h | 2 ++
arch/powerpc/perf/power10-pmu.c
raw event type.
Suggested-by: Alexey Kardashevskiy
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/perf_event_server.h | 6 ++
arch/powerpc/perf/core-book3s.c | 12
2 files changed, 18 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server
event]
hv_24x7/TOD,chip=?/[Kernel PMU event]
..
Demsg:
[0.000357] printk: console [hvc0] enabled
[0.808592] hv-24x7: read 1530 catalog entries, created 509 event attrs
(0 failures), 275 descs
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Kajol
On 12/17/20 5:02 PM, Kajol Jain wrote:
hv_24x7 performance monitoring unit creates list of supported events
from the event catalog obtained via HCALL. hv_24x7 catalog could also
contain invalid or dummy events (with names like FREE_ or CPM_FREE_ so
Can you also include " RESERVED_NEST*" as
I saw were fixed by
https://github.com/aik/linux/commit/17899eaf88d689 but it is hardly a
replacement. Thanks,
sorry missed this. Will look at this again. Since we will need
generation specific checks for the reserve field.
Maddy
On 04/06/2020 02:34, Madhavan Srinivasan wrote:
On 6/2/
On 11/24/20 10:21 AM, Namhyung Kim wrote:
Hello,
On Mon, Nov 23, 2020 at 8:00 PM Michael Ellerman wrote:
Namhyung Kim writes:
Hi Peter and Kan,
(Adding PPC folks)
On Tue, Nov 17, 2020 at 2:01 PM Namhyung Kim wrote:
Hello,
On Thu, Nov 12, 2020 at 4:54 AM Liang, Kan wrote:
On 11/11/
On 10/22/20 6:55 AM, Michael Ellerman wrote:
Christophe Leroy writes:
Le 21/10/2020 à 10:53, Madhavan Srinivasan a écrit :
In power10 DD1, there is an issue where the
Sampled Instruction Address Register (SIAR)
not latching to the sampled address during
random sampling. This results in
In power10 DD1, there is an issue where the
Sampled Instruction Address Register (SIAR)
not latching to the sampled address during
random sampling. This results in value of 0s
in the SIAR. Patch adds a check to use regs->nip
when SIAR is zero.
Signed-off-by: Madhavan Srinivasan
---
arch/powe
for marked
events. Hence add a check to use the address in Sampled Instruction Address
Register (SIAR) to identify the privilege level.
Signed-off-by: Athira Rajeev
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/core-book3s.c | 14 ++
1 file changed, 14 insertions(+)
diff
Control Register (MMCR2). Patch adds a check to drop
these samples at such conditions.
Signed-off-by: Athira Rajeev
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/core-book3s.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc
if the SIAR_VALID bit is set.
So drop the check for SIAR_VALID and return true always incase of
power10 DD1.
Signed-off-by: Athira Rajeev
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Drop the check for SIER[CMPL] and retur true instead
- Made changes to commit message
arch/powerpc
by: Athira Rajeev
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/perf_event_server.h | 1 +
arch/powerpc/perf/power10-pmu.c | 6 ++
2 files changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_serv
8bits. Patch fixes the current
code to modify the MMCRA[TECM] extraction macro to handle this changes.
Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to
userspace')
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Fixed the commit message
- Fixed the condi
On 10/13/20 9:28 PM, Michal Suchánek wrote:
On Tue, Oct 13, 2020 at 06:27:05PM +0530, Madhavan Srinivasan wrote:
On 10/12/20 4:59 PM, Michal Suchánek wrote:
Hello,
On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote:
Power9 and isa v3.1 has 7bit mantissa field for Threshold
On 10/12/20 4:59 PM, Michal Suchánek wrote:
Hello,
On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote:
Power9 and isa v3.1 has 7bit mantissa field for Threshold Event Counter
^^^ Shouldn't his be 3.0?
My bad, What I meant was
Power9, ISA v3.0 an
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