On Sat, Oct 12, 2013 at 04:40:06AM +0100, Tang Yuantian-B29983 wrote:
Thanks for your review.
+- reg: Offset and length of the clock register set
+- clock-frequency: Indicates input clock frequency of clock block.
+ Will be set by u-boot
Why does the fact this
this patch set.
Sorry for the delay.
This looks ok to me.
Acked-by: Mark Rutland mark.rutl...@arm.com
On 09/26/2013 05:33 PM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch
adds
On Fri, Oct 11, 2013 at 04:18:18AM +0100, Tang Yuantian-B29983 wrote:
Thanks for your review.
See my reply inline
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: 2013年10月10日 星期四 18:04
To: Tang Yuantian-B29983
Cc: ga...@kernel.crashing.org; linuxppc
On Wed, Oct 09, 2013 at 07:38:24AM +0100, yuantian.t...@freescale.com wrote:
From: Tang Yuantian yuantian.t...@freescale.com
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li
On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote:
On 09/02/2013 11:58 PM, Mark Rutland wrote:
Hi,
On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA
On Wed, Aug 28, 2013 at 09:18:55AM +0100, Hongbo Zhang wrote:
On 08/27/2013 07:25 PM, Mark Rutland wrote:
On Tue, Aug 27, 2013 at 11:42:01AM +0100, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch updates the discription of each type of DMA
On Wed, Aug 28, 2013 at 07:54:01AM +0100, Hongbo Zhang wrote:
On 08/27/2013 07:35 PM, Mark Rutland wrote:
On Tue, Aug 27, 2013 at 11:42:02AM +0100, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines
On Tue, Aug 27, 2013 at 11:42:01AM +0100, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch updates the discription of each type of DMA controller and its
channels, it is preparation for adding another new DMA controller binding, it
also fixes some
On Tue, Aug 27, 2013 at 11:42:02AM +0100, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
the device tree nodes for them.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
On Thu, Aug 22, 2013 at 10:00:35PM +0100, Sascha Hauer wrote:
On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
Quoting Tomasz Figa (2013-08-21 14:34:55)
On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote
On Fri, Aug 23, 2013 at 07:34:21AM +0100, Sascha Hauer wrote:
On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
Quoting Sascha Hauer (2013-08-22 14:00:35)
On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland
for this
case (see below). I don't see that we need to leak what is a Linux issue
into the dt.
Thanks,
Mark.
8
From f0d46f36426ded4ba3609d7966452f9925e2 Mon Sep 17 00:00:00 2001
From: Mark Rutland mark.rutl...@arm.com
Date: Fri, 23 Aug 2013 15:46:33 +0100
Subject: [PATCH] clk: add
On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
Quoting Tomasz Figa (2013-08-21 14:34:55)
On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
Quoting Mark Rutland (2013-08-19 02:35:43
On Mon, Aug 19, 2013 at 02:56:10PM +0100, Sudeep KarkadaNagesha wrote:
On 19/08/13 14:02, Rob Herring wrote:
On 08/19/2013 05:19 AM, Mark Rutland wrote:
On Sat, Aug 17, 2013 at 11:09:36PM +0100, Benjamin Herrenschmidt wrote:
On Sat, 2013-08-17 at 12:50 +0200, Tomasz Figa wrote:
I wonder
On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
Quoting Mark Rutland (2013-08-19 02:35:43)
On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote
On Mon, Aug 19, 2013 at 12:34:08PM +0100, Nicolin Chen wrote:
On Mon, Aug 19, 2013 at 12:13:49PM +0100, Mark Rutland wrote:
+ rxtx0-7 Clock source list for tx and rx clock.
+ This clock list should be identical
On Tue, Aug 20, 2013 at 06:19:49AM +0100, Shawn Guo wrote:
On Mon, Aug 19, 2013 at 10:54:33AM +0100, Mark Rutland wrote:
I guess it's better to drop the 'imx6q-spdif' here?
That depends:
* If the two IP blocks are identical, only the imx35-spdif name is
necessary, and we can
On Mon, Aug 19, 2013 at 09:35:21AM +0100, Nicolin Chen wrote:
This patch implements a device-tree-only CPU DAI driver for Freescale
S/PDIF controller that supports stereo playback and record feature.
Signed-off-by: Nicolin Chen b42...@freescale.com
---
On Mon, Aug 19, 2013 at 09:35:22AM +0100, Nicolin Chen wrote:
This patch implements a device-tree-only machine driver for Freescale
i.MX series Soc. It works with spdif_transmitter/spdif_receiver and
fsl_spdif.c drivers.
Signed-off-by: Nicolin Chen b42...@freescale.com
---
On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
Also I would make this option required. Use a dummy clock for
mux
inputs that are grounded for a
On Mon, Aug 19, 2013 at 10:34:24AM +0100, Nicolin Chen wrote:
Hi Mark,
Thank you for the commenst. I'll Fix them in v8.
Here are some remaining question:
On Mon, Aug 19, 2013 at 10:18:09AM +0100, Mark Rutland wrote:
+Required properties:
+
+ - compatible : Compatible list
On Mon, Aug 19, 2013 at 10:50:43AM +0100, Nicolin Chen wrote:
Hi,
On Mon, Aug 19, 2013 at 10:24:58AM +0100, Mark Rutland wrote:
Is this used semantically, or is it a completely arbitrary string? In
either case I don't see why the compatible string doesn't give the
driver enough to have
On Sat, Aug 17, 2013 at 11:09:36PM +0100, Benjamin Herrenschmidt wrote:
On Sat, 2013-08-17 at 12:50 +0200, Tomasz Figa wrote:
I wonder how would this handle uniprocessor ARM (pre-v7) cores, for
which
the updated bindings[1] define #address-cells = 0 and so no reg
property.
[1] -
On Mon, Aug 19, 2013 at 11:13:04AM +0100, Nicolin Chen wrote:
On Mon, Aug 19, 2013 at 10:54:33AM +0100, Mark Rutland wrote:
I see, so 'Compatible list, must contains fsl,imx35-spdif' would be
okay?
While that needs to be mentioned, other values which might be present
(e.g. fsl,imx6q
On Mon, Aug 19, 2013 at 11:21:06AM +0100, Nicolin Chen wrote:
On Mon, Aug 19, 2013 at 11:01:43AM +0100, Mark Rutland wrote:
At least they are separate drivers as I mentioned in the commit comments.
I'm not sure that the boundary of Linux drivers should necessarily
determine the way we
On Mon, Aug 19, 2013 at 11:52:01AM +0100, Mark Brown wrote:
On Mon, Aug 19, 2013 at 11:01:43AM +0100, Mark Rutland wrote:
On Mon, Aug 19, 2013 at 10:50:43AM +0100, Nicolin Chen wrote:
The phrase user-visible is being used in many current docs, I don't
dare to change it unless a sage
On Mon, Jul 22, 2013 at 01:14:44PM +0100, Gerhard Sittig wrote:
this change implements a clock driver for the MPC512x PowerPC platform
which follows the COMMON_CLK approach and uses common clock drivers
shared with other platforms
this driver implements the publicly announced set of clocks
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