Re: [1/1] powerpc/traps : Updated MC for E6500 L1D cache err

2017-08-28 Thread Matthew Weber
All, On Wed, Jun 28, 2017 at 11:30 AM, Matthew Weber wrote: > Scott, > > On Sun, Apr 30, 2017 at 2:01 AM, Scott Wood wrote: >> On Thu, Apr 27, 2017 at 12:59:40PM -0500, Matt Weber wrote: >>> This patch updates the machine check handler of Linux kernel to >>> h

Re: [1/1] powerpc/traps : Updated MC for E6500 L1D cache err

2017-06-28 Thread Matthew Weber
de (DCWS) register is not implemented but L1 data cache always >> runs in write shadow mode. So, on L1 data cache parity errors, hardware >> will automatically invalidate the data cache but will still log a >> machine check interrupt. >> >> Signed-off-by: Ronak Desai