On Mon, Feb 03, 2014 at 10:17:43AM +, David Laight wrote:
> We achieved about twice that using the PEX dma controller.
> Your 3MB/s for single word transfers is similar to what we saw.
> Cycle times that make an ISA bus look fast.
Indeed, this is a really poor performance. I know we could ac
On Fri, Jan 31, 2014 at 03:18:30PM -0800, David Hawkins wrote:
> 1. Peripheral board DMA (board-to-board)
> 2. Peripheral board DMA to host memory.
> 3. Host (root complex) DMA.
>
> As far as "verification" of your custom peripheral board FPGA IP is
> concerned, if I was a customer, and you had da
Allow for IO memory to be mapped cacheable for performing
PCI read bursts.
Signed-off-by: Michael Moese
---
arch/powerpc/include/asm/io.h | 3 +++
arch/powerpc/mm/pgtable_32.c | 8
2 files changed, 11 insertions(+)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm
