Some opencapi FPGA images allow to control if the FPGA should be reloaded
on the next adapter reset. If it is supported, the image specifies it
through a Vendor Specific DVSEC in the config space of function 0.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2:
- refine ResetReload debug
-off-by: Philippe Bergheaud
---
Documentation/ABI/testing/sysfs-class-ocxl | 10
drivers/misc/ocxl/config.c | 59 +-
drivers/misc/ocxl/ocxl_internal.h | 6 +++
drivers/misc/ocxl/sysfs.c | 35 +
include/misc/ocxl-config.h
On 15/05/2018 07:30, Michael Ellerman wrote:
Philippe Bergheaud writes:
On 14/05/2018 12:51, Michael Ellerman wrote:
Philippe Bergheaud writes:
Skiboot used to set the default Tunnel BAR register value when capi mode
was enabled. This approach was ok for the cxl driver, but prevented
On 14/05/2018 12:51, Michael Ellerman wrote:
Philippe Bergheaud writes:
Skiboot used to set the default Tunnel BAR register value when capi mode
was enabled. This approach was ok for the cxl driver, but prevented other
drivers from choosing different values.
Skiboot versions > 5.11 will
Failure to synchronize the tunneled operations does not prevent
the initialization of the cxl card. This patch reports the tunneled
operations status via /sys.
Signed-off-by: Philippe Bergheaud
---
v3: Added this patch to report the tunneled operations status.
v4: Updated Documentation/ABI
set/reset the Tunnel BAR register when
entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar().
That should work with old skiboot (since we are re-writing the value
already set) and new skiboot.
Signed-off-by: Philippe Bergheaud
Reviewed-by: Christophe Lombard
Acked-by: Frederic Barrat
---
Failure to synchronize the tunneled operations does not prevent
the initialization of the cxl card. This patch reports the tunneled
operations status via /sys.
Signed-off-by: Philippe Bergheaud
---
v3: Added this patch to report the tunneled operations status.
---
drivers/misc/cxl/cxl.h | 1
set/reset the Tunnel BAR register when
entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar().
Signed-off-by: Philippe Bergheaud
Reviewed-by: Christophe Lombard
---
v2: Restrict tunnel bar setting to power9.
Do not fail cxl_configure_adapter() on tunnel bar setting error.
Log an i
set/reset the Tunnel BAR register when
entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar().
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: Restrict tunnel bar setting to power9.
Do not fail cxl_configure_adapter() on tunnel bar setting error.
Log an info message instead,
set/reset the Tunnel BAR register when
entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar().
Signed-off-by: Philippe Bergheaud
---
drivers/misc/cxl/pci.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 83f1d08058fc..3beff9188
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
Reviewed-by: Frederic Barrat
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications".
v3: No chang
be woken up.
Signed-off-by: Philippe Bergheaud
Reviewed-by: Frederic Barrat
---
Changelog:
v2: Do not set the ASN indication. Get it from the device tree.
v3: Make pnv_pci_get_phb_node() available when compiling without cxl.
v4: Add pnv_pci_get_as_notify_info().
Rebase opal call numbers on
be woken up.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: Do not set the ASN indication. Get it from the device tree.
v3: Make pnv_pci_get_phb_node() available when compiling without cxl.
v4: Add pnv_pci_get_as_notify_info().
Rebase opal call numbers on skiboot 5.9.6.
v5
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications".
v3: No change.
v4: No functional change
Tunnel BAR Response address used by driver.
This function uses two new OPAL calls, as the PBCQ Tunnel BAR
register is configured by skiboot.
pnv_pci_get_as_notify_info()
Return the ASN info of the thread to be woken up.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: Do not set the
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications".
v3: No change.
v4: No functional change
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications".
v3: No change.
v4: No functional change
Tunnel BAR Response address used by driver.
This function uses two new OPAL calls, as the PBCQ Tunnel BAR
register is configured by skiboot.
pnv_pci_get_as_notify_info()
Return the ASN info of the thread to be woken up.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: Do not set the
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications".
v3: No change.
v4: No functional change
Tunnel BAR Response address used by driver.
This function uses two new OPAL calls, as the PBCQ Tunnel BAR
register is configured by skiboot.
pnv_pci_get_as_notify_info()
Return the ASN info of the thread to be woken up.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: Do not set the
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications".
v3: No change.
v4: No functional change
Tunnel BAR Response address used by driver.
This function uses two new OPAL calls, as the PBCQ Tunnel BAR
register is configured by skiboot.
pnv_pci_get_as_notify_info()
Return the ASN info of the thread to be woken up.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: Do not set the
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications".
v3: No change.
v4: No functional change
Tunnel BAR Response address used by driver.
This function uses two new OPAL calls, as the PBCQ Tunnel BAR
register is configured by skiboot.
void pnv_pci_get_as_notify_info()
Return the ASN info of the thread to be woken up.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: Do not set
ned-off-by: Christophe Lombard
Reviewed-by: Philippe Bergheaud
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications".
v3: No change.
This patch depends on the
Tunnel BAR Response address used by driver.
The latter uses two new OPAL calls, as the PBCQ Tunnel BAR register
is configured by skiboot.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: Do not set the ASN indication. Get it from the device tree.
v3: Make pnv_pci_get_phb_node() available
Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: New patch. Use the new device tree property "ibm,phb-indications".
This patch depends on the followi
Tunnel BAR Response address used by driver.
The latter uses two new OPAL calls, as the PBCQ Tunnel BAR register
is configured by skiboot.
Signed-off-by: Philippe Bergheaud
---
Changelog:
v2: Do not set the ASN indication. Get it from the device tree.
This patch depends on the following skiboot
Tunnel BAR address mask used
by driver.
These functions use four new OPAL calls, as PBCQ and PHB configurations
are done by skiboot.
Signed-off-by: Philippe Bergheaud
---
This patch depends on the following skiboot prerequisites:
https://patchwork.ozlabs.org/patch/829294/
[1/2] phb4: set PHB
On 31/08/2017 20:06, Sukadev Bhattiprolu wrote:
felix [fe...@linux.vnet.ibm.com] wrote:
On 31/08/2017 01:32, Sukadev Bhattiprolu wrote:
Michael Neuling [mi...@neuling.org] wrote:
Suka,
Please CC Christophe who as an alternative way of doing this. We ned to get
agreement across all users of TI
patch also changes the size of the field data_size, and
makes it constant, to support 32-bit userland applications
running on big-endian ppc64 kernels transparently.
This breaks the (young) API that has been merged in v4.8.
Signed-off-by: Philippe Bergheaud
---
Changes since v1:
Added an
makes the definition of cxl_event_afu_driver_reserved
more consistent with the other definitions in the header file.
Signed-off-by: Philippe Bergheaud
---
include/uapi/misc/cxl.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/uapi/misc/cxl.h b/include/uapi/misc
implementation errors.
Signed-off-by: Philippe Bergheaud
---
Changes since v1:
- Rebased on Ian's patch
"cxl: Abstract the differences between the PSL and XSL"
Changes since v2:
- Added description
drivers/misc/cxl/cxl.h| 15 +++
drivers/misc/cx
Signed-off-by: Philippe Bergheaud
---
Changes since v1:
- Rebased on Ian's patch
"cxl: Abstract the differences between the PSL and XSL"
drivers/misc/cxl/cxl.h| 15 +++
drivers/misc/cxl/guest.c | 9 ++---
drivers/misc/cx
One should not attempt to switch a PHB into CAPI mode if there is
a switch between the PHB and the adapter. This patch modifies the
cxl driver to ignore CAPI adapters misplaced in switched slots.
Signed-off-by: Philippe Bergheaud
---
This patch fixes Bz 142217.
Changes since v1:
- As
One should not attempt to switch a PHB into CAPI mode if there is
a switch between the PHB and the adapter. This patch modifies the
cxl driver to ignore CAPI adapters misplaced in switched slots.
Signed-off-by: Philippe Bergheaud
---
This patch fixes Bz 142217.
drivers/misc/cxl/pci.c | 29
Michael Ellerman wrote:
On Fri, 2016-24-06 at 06:47:07 UTC, Philippe Bergheaud wrote:
From: Michael Neuling
This provides AFU drivers a means to associate private data with a cxl
context. This is particularly intended for make the new callbacks for
driver specific events easier for AFU
.
Signed-off-by: Michael Neuling
Signed-off-by: Ian Munsie
Signed-off-by: Philippe Bergheaud
---
No changes since v1. Added Matt Ochs reviewed-by tag.
drivers/misc/cxl/api.c | 21 +
drivers/misc/cxl/cxl.h | 3 +++
include/misc/cxl.h | 7 +++
3 files changed, 31 insertions
.
Signed-off-by: Michael Neuling
Signed-off-by: Ian Munsie
Signed-off-by: Philippe Bergheaud
---
No changes since v1. Added Matt Ochs reviewed-by tag.
drivers/misc/cxl/api.c | 21 +
drivers/misc/cxl/cxl.h | 3 +++
include/misc/cxl.h | 7 +++
3 files changed, 31 insertions
ovide their own means for userspace to obtain the
AFU file descriptor (i.e. cxlflash uses an ioctl on their scsi file
descriptor to obtain the AFU file descriptor) and the generic cxl driver
will never use this event, the ABI of the event is up to each individual
AFU driver.
Signed-off-by: Phi
Should also check against the length of user-buffer (count) provided in the read
call.Ideally this condition check should be moved to the read call where
you have access to the count variable.
Right now libcxl is using a harcoded value of CXL_READ_MIN_SIZE to
issue the read call and in kernel cod
Matthew R. Ochs wrote:
On Jun 21, 2016, at 5:34 AM, Vaibhav Jain wrote:
Hi Ian,
Ian Munsie writes:
Excerpts from Vaibhav Jain's message of 2016-06-20 14:20:16 +0530:
What exactly is the use case for this API? I'd vote to drop it if we can
do without it.
Agree with this. Functionality of
.
Signed-off-by: Michael Neuling
Signed-off-by: Ian Munsie
Signed-off-by: Philippe Bergheaud
---
No changes since v1. Added Matt Ochs reviewed-by tag.
drivers/misc/cxl/api.c | 21 +
drivers/misc/cxl/cxl.h | 3 +++
include/misc/cxl.h | 7 +++
3 files changed, 31 insertions
s for userspace to obtain the
AFU file descriptor (i.e. cxlflash uses an ioctl on their scsi file
descriptor to obtain the AFU file descriptor) and the generic cxl driver
will never use this event, the ABI of the event is up to each individual
AFU driver.
Signed-off-by: Philippe Bergheaud
---
Ch
Michael Ellerman wrote:
On Mon, 2016-23-05 at 12:49:01 UTC, Philippe Bergheaud wrote:
This adds an afu_driver_ops structure with deliver_event() and
event_delivered() callbacks. An AFU driver such as cxlflash can fill
this out and associate it with a context to enable passing custom
AFU
.
Signed-off-by: Michael Neuling
Signed-off-by: Ian Munsie
Signed-off-by: Philippe Bergheaud
---
No changes since v1, added Matt Ochs reviewed-by tag.
drivers/misc/cxl/api.c | 21 +
drivers/misc/cxl/cxl.h | 3 +++
include/misc/cxl.h | 7 +++
3 files changed, 31 insertions
.
Signed-off-by: Michael Neuling
Signed-off-by: Ian Munsie
Signed-off-by: Philippe Bergheaud
---
No changes since v1, added Matt Ochs reviewed-by tag.
drivers/misc/cxl/api.c | 21 +
drivers/misc/cxl/cxl.h | 3 +++
include/misc/cxl.h | 7 +++
3 files changed, 31 insertions
means for userspace to obtain the
AFU file descriptor (i.e. cxlflash uses an ioctl on their scsi file
descriptor to obtain the AFU file descriptor) and the generic cxl driver
will never use this event, the ABI of the event is up to each individual
AFU driver.
Signed-off-by: Philippe Berg
will never use this event, the ABI of the event is up to each individual
AFU driver.
Signed-off-by: Philippe Bergheaud
---
Changes since v3:
- Removed driver ops callback ctx_event_pending
- Created cxl function cxl_context_pending_events
- Created cxl function cxl_unset_driver_ops
- Added at
will never use this event, the ABI of the event is up to each individual
AFU driver.
Signed-off-by: Philippe Bergheaud
---
Changes since v3:
- Removed driver ops callback ctx_event_pending
- Created cxl function cxl_context_pending_events
- Created cxl function cxl_unset_driver_ops
- Added at
.
Signed-off-by: Michael Neuling
Signed-off-by: Ian Munsie
Signed-off-by: Philippe Bergheaud
---
No changes since v1, added Matt Ochs reviewed-by tag.
drivers/misc/cxl/api.c | 21 +
drivers/misc/cxl/cxl.h | 3 +++
include/misc/cxl.h | 7 +++
3 files changed, 31 insertions
Signed-off-by: Philippe Bergheaud
---
drivers/misc/cxl/cxl.h| 15 +++
drivers/misc/cxl/guest.c | 11 ---
drivers/misc/cxl/irq.c| 27 +++
drivers/misc/cxl/native.c | 27 ++-
4 files changed, 68 insertions(+), 12
The POWER8NVL chip has two CAPI ports. Configure the PSL to route
data to the port corresponding to the CAPP unit.
Signed-off-by: Philippe Bergheaud
---
V2:
- Complete rewrite after Mikey's review
V3:
Fixes suggested by Michael:
- s/capp_unit_id(/get_capp_unit_id(/
- Fix
Signed-off-by: Philippe Bergheaud
---
V2:
- New patch, added to patch set
V3:
- no change
arch/powerpc/include/asm/reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index f5f4c66..cf09c6e 100644
--- a/arch/powerpc
Sorry, I've sent this to the wrong list.
Philippe
Philippe Bergheaud wrote:
From: Vaibhav Jain
Adds a 5ms wait to phb3_msi_set_xive after the interrupt is masked so
that the kernel delays cleanup until an irq if its in-flight is
handled. The value 5ms is the worst case time needed by a
From: Vaibhav Jain
Adds a 5ms wait to phb3_msi_set_xive after the interrupt is masked so
that the kernel delays cleanup until an irq if its in-flight is
handled. The value 5ms is the worst case time needed by an irq to be
presented to the host after its generated.
Signed-off-by: Vaibhav Jain
--
Signed-off-by: Philippe Bergheaud
---
V2:
- New patch, added to patch set
arch/powerpc/include/asm/reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c4cb2ff..6a6de4a 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b
The POWER8NVL chip has two CAPI ports. Configure the PSL to route
data to the port corresponding to the CAPP unit.
Signed-off-by: Philippe Bergheaud
---
V2:
- Complete rewrite after Mikey's review
drivers/misc/cxl/pci.c | 31 ++-
1 file changed, 30 inser
Michael Neuling wrote:
On Tue, 2016-03-15 at 15:26 +0100, Philippe Bergheaud wrote:
Naples CPUs have two CAPI ports.
Naples is an internal name, don't use that. Use POWER8NVL is the name
we use in the kernel.
alsi, it's a "chip" that has two CAPI ports, not the CPU.
Naples CPUs have two CAPI ports. Configure the PSL to route data to
the port corresponding to the PHB index.
Signed-off-by: Philippe Bergheaud
---
drivers/misc/cxl/pci.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc
This patch configures the PSL Timebase function and enables it,
after the CAPP has been initialized by OPAL.
Acked-by: Ian Munsie
Signed-off-by: Philippe Bergheaud
---
drivers/misc/cxl/cxl.h | 5 +
drivers/misc/cxl/pci.c | 57 +-
2 files
Philippe Bergheaud wrote:
This patch configures the PSL Timebase function and enables it,
after the CAPP has been initialized by OPAL.
V2:
- Clear CXL_PSL_ErrIVTE_tberror bit
- Define the sync count unit
- Wait 1ms before each test
- Use negative error code
- Do not ignore errors
- Except
supported by OPAL
- Be silent on success
Signed-off-by: Philippe Bergheaud
---
drivers/misc/cxl/cxl.h |5
drivers/misc/cxl/pci.c | 57 +++-
2 files changed, 61 insertions(+), 1 deletions(-)
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl
Michael Neuling wrote:
> Please use negative error codes here. -EIO?
> And check it here.
Mikey,
I am reluctant to fail the entire CAPI init after a PSL timebase sync failure.
If we ignore the error, the CAPI device stays available (without timebase sync).
If we honour the error, the CAPI devic
Michael Neuling wrote:
On Mon, 2015-06-01 at 09:37 +0200, Philippe Bergheaud wrote:
Michael Neuling wrote:
On Thu, 2015-05-28 at 15:12 +0200, Philippe Bergheaud wrote:
This patch configures the PSL Timebase function and enables it,
after the CAPP has been initialized by OPAL. Failures are
Michael Neuling wrote:
On Thu, 2015-05-28 at 15:12 +0200, Philippe Bergheaud wrote:
This patch configures the PSL Timebase function and enables it,
after the CAPP has been initialized by OPAL. Failures are reported
and ignored.
Needs an Signed-off-by.
Yes.
Comments inline.
---
drivers
This patch configures the PSL Timebase function and enables it,
after the CAPP has been initialized by OPAL. Failures are reported
and ignored.
---
drivers/misc/cxl/cxl.h |5 +
drivers/misc/cxl/pci.c | 35 +++
2 files changed, 40 insertions(+), 0 deletions
Fix the attribute name of the configuration record class ID.
Signed-off-by: Philippe Bergheaud
---
Documentation/ABI/testing/sysfs-class-cxl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-class-cxl
b/Documentation/ABI/testing/sysfs-class
From: Philippe Bergheaud
This fixes two typos and explains where shared attributes are stored.
Signed-off-by: Philippe Bergheaud
Acked-by: Michael Neuling
---
Documentation/ABI/testing/sysfs-class-cxl | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
diff --git a
Denis Kirjanov wrote:
Any feedback from PPC folks?
I have reviewed the patch and it looks fine to me.
I have tested successfuly on ppc64le.
I could not test it on ppc64.
Philippe
On 10/26/14, Denis Kirjanov wrote:
Cc: Matt Evans
Signed-off-by: Denis Kirjanov
---
arch/powerpc/include/asm
Anton Blanchard wrote:
Unaligned stores take alignment exceptions on POWER7 running in little-endian.
This is a dumb little-endian base memcpy that prevents unaligned stores.
Once booted the feature fixup code switches over to the VMX copy loops
(which are already endian safe).
The question is w
Rusty Russell wrote:
Philippe Bergheaud writes:
Anton Blanchard wrote:
Here are the ABIv2 patches rebased against 3.15-rc2.
After recompiling 3.15-rc2 with the ABIv2 patches,
I see the following line in Modules.symvers:
0x TOC. vmlinux EXPORT_SYMBOL
Kernel will not load
Anton Blanchard wrote:
Here are the ABIv2 patches rebased against 3.15-rc2.
After recompiling 3.15-rc2 with the ABIv2 patches,
I see the following line in Modules.symvers:
0x TOC. vmlinux EXPORT_SYMBOL
Kernel will not load modules because TOC. has no CRC.
Is this expected ? Should
Anton Blanchard wrote:
diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S
index 72ad055..01da956 100644
--- a/arch/powerpc/lib/memcpy_64.S
+++ b/arch/powerpc/lib/memcpy_64.S
@@ -12,7 +12,7 @@
.align 7
_GLOBAL(memcpy)
BEGIN_FTR_SECTION
- std r3,48(r1)
Michael Ellerman wrote:
On Wed, 2013-12-11 at 11:30 +0100, Philippe Bergheaud wrote:
Benjamin Herrenschmidt wrote:
On Wed, 2013-12-11 at 17:29 +1100, Michael Ellerman wrote:
It would be nice if you could make an assertion about what the state of HMT
handling should be once your patch is
Benjamin Herrenschmidt wrote:
On Wed, 2013-12-11 at 17:29 +1100, Michael Ellerman wrote:
It would be nice if you could make an assertion about what the state of HMT
handling should be once your patch is applied.
I think it's:
* The kernel should use HMT_MEDIUM_LOW as it's "default" priority
manage SMT priority for spinning and active (in the critical region) threads.
Libpthread must be able to raise and lower the the SMT priority versus the
default to be effective.
This lowers the default kernel thread priority from medium to medium-low.
Signed-off-by: Philippe Bergheaud
---
arch
Benjamin Herrenschmidt wrote:
On Wed, 2013-12-04 at 14:45 +0100, Philippe Bergheaud wrote:
+#ifdef __LITTLE_ENDIAN__
+#define GETWORD(v) (((v)[3] << 24) + ((v)[2] << 16) + ((v)[1] << 8) +
(v)[0])
+#else
#define GETWORD(v) (((v)[0] << 24) + ((v)[1] <<
Tom Musta wrote:
On 12/2/2013 3:10 AM, Philippe Bergheaud wrote:
This patch fixes the disassembler of the powerpc kernel debugger xmon,
for little-endian.
Signed-off-by: Philippe Bergheaud
---
arch/powerpc/xmon/xmon.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc
This patch fixes the disassembler of the powerpc kernel debugger xmon,
for little-endian.
Signed-off-by: Philippe Bergheaud
---
arch/powerpc/xmon/xmon.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index af9d346..6c27804 100644
uld be bad for
all other 64bit platforms.
Signed-off-by: Philippe Bergheaud
---
arch/powerpc/include/asm/string.h |4
arch/powerpc/kernel/ppc_ksyms.c |2 --
arch/powerpc/lib/Makefile |2 --
arch/powerpc/lib/memcpy_64.S | 19 +++
4 files changed, 19
Michael Neuling wrote:
Philippe Bergheaud wrote:
Unaligned stores take alignment exceptions on POWER7 running in little-endian.
This is a dumb little-endian base memcpy that prevents unaligned stores.
It is replaced by the VMX memcpy at boot.
Is this any faster than the generic version
Unaligned stores take alignment exceptions on POWER7 running in little-endian.
This is a dumb little-endian base memcpy that prevents unaligned stores.
It is replaced by the VMX memcpy at boot.
Signed-off-by: Philippe Bergheaud
---
arch/powerpc/include/asm/string.h |4
arch/powerpc
This is an optimization for the PowerPC in 64-bit
little-endian. Bit counting is used in find_zero(), instead
of the multiply and shift.
It is modelled after Alan Modra's PowerPC LE strlen patch
http://sourceware.org/ml/libc-alpha/2013-08/msg00097.html.
Signed-off-by: Philippe Berg
This enables the Berkeley Packet Filter JIT compiler
for the PowerPC running in 64bit Little Endian.
Signed-off-by: Philippe Bergheaud
---
arch/powerpc/include/asm/ppc-opcode.h |1 +
arch/powerpc/net/bpf_jit.h| 10 ++
arch/powerpc/net/bpf_jit_64.S |9
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