[I used the wrong branch, this will hopefully not conflict]
This is hopfully the last iteration of the series.
Rex Scott, please test and signoff.
Changes since last version:
- Added mandatory pinning of iTLB
- Added DTLB Miss cleanup
Joakim Tjernlund (10):
8xx: invalidate non present TLBs
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff
when a page has been made dirty.
- Proper RO/RW mapping of user space.
- Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?)
- kernel RO/user NA support.
Cons:
- A few more instructions in the TLB Miss routines.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
Test for DAR=0x00f0 in DataTLBError and bail
to handle_page_fault().
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 147
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE?
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/misc_32.S | 18 --
arch/powerpc/lib/copy_32.S| 24
2
There is no need to do set the DIRTY bit directly in DTLB Error.
Trap to do_page_fault() and let the generic MM code do the work.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 96
1 files changed, 0
Use symbolic constant for PRESENT and avoid branching.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 17 +++--
1 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff
This is hopfully the last iteration of the series.
Rex Scott, please test and signoff.
Changes since last version:
- Added mandatory pinning of iTLB
- Added DTLB Miss cleanup
Joakim Tjernlund (10):
8xx: invalidate non present TLBs
8xx: Update TLB asm so it behaves as linux mm expects
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
Test for DAR=0x00f0 in DataTLBError and bail
to handle_page_fault().
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
when a page has been made dirty.
- Proper RO/RW mapping of user space.
- Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?)
- kernel RO/user NA support.
Cons:
- A few more instructions in the TLB Miss routines.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git
Use symbolic constant for PRESENT and avoid branching.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 17 +++--
1 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE?
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 147
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/misc_32.S | 18 --
arch/powerpc/lib/copy_32.S| 24
2
There is no need to do set the DIRTY bit directly in DTLB Error.
Trap to do_page_fault() and let the generic MM code do the work.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 96
1 files changed, 0
Scott Wood scottw...@freescale.com wrote on 13/11/2009 20:25:48:
Joakim Tjernlund wrote:
Anyhow, lets start simple and just do the pinned ITLB so the
new TLB code can be applied. Can you confirm this works for you?
It works (after changing #ifdef 1 to #if 1).
OK, new series sent.
BTW
Dan Malek d...@embeddedalley.com wrote on 14/11/2009 19:08:43:
On Nov 14, 2009, at 2:42 AM, Joakim Tjernlund wrote:
. Avoid this by always pinning
kernel instruction TLB space.
You may as well map the data space, too, since you have
reserved the entries. Take advantage
Scott Wood scottw...@freescale.com wrote on 11/11/2009 16:26:53:
On Wed, Nov 11, 2009 at 01:06:10AM +0100, Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 11/11/2009 00:21:18:
Where would you put the dcbi? How do you regain control after that
cache line has been
Scott Wood scottw...@freescale.com wrote on 12/11/2009 20:45:59:
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 11/11/2009 16:26:53:
On Wed, Nov 11, 2009 at 01:06:10AM +0100, Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 11/11/2009 00:21:18
Scott Wood scottw...@freescale.com wrote on 12/11/2009 22:57:59:
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 12/11/2009 20:45:59:
One other concern with pinning on 8xx -- could it cause problems with
uncached DMA mappings? What happens if a speculative load pulls
Scott Wood scottw...@freescale.com wrote on 10/11/2009 00:00:04:
On Mon, Nov 09, 2009 at 03:53:21PM -0600, Scott Wood wrote:
On Fri, Nov 06, 2009 at 10:29:44AM +0100, Joakim Tjernlund wrote:
With this, the kernel hangs after Mount-cache hash table entries:
512.
Somewhat
JFFS2 uses lesser compression ratio and inflate always
ends up in copy direct from output case.
This patch tries to optimize the direct copy procedure.
Uses get_unaligned() but only in one place.
The copy loop just above this one can also use this
optimization, but I havn't done so as I have not
Scott Wood scottw...@freescale.com wrote on 10/11/2009 22:36:32:
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 10/11/2009 21:27:05:
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 10/11/2009 17:55:28:
Except that the invalidation only happens
Scott Wood scottw...@freescale.com wrote on 10/11/2009 21:27:05:
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 10/11/2009 17:55:28:
Except that the invalidation only happens when you take an ITLB miss on
an adjacent page, which means we'd likely never get CPU15
Scott Wood scottw...@freescale.com wrote on 10/11/2009 21:00:07:
Joakim Tjernlund wrote:
I think I have misunderstood, its is not CPU15 or 8xx problem per se, it
is a general problem that could happen to any ppc CPU, right?
8xx just happen to be the first CPU that hits this case due to my
Scott Wood scottw...@freescale.com wrote on 10/11/2009 00:00:04:
On Mon, Nov 09, 2009 at 03:53:21PM -0600, Scott Wood wrote:
On Fri, Nov 06, 2009 at 10:29:44AM +0100, Joakim Tjernlund wrote:
With this, the kernel hangs after Mount-cache hash table entries:
512.
Somewhat
Scott Wood scottw...@freescale.com wrote on 10/11/2009 17:55:28:
Scott Wood wrote:
Joakim Tjernlund wrote:
Why does not pinning interact well with CPU15? If pinned, you never get
a TLB miss for kernel text so that should mitigate the CPU15 problem.
The nature of the workaround
Scott Wood scottw...@freescale.com wrote on 10/11/2009 23:02:10:
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 10/11/2009 22:36:32:
Joakim Tjernlund wrote:
yes, maybe there is a way around that. Perhaps by using one of the
pinned entries for loaded modules, i.e
Scott Wood scottw...@freescale.com wrote on 11/11/2009 00:21:18:
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 10/11/2009 23:02:10:
Joakim Tjernlund wrote:
It wasn't the CPU15 workaround that I was worried about taking down the
pinning -- but rather the CPU15 bug
Scott Wood scottw...@freescale.com wrote on 06/11/2009 01:33:05:
On Wed, Nov 04, 2009 at 02:38:32PM +0100, Joakim Tjernlund wrote:
Here is the latest(last?) round of this series. I
hope I got everything right now.
Scott and Rex, please test and send ACK/NACK.
Jocke
Joakim
Scott Wood scottw...@freescale.com wrote on 06/11/2009 01:33:05:
On Wed, Nov 04, 2009 at 02:38:32PM +0100, Joakim Tjernlund wrote:
Here is the latest(last?) round of this series. I
hope I got everything right now.
Scott and Rex, please test and send ACK/NACK.
Jocke
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git
Here is the latest(last?) round of this series. I
hope I got everything right now.
Scott and Rex, please test and send ACK/NACK.
Jocke
Joakim Tjernlund (8):
8xx: invalidate non present TLBs
8xx: Update TLB asm so it behaves as linux mm expects.
8xx: Tag DAR with 0x00f0 to catch buggy
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff
when a page has been made dirty.
- Proper RO/RW mapping of user space.
- Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?)
- kernel RO/user NA support.
Cons:
- A few more instructions in the TLB Miss routines.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 147
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
Test for DAR=0x00f0 in DataTLBError and bail
to handle_page_fault().
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/misc_32.S | 18 --
arch/powerpc/lib/copy_32.S| 24
2
There is no need to do set the DIRTY bit directly in DTLB Error.
Trap to do_page_fault() and let the generic MM code do the work.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/kernel/head_8xx.S | 96
1 files changed, 0
Scott Wood scottw...@freescale.com wrote on 30/10/2009 18:37:49:
On Fri, Oct 30, 2009 at 12:16:07PM -0500, Scott Wood wrote:
On Sat, Oct 17, 2009 at 02:01:38PM +0200, Joakim Tjernlund wrote:
+ mfspr r10, SPRN_SRR0
DO_8xx_CPU6(0x3780, r3)
mtspr SPRN_MD_EPN, r10
Scott Wood scottw...@freescale.com wrote on 03/11/2009 17:59:30:
Joakim Tjernlund wrote:
and things seem to work. You could probably replace the rlwinm by
subtracting PAGE_OFFSET from swapper_pg_dir instead.
Just guessing here, do you mean:
lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
Scott Wood scottw...@freescale.com wrote on 30/10/2009 18:37:49:
On Fri, Oct 30, 2009 at 12:16:07PM -0500, Scott Wood wrote:
On Sat, Oct 17, 2009 at 02:01:38PM +0200, Joakim Tjernlund wrote:
+ mfspr r10, SPRN_SRR0
DO_8xx_CPU6(0x3780, r3)
mtspr SPRN_MD_EPN, r10
On Friday 30 October 2009 16:08:55 Alessandro Rubini wrote:
asm(eieio; sync);
Hmm...
: : : memory
And, doesn't ; start a comment in assembly? (no, not on powerpc
it seems)
Yes, I think the barrier is wrong.
Please try with
#define mb() __asm__
Michael Buesch m...@bu3sch.de wrote on 31/10/2009 17:42:54:
On Saturday 31 October 2009 14:26:48 Joakim Tjernlund wrote:
On Friday 30 October 2009 16:08:55 Alessandro Rubini wrote:
asm(eieio; sync);
Hmm...
: : : memory
And, doesn't ; start a comment
Michael Buesch m...@bu3sch.de wrote on 31/10/2009 21:35:31:
On Saturday 31 October 2009 21:14:07 Joakim Tjernlund wrote:
Michael Buesch m...@bu3sch.de wrote on 31/10/2009 17:42:54:
On Saturday 31 October 2009 14:26:48 Joakim Tjernlund wrote:
On Friday 30 October 2009 16:08:55
On Tue, Oct 27, 2009 at 04:24:53PM -0600, Jonathan Haws wrote:
How can I get that pointer? Unfortunately I cannot simply
use
the
address of the flash. Is there some magical function call
that
gives me access to that portion of the memory space?
$ man 2
On Tue, Oct 27, 2009 at 04:24:53PM -0600, Jonathan Haws wrote:
How can I get that pointer? Unfortunately I cannot simply
use
the
address of the flash. Is there some magical function call
that
gives me access to that portion of the memory space?
Scott Wood scottw...@freescale.com wrote on 30/10/2009 01:12:28:
On Sat, Oct 17, 2009 at 02:01:38PM +0200, Joakim Tjernlund wrote:
Joakim Tjernlund/Transmode wrote on 17/10/2009 13:24:18:
Rex Feany rfe...@mrv.com wrote on 16/10/2009 22:25:41:
Thus spake Joakim Tjernlund
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 27/10/2009 01:00:53:
On Mon, 2009-10-26 at 16:26 -0700, Dan Malek wrote:
Just be careful the get_user() doesn't regenerate the same
translation error you are trying to fix by being here..
yes, I had some problems with this
Scott Wood scottw...@freescale.com wrote on 27/10/2009 16:58:41:
On Tue, Oct 27, 2009 at 10:16:17AM +0100, Joakim Tjernlund wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 27/10/2009
01:00:53:
On Mon, 2009-10-26 at 16:26 -0700, Dan Malek wrote:
Just be careful
Wolfgang Denk w...@denx.de wrote on 17/10/2009 21:34:54:
Dear Joakim Tjernlund,
In message OFEC00B9FB.B03AA854-ONC1257652.00644350-C1257652.
00651...@transmode.se you wrote:
Recompile and relink it with soft-fp as well. Or ask the provider to
do that.
That is what I am trying do
Rex Feany rfe...@mrv.com wrote on 16/10/2009 22:25:41:
Thus spake Joakim Tjernlund (joakim.tjernl...@transmode.se):
Right, it is the pte table walk that is blowing up.
I just noted that 2.6 lacks a tophys() call in its table walk
so I removed that one(there is one more tophys call but I
Joakim Tjernlund/Transmode wrote on 17/10/2009 13:24:18:
Rex Feany rfe...@mrv.com wrote on 16/10/2009 22:25:41:
Thus spake Joakim Tjernlund (joakim.tjernl...@transmode.se):
Right, it is the pte table walk that is blowing up.
I just noted that 2.6 lacks a tophys() call in its table
Anyone tried mixing hard and soft FP in on soft float CPU such as 83xx?
Been trying to figure out if this is a good idea or not.
Any combinations that will or won't work?
Generally I got soft FP in all system libs but there might be
an binary application which will use hard FP.
Is the MATH_EMU
Wolfgang Denk w...@denx.de wrote on 17/10/2009 20:12:24:
Dear Joakim Tjernlund,
In message OFC920E57F.DFABC29F-ONC1257652.00421E11-C1257652.
00434...@transmode.se you wrote:
Anyone tried mixing hard and soft FP in on soft float CPU such as 83xx?
Hm... most 83xx have a FPU.
Yeah, I
Rex Feany rfe...@mrv.com wrote on 15/10/2009 18:56:50:
arch/powerpc/kernel/head_8xx.o: In function `FixupDAR':
/home/rfeany/src/lnxnm/linux-dev/arch/powerpc/kernel/head_8xx.S:576: undefined
reference to `DARfix'
With all of your patches applied I have this problem:
open(/proc/mounts,
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
---
arch/powerpc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index
Now updated with Scott's remarks.
There is still(probably) a trivial conflict in pte-8xx.h
Joakim Tjernlund (8):
8xx: invalidate non present TLBs
8xx: Update TLB asm so it behaves as linux mm expects.
8xx: Tag DAR with 0x00f0 to catch buggy instructions.
8xx: Fixup DAR from buggy dcbX
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
---
arch/powerpc/kernel/head_8xx.S | 180 +++-
1 files changed, 176
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
Test for DAR=0x00f0 in DataTLBError and bail
to handle_page_fault().
---
arch/powerpc/kernel/head_8xx.S | 15 ++-
1 files
Update the TLB asm to make proper use of _PAGE_DIRY and _PAGE_ACCESSED.
Get rid of _PAGE_HWWRITE too.
Pros:
- I/D TLB Miss never needs to write to the linux pte.
- _PAGE_ACCESSED is only set on TLB Error fixing accounting
- _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
---
arch/powerpc/kernel/misc_32.S | 18 --
arch/powerpc/lib/copy_32.S| 24
2 files changed, 0 insertions(+), 42 deletions(-)
diff --git
There is no need to do set the DIRTY bit directly in DTLB Error.
Trap to do_page_fault() and let the generic MM code do the work.
---
arch/powerpc/kernel/head_8xx.S | 96
1 files changed, 0 insertions(+), 96 deletions(-)
diff --git
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
---
arch/powerpc/kernel/head_8xx.S | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE?
---
arch/powerpc/include/asm/pte-8xx.h |5 +++--
Scott Wood scottw...@freescale.com wrote on 14/10/2009 19:23:51:
On Sun, Oct 11, 2009 at 06:35:04PM +0200, Joakim Tjernlund wrote:
This is the latest batch of mu 8xx MMU/TLB rework.
I think this is complete now and will relax with
other work the next few days. I hope I can get some
Scott Wood scottw...@freescale.com wrote on 14/10/2009 19:20:03:
On Sun, Oct 11, 2009 at 06:35:08PM +0200, Joakim Tjernlund wrote:
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump
Scott Wood scottw...@freescale.com wrote on 14/10/2009 21:23:02:
Joakim Tjernlund wrote:
BTW, you could add a test and printk in do_page_fault on address 0x00f0.
if that ever hits there is a problem with dcbX fixup.
It doesn't get any 0xf0 faults.
FWIW, I'm not seeing the segfault any
Scott Wood scottw...@freescale.com wrote on 14/10/2009 22:22:25:
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 14/10/2009 21:23:02:
Joakim Tjernlund wrote:
BTW, you could add a test and printk in do_page_fault on address
0x00f0.
if that ever hits
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 14/10/2009 23:17:09:
On Wed, 2009-10-14 at 16:14 -0500, Scott Wood wrote:
I think the last working version was a little older than that -- and it's
quite
possible that there was underlying badness even earlier that just recently
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 14/10/2009 23:52:10:
On Wed, 2009-10-14 at 23:41 +0200, Joakim Tjernlund wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 14/10/2009
23:17:09:
On Wed, 2009-10-14 at 16:14 -0500, Scott Wood wrote:
I think
Rex Feany rfe...@mrv.com wrote on 15/10/2009 03:08:55:
Thus spake Benjamin Herrenschmidt (b...@kernel.crashing.org):
On Wed, 2009-10-14 at 17:41 -0700, Rex Feany wrote:
The biggest problem for me turned out to be the MMU context IDs being
clamped to 32 when the 8xx only has 16. With
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 15/10/2009 03:12:50:
On Wed, 2009-10-14 at 18:08 -0700, Rex Feany wrote:
Thus spake Benjamin Herrenschmidt (b...@kernel.crashing.org):
On Wed, 2009-10-14 at 17:41 -0700, Rex Feany wrote:
The biggest problem for me turned out to
There is no need to do set the DIRTY bit directly in DTLB Error.
Trap to do_page_fault() and let the generic MM code do the work.
---
Ben, here it is :)
arch/powerpc/kernel/head_8xx.S | 95
1 files changed, 0 insertions(+), 95 deletions(-)
diff --git
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 12/10/2009 07:46:14:
On Mon, 2009-10-12 at 07:36 +0200, Joakim Tjernlund wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 12/10/2009
00:44:56:
On Mon, 2009-10-12 at 00:19 +0200, Joakim Tjernlund wrote:
I hear
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
---
arch/powerpc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index
This is the latest batch of mu 8xx MMU/TLB rework.
I think this is complete now and will relax with
other work the next few days. I hope I can get some
testing from Scott and Rex during this time.
Joakim Tjernlund (8):
8xx: invalidate non present TLBs
8xx: Update TLB asm so it behaves
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
Test for DAR=0x00f0 in DataTLBError and bail
to handle_page_fault().
---
arch/powerpc/kernel/head_8xx.S | 15 ++-
1 files
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
---
arch/powerpc/kernel/head_8xx.S | 146 +++-
1 files changed, 145
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE?
---
arch/powerpc/include/asm/pte-8xx.h |5 +++--
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
---
arch/powerpc/kernel/misc_32.S | 18 --
arch/powerpc/lib/copy_32.S| 24
2 files changed, 0 insertions(+), 42 deletions(-)
diff --git
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
---
arch/powerpc/kernel/head_8xx.S | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 11/10/2009 23:25:30:
On Sun, 2009-10-11 at 18:35 +0200, Joakim Tjernlund wrote:
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
Easier fix: Stop doing thing in DTLB
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 11/10/2009 23:26:27:
On Sun, 2009-10-11 at 18:35 +0200, Joakim Tjernlund wrote:
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 12/10/2009 00:44:56:
On Mon, 2009-10-12 at 00:19 +0200, Joakim Tjernlund wrote:
I hear you, I can remove DTLB error with an add on patch later if that is
OK?
I cannot remove the DARFix though, when I move that to do_page_fault(), I
Rex Feany rfe...@mrv.com wrote on 09/10/2009 02:15:27:
Thus spake Joakim Tjernlund (joakim.tjernl...@transmode.se):
So here we go again. This time I am
fairly confindent I got most things correct :)
Also manged to use even less instructions in the
TLB Miss handlers.
Scott and Rex
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 09/10/2009 02:53:31:
Subject:
Re: [PATCH 2/6] 8xx: Update TLB asm so it behaves as linux mm expects.
On Fri, 2009-10-09 at 00:44 +0200, Joakim Tjernlund wrote:
accessed == 1 and present = 0 is impossible, right?
So basically just
Rex Feany rfe...@mrv.com wrote on 09/10/2009 08:46:49:
Thus spake Joakim Tjernlund (joakim.tjernl...@transmode.se):
Rex Feany rfe...@mrv.com wrote on 09/10/2009 02:15:27:
open(/proc/mounts, O_RDONLY) = 3
fstat64(0x3, 0x7fe7e2a8)= 0
mmap(NULL, 4096
Rex Feany rfe...@mrv.com wrote on 09/10/2009 08:46:49:
Thus spake Joakim Tjernlund (joakim.tjernl...@transmode.se):
Rex Feany rfe...@mrv.com wrote on 09/10/2009 02:15:27:
open(/proc/mounts, O_RDONLY) = 3
fstat64(0x3, 0x7fe7e2a8)= 0
mmap(NULL, 4096, PROT_READ
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
---
arch/powerpc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
---
arch/powerpc/kernel/head_8xx.S | 146 +++-
1 files changed, 145
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
Test for DAR=0x00f0 in DataTLBError and bail
to handle_page_fault().
---
arch/powerpc/kernel/head_8xx.S | 15 ++-
1 files
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 07/10/2009 23:18:05:
On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote:
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
not sure about
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