From: Tang Yuantian
Otherwise there wil be no SCSI device nodes.
Signed-off-by: Shaohui Xie
Signed-off-by: Tang Yuantian
---
arch/powerpc/configs/corenet64_smp_defconfig | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig
b/arch/powerpc/con
From: Tang Yuantian
Each time the CPU switches its frequency, the clock nodes in
DTS are walked through to find proper clock source. This is
very time-consuming, for example, it is up to 500+ us on T4240.
Besides, switching time varies from clock to clock.
To optimize this, each input clock of CP
From: Tang Yuantian
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback functi
From: Tang Yuantian
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback functi
From: Tang Yuantian
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback functi
From: Tang Yuantian
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Poonam Aggrwal
Signed-off-by: Tang Yuantian
---
arch/powerpc/boot/dts/p2020rdb-pc.dts| 96 +
arch/powerpc/boot/dts/p2020rdb-pc.dtsi | 241 ++
arch/powerpc/boot/dts/p2020rd
From: Tang Yuantian
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v4:
- add binding document
- update compatible string
- update the reg property
v3:
- fix typo
From: Tang Yuantian
Basically, this patch does the following:
1. Move the codes of parsing boot parameters from setup-common.c
to driver. In this way, code reader can know directly that
there are boot parameters that can change the timeout.
2. Make boot parameter 'booke_wdt_period' effectiv
From: Tang Yuantian
Main changs include:
- Clarified the clock nodes' version number
- Fixed a issue in example
Singed-off-by: Tang Yuantian
---
v2:
- rename this binding
- rewrite the description
.../bindings/clock/{corenet-clock.txt => qoriq-clock.txt} |
From: Tang Yuantian
config FSL_SOC and CPM do not really depend on PPC_CLOCK. So remove it.
PPC_CLOCK also keeps powerpc archtecture from supporting COMMON_CLK.
Signed-off-by: Tang Yuantian
---
arch/powerpc/Kconfig |1 -
arch/powerpc/platforms/Kconfig |1 -
2 files changed, 0
From: Tang Yuantian
config FSL_SOC and CPM do not really depend on PPC_CLOCK. So remove it.
PPC_CLOCK also keeps powerpc archtecture from supporting COMMON_CLK.
Signed-off-by: Tang Yuantian
---
v2: correct the title
arch/powerpc/Kconfig |1 -
arch/powerpc/platforms/Kconfig |
From: Tang Yuantian
Config FSL_SOC does not depend on PPC_CLOCK anymore since the following
commit got merged: 93abe8e (clk: add non CONFIG_HAVE_CLK routines)
Config CPM does not use PPC_CLOCK either currently. So remove them.
PPC_CLOCK also keeps Freescale PowerPC archtecture from supporting CO
From: Tang Yuantian
Signed-off-by: Tang Yuantian
---
take p5020 for example.
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 44 ++-
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi |2 +
2 files changed, 45 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/d
From: Tang Yuantian
This adds the clock driver support for Freescale E500MC, E5500,
E6500 series SoCs using common clock framework.
Signed-off-by: Tang Yuantian
---
arch/powerpc/platforms/Kconfig.cputype |1 +
drivers/clk/Kconfig|7 +
drivers/clk/Makefile
From: Tang Yuantian
This adds the clock driver for Freescale PowerPC corenet
series SOC using common clock infrastructure.
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
arch/powerpc/platforms/Kconfig.cputype | 1 +
drivers/clk/Kconfig| 7 +
drivers/clk/Makefi
From: Tang Yuantian
The following SOCs will be affected: p2041, p3041, p4080,
p5020, p5040
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 62 -
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 4 ++
arch/powerpc/boot/dts/f
From: Tang Yuantian
Add cpufreq driver for Freescale e500mc, e5500 and e6500 SOCs
which are capable of changing the frequency of CPU dynamically
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
drivers/cpufreq/Kconfig.powerpc | 10 ++
drivers/cpufreq/Makefile | 1
From: Tang Yuantian
Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs
which are capable of changing the frequency of CPU dynamically
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v2:
- change the per_cpu variable to point type
- fixed other issues
driver
From: Tang Yuantian
This adds the clock driver for Freescale PowerPC corenet
series SoCs using common clock infrastructure.
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v2: add the document for device tree clock bindings
.../bindings/clock/freescale-corenet-clock.txt | 67 +++
From: Tang Yuantian
Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs
which are capable of changing the frequency of CPU dynamically
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v3:
- change sizeof(struct name).. to sizeof(*p)
- remove the struct cpufreq_
From: Tang Yuantian
As the function itself says it is caller's responsibility to call the
of_node_put(). So, remove it on success to keep the reference count
correct.
Signed-off-by: Tang Yuantian
---
drivers/of/base.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/of/base.c b/d
From: Tang Yuantian
Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs
which are capable of changing the CPU frequency dynamically
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v4:
- rebase on bleeding-edge branch of Rafael's linux-pm.git
- #define pr_fmt(
From: Tang Yuantian
This adds the clock driver for Freescale PowerPC corenet
series SoCs using common clock infrastructure.
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v3:
- remove the module author and description
v2:
- add the document for device tree clock bindin
From: Tang Yuantian
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
* resend for review
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 62 -
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 4 ++
ar
From: Tang Yuantian
Call of_node_put() only when the out_args is NULL on success,
or the node's reference count will not be correct because the caller
will call of_node_put() again.
Signed-off-by: Tang Yuantian
---
v2:
- modified the title and description. the 1st patch title is:
From: Tang Yuantian
The compatible string of clock is changed from *-2 to *-2.0
on chassis 2. So updated it accordingly.
Signed-off-by: Tang Yuantian
---
drivers/clk/clk-ppc-corenet.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/cl
From: Tang Yuantian
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v2:
- add t4240, b4420, b4860 support
- remove pll/4 clock from p2041, p3041 and p5020 board
arch/powerpc/bo
From: Tang Yuantian
Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs
which are capable of changing the CPU frequency dynamically
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v5:
- enhance the CPU hotplug case
- mask the disallowed CPU frequencies
From: Tang Yuantian
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v3:
- fix typo
v2:
- add t4240, b4420, b4860 support
- remove pll/4 clock from p2041, p3041 and p5020
From: Tang Yuantian
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v5:
- refine the binding document
- update the compatible string
v4:
- add binding document
-
From: Tang Yuantian
Adds the clock bindings for Freescale PowerPC CoreNet platforms
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v6:
- splited the previous patch into 2 parts, one is for binding(this one),
the other is for DTS modification(will submit once this get
From: Tang Yuantian
Adds the clock bindings for Freescale PowerPC CoreNet platforms
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v7:
- refined some properties' definitions
v6:
- splited the previous patch into 2 parts, one is for binding(this one),
the othe
From: Tang Yuantian
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 36 +
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 2 +
arch/powerp
From: Tang Yuantian
Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untou
From: Tang Yuantian
redefine variable clocks_per_pll as a struct member
If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.
Signed-off-by: Tang Yuantian
---
These patches are based on following three patches which are acke
From: Tang Yuantian
Freescale introduced new ARM core-based SoCs which support dynamic
frequency switch feature. DFS on new SoCs are compatible with current
PowerPC CoreNet platforms. In order to support those new platforms,
this driver needs to be updated. The main changes include:
1. Changed t
From: Tang Yuantian
This driver works on all QorIQ platforms which include
ARM-based cores and PPC-based cores.
Rename it in order to represent better.
Signed-off-by: Tang Yuantian
Acked-by: Viresh Kumar
---
v3, v4
- none
v2:
- use -C -M options when format-patch
drivers/cpuf
From: Tang Yuantian
This driver works on all QorIQ platforms which include
ARM-based cores and PPC-based cores.
Rename it in order to represent better.
Signed-off-by: Tang Yuantian
Acked-by: Viresh Kumar
---
v5:
- rebased to 4.0-rc3
- added Kconfig and Makefile entry
v3, v4
From: Tang Yuantian
Freescale introduced new ARM core-based SoCs which support dynamic
frequency switch feature. DFS on new SoCs are compatible with current
PowerPC CoreNet platforms. In order to support those new platforms,
this driver needs to be updated. The main changes include:
1. Changed t
From: Tang Yuantian
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
S
From: Tang Yuantian
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
S
From: Tang Yuantian
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
S
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