On Fri, 2015-04-03 at 18:35 +0800, Shengzhou Liu wrote:
> + rcpm: global-utilities@e2000 {
> + compatible = "fsl,t1023-rcpm", "fsl,qoriq-rcpm-2.0";
> + reg = <0xe2000 0x1000>;
> + };
> +
> + sfp: sfp@e8000 {
> + compatible = "fsl,t1023-sfp";
> +
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Accel
On Mon, 2015-03-30 at 22:32 -0500, Liu Shengzhou-B36685 wrote:
> > > > There are other differences between t1023 an t1024. Where do you
> > > > describe t1024's QE? Where do you describe the DDR and IFC differences?
> > > > can they be detected at runtime? t1024 supports deep sleep, but
> > > >
> > > There are other differences between t1023 an t1024. Where do you
> > > describe t1024's QE? Where do you describe the DDR and IFC differences?
> > > can they be detected at runtime? t1024 supports deep sleep, but
> > > t1023 doesn't -- yet you label both chips as having t1024 rcpm.
> > >
>
On Mon, 2015-03-30 at 06:08 -0500, Liu Shengzhou-B36685 wrote:
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Friday, January 30, 2015 9:20 AM
> > To: Liu Shengzhou-B36685
> > Cc: linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [1/4] powerp
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, January 30, 2015 9:20 AM
> To: Liu Shengzhou-B36685
> Cc: linuxppc-dev@lists.ozlabs.org
> Subject: Re: [1/4] powerpc/fsl-booke: Add device tree support for
> T1024/T1023 SoC
>
> On Thu, Jan 2
On Thu, Jan 29, 2015 at 03:52:24PM +0800, Shengzhou Liu wrote:
> +/include/ "qoriq-i2c-0.dtsi"
> +/include/ "qoriq-i2c-1.dtsi"
t1023 has only three i2c controllers -- where do you disable the fourth?
> +/include/ "t1023si-post.dtsi"
> +
> +/ {
> + aliases {
> + vga = &display;
>
On Thu, Jan 29, 2015 at 03:52:24PM +0800, Shengzhou Liu wrote:
> + corenet-cf@18000 {
> + compatible = "fsl,corenet2-cf";
While the damage has already been done by the t1040 device tree, this is
not 100% compatible with what's on t4240. I'm not sure if it's worth
doing anything ab
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Accel
