On Thu, Mar 27, 2014 at 09:41:20AM +, David Laight wrote:
> From: Mark Brown
> > The trace is already conditional? I'd also expect to see the driver
> > only acknowledging sources it knows about and only reporting that the
> > interrupt was handled if it saw one of them - right now all interr
On Thu, Mar 27, 2014 at 11:57:27AM +0800, Nicolin Chen wrote:
> On Thu, Mar 27, 2014 at 12:06:53PM +0800, Xiubo Li-B47053 wrote:
> > I have checked in the Vybrid and LS1 SoC datasheets, and they are all the
> > Same as above, and nothing else.
> > Have I missed ?
> What i.MX IC team told me is S
From: Mark Brown
> On Wed, Mar 26, 2014 at 11:59:53AM +, David Laight wrote:
> > From: Nicolin Chen
>
> > > + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> > > + regmap_write(sai->regmap, FSL_SAI_TCSR, xcsr);
>
> > Assuming these are 'write to clear' bits, you might want
> > to make the wr
> > So let's just ignore the clearance of these bits in isr().
> >
> > +
> > SAI Transmit Control Register (I2S1_TCSR) : 32 : R/W : _h
>
> I'm talking about FWF and FRF bits, not TCSR as a register.
>
> > -
> >
> > I have checked in the Vybrid and LS1 SoC datasheets, and they are
On Thu, Mar 27, 2014 at 12:06:53PM +0800, Xiubo Li-B47053 wrote:
> > > > > > > > + if (xcsr & FSL_SAI_CSR_FWF)
> > > > > > > > + dev_dbg(dev, "isr: Enabled transmit FIFO is
> > > > > > > > empty\n");
> > > > > > > > +
> > > > > > > > + if (xcsr & FSL_SAI_CSR_FRF)
> > > >
> > > > > > > + if (xcsr & FSL_SAI_CSR_FWF)
> > > > > > > + dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
> > > > > > > +
> > > > > > > + if (xcsr & FSL_SAI_CSR_FRF)
> > > > > > > + dev_dbg(dev, "isr: Transmit FIFO watermark has been
> > > reached\n");
> > > > > > > +
> > >
On Thu, Mar 27, 2014 at 11:41:02AM +0800, Xiubo Li-B47053 wrote:
>
> > Subject: Re: [PATCH] ASoC: fsl_sai: Add isr to deal with error flag
> >
> > On Thu, Mar 27, 2014 at 10:53:50AM +0800, Xiubo Li-B47053 wrote:
> > > > On Thu, Mar 27, 2014 at 10:13:
> Subject: Re: [PATCH] ASoC: fsl_sai: Add isr to deal with error flag
>
> On Thu, Mar 27, 2014 at 10:53:50AM +0800, Xiubo Li-B47053 wrote:
> > > On Thu, Mar 27, 2014 at 10:13:48AM +0800, Xiubo Li-B47053 wrote:
> > > > > + regmap_read
On Thu, Mar 27, 2014 at 10:53:50AM +0800, Xiubo Li-B47053 wrote:
> > On Thu, Mar 27, 2014 at 10:13:48AM +0800, Xiubo Li-B47053 wrote:
> > > > + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> > > > + regmap_write(sai->regmap, FSL_SAI_TCSR, xcsr);
> > > > +
> > > > + if (xcsr & FS
> On Thu, Mar 27, 2014 at 10:13:48AM +0800, Xiubo Li-B47053 wrote:
> > > + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> > > + regmap_write(sai->regmap, FSL_SAI_TCSR, xcsr);
> > > +
> > > + if (xcsr & FSL_SAI_CSR_WSF)
> > > + dev_dbg(dev, "isr: Start of Tx word detected\n");
> > > +
> >
On Thu, Mar 27, 2014 at 10:13:48AM +0800, Xiubo Li-B47053 wrote:
> > + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> > + regmap_write(sai->regmap, FSL_SAI_TCSR, xcsr);
> > +
> > + if (xcsr & FSL_SAI_CSR_WSF)
> > + dev_dbg(dev, "isr: Start of Tx word detected\n");
> > +
> > + if
On Thu, Mar 27, 2014 at 01:14:24AM +, Mark Brown wrote:
> On Wed, Mar 26, 2014 at 11:59:53AM +, David Laight wrote:
> > From: Nicolin Chen
>
> > > + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> > > + regmap_write(sai->regmap, FSL_SAI_TCSR, xcsr);
>
> > Assuming these are 'write to cle
> + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> + regmap_write(sai->regmap, FSL_SAI_TCSR, xcsr);
> +
> + if (xcsr & FSL_SAI_CSR_WSF)
> + dev_dbg(dev, "isr: Start of Tx word detected\n");
> +
> + if (xcsr & FSL_SAI_CSR_SEF)
> + dev_dbg(dev, "isr: Tx Frame
On Wed, Mar 26, 2014 at 11:59:53AM +, David Laight wrote:
> From: Nicolin Chen
> > + regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
> > + regmap_write(sai->regmap, FSL_SAI_TCSR, xcsr);
> Assuming these are 'write to clear' bits, you might want
> to make the write (above) and all the trace
From: Nicolin Chen
> It's quite cricial to clear error flags because SAI might hang if getting
> FIFO underrun during playback (I haven't confirmed the same issue on Rx
> overflow though).
>
> So this patch enables those irq and adds isr() to clear the flags so as to
> keep playback entirely safe.
It's quite cricial to clear error flags because SAI might hang if getting
FIFO underrun during playback (I haven't confirmed the same issue on Rx
overflow though).
So this patch enables those irq and adds isr() to clear the flags so as to
keep playback entirely safe.
Signed-off-by: Nicolin Chen
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