The spdif root clock may be used by other module or defined with
CLK_SET_RATE_GATE, so we can't change the clock rate in driver.
In this patch remove the clk_set_rate and clk_round_rate to protect the
clock.
Signed-off-by: Shengjiu Wang shengjiu.w...@freescale.com
---
sound/soc/fsl/fsl_spdif.c |
On Tue, Sep 16, 2014 at 07:46:34PM +0800, Shengjiu Wang wrote:
The spdif root clock may be used by other module or defined with
CLK_SET_RATE_GATE, so we can't change the clock rate in driver.
In this patch remove the clk_set_rate and clk_round_rate to protect the
clock.
It's a quite
On Tue, Sep 16, 2014 at 11:19:28AM -0700, Nicolin Chen wrote:
So I think, if it's a shared clock, we should not define it as a
rate-changeable one in the SoC level, as we might still have some
SoCs provide a dedicated clock to S/PDIF so as to get the maximum
range of clock support for users.
On Wed, Sep 17, 2014 at 09:32:52AM +0800, Shawn Guo wrote:
On Tue, Sep 16, 2014 at 11:19:28AM -0700, Nicolin Chen wrote:
On Tue, Sep 16, 2014 at 07:46:34PM +0800, Shengjiu Wang wrote:
The spdif root clock may be used by other module or defined with
CLK_SET_RATE_GATE, so we can't change
On Tue, Sep 16, 2014 at 07:24:40PM -0700, Nicolin Chen wrote:
It's not supported in the clock API or just not implemented in our
code? Can we just register a clock without CLK_SET_RATE_PARENT to
achieve the purpose? (We are just trying to fix those PRED and PODF
dividers when the driver calls
On Wed, Sep 17, 2014 at 10:31:28AM +0800, Shawn Guo wrote:
On Tue, Sep 16, 2014 at 07:24:40PM -0700, Nicolin Chen wrote:
It's not supported in the clock API or just not implemented in our
code? Can we just register a clock without CLK_SET_RATE_PARENT to
achieve the purpose? (We are just
On Tue, Sep 16, 2014 at 11:19:28AM -0700, Nicolin Chen wrote:
On Tue, Sep 16, 2014 at 07:46:34PM +0800, Shengjiu Wang wrote:
The spdif root clock may be used by other module or defined with
CLK_SET_RATE_GATE, so we can't change the clock rate in driver.
In this patch remove the clk_set_rate
