On Tue, 16 Dec 2008, Benjamin Herrenschmidt wrote:
> On Mon, 2008-12-15 at 17:11 -0800, Trent Piepho wrote:
>> Shame, as it provides a huge speed up. I suppose an alternative would be
>> to map the chip twice at different physical addresses, by just configuring
>> the chip select to be twice the s
On Mon, 2008-12-15 at 17:11 -0800, Trent Piepho wrote:
> Shame, as it provides a huge speed up. I suppose an alternative would be
> to map the chip twice at different physical addresses, by just configuring
> the chip select to be twice the size it should be, and giving them
> different cacheabili
On Mon, 2008-12-15 at 10:25 -0800, Trent Piepho wrote:
> The MTD system supports operation where a direct mapped flash chip is
> mapped twice. The normal mapping is a standard ioremap(), which is
> non-cached and guarded on powerpc. The second mapping is used only for
> reads and can be cached an
On Tue, 16 Dec 2008, Paul Mackerras wrote:
> Trent Piepho writes:
>> The MTD system supports operation where a direct mapped flash chip is
>> mapped twice. The normal mapping is a standard ioremap(), which is
>> non-cached and guarded on powerpc. The second mapping is used only for
>> reads and c
Trent Piepho writes:
> The MTD system supports operation where a direct mapped flash chip is
> mapped twice. The normal mapping is a standard ioremap(), which is
> non-cached and guarded on powerpc. The second mapping is used only for
> reads and can be cached and non-guarded. Currently, only t
On Mon, 15 Dec 2008, Josh Boyer wrote:
>
> Did you actually change anything in this version when compared to the
> version you sent out last week? If not, is there a reason you sent it
> again without flagging it as a resend?
I sent it out last week? I'm trying to tie up loose ends before I leav
On Mon, 15 Dec 2008 10:25:18 -0800
Trent Piepho wrote:
> The MTD system supports operation where a direct mapped flash chip is
> mapped twice. The normal mapping is a standard ioremap(), which is
> non-cached and guarded on powerpc. The second mapping is used only for
> reads and can be cached
The MTD system supports operation where a direct mapped flash chip is
mapped twice. The normal mapping is a standard ioremap(), which is
non-cached and guarded on powerpc. The second mapping is used only for
reads and can be cached and non-guarded. Currently, only the pxa2xx
mapping driver makes
